a commercially available digitization system fotiou andreas andreas fotiou

A commercially available A commercially available digitization systemdigitization system

Fotiou Andreas

Andreas Fotiou

2

General features

Technical measurements

Tests with Optical Modules

Conclusions

3 Key features of BenKey features of BenNUEYNUEY CardCard

Up to 12 channels with12-bit 250MSPS analog capture per channel.

64-bit/33MHz PCI Interface.

Four Gigabit Ethernet ports with dedicated Quad PHY device.

8 Mbytes of ZBT Memory.

Low consumption.

4BenNUEY Functional BenNUEY Functional DiagramDiagram

By Nallatech company

5 Key features of BenADC Key features of BenADC cardcard

Quad 12-bit 250MSPS analog capture channels.

On-board Xilinx Virtex-4 User FPGA (supporting SX55, LX100 or LX160).

±725 mV maximum input signal range.

Two dedicated onboard module oscillators:– 200 and 250 MHz Oscillators.

External clock input.

16MBytes of DDR-II SRAM.

6

BenADC Physical Layout (Top)BenADC Physical Layout (Top)

By Nallatech company

7

BenADC Physical Layout (BenADC Physical Layout (BottomBottom))

By Nallatech company

8BenNUEY Physical Layout BenNUEY Physical Layout (Top)(Top)

By Nallatech company

9BenNUEY Physical Layout BenNUEY Physical Layout (Bottom)(Bottom)

By Nallatech company

10The clock management The clock management systemsystem

By Nallatech company

11

General features

Technical measurements

Tests with Optical Modules

Conclusions

12

Type of measurements Type of measurements

Distortion measurements- Amplitude distortion

- Rise time distortion

Power consumption measurements The host of the system was a pentium m based

PC.

13

Block diagram of the setupBlock diagram of the setup

Negative triangular pulses of various amplitudes with 17ns FWHM were used.

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Amplitude distortionAmplitude distortion

15

Rise time distortionRise time distortion

16System Power System Power ConsumptionConsumption

Status Card Consumption(Watt)

Idle mode 91 card sampling (4 CH)

37

2 cards sampling (8 CH)

48

3 cards sampling (12 CH)

59*

* Estimated value* Estimated value

17

General features

Technical measurements

Tests with Optical Modules

Conclusions

18

A trigger algorithm has been implemented in VHDL. The basic parameters are:

Threshold Coincidence window Majority Total recording time Pro-event recording time

Most of the parameters can change via software (Tcl, C).

Coincidence window length requires firmware modifications.

Trigger implementationTrigger implementation

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• Coincidence window: 60 ns (15 samples).

• Total recording time: 512 ns (128 samples).

• Pro-event recording time: 64ns (16 samples).

• Different majority number and threshold levels were applied.

Test run parameters Test run parameters

20Majority 2, threshold -30 Majority 2, threshold -30 mV mV

21Majority 3, threshold -30 Majority 3, threshold -30 mV mV

22

Majority 4, threshold -30 mVMajority 4, threshold -30 mV

23

Majority 2, threshold -120 mVMajority 2, threshold -120 mV

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Majority 3, threshold -120 mVMajority 3, threshold -120 mV

25

General features

Technical measurements

Tests with Optical Modules

Conclusions

26

ConclusionsConclusions

• Simultaneous 12-channel 250MSPS continuous digitizing system

• Dead time free between triggers

• Less than 15% distortion in rise time and less than 3% in amplitude

• Low power consumption

27

ThanksThanks

Special thanks to the Nallatech company, which loaned us this card for 3 months.

Company’s website: www.nallatech.com