aip introduction
DESCRIPTION
analog integrated circuit ppt in nthuTRANSCRIPT
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Chapter 10
1
Operational Amplifier Circuits
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10.1
2
The Two-Stage CMOS Op Amp
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The Two-Stage CMOS Op Amp! The circuit consists of two stages:
" The first stage is formed by the differential pair ." The second stage consists of the commonsource and its current-source
load .
1 2Q Q6Q
7Q
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3Figure 10.1
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The Two-Stage CMOS Op Amp! The differential pair is biased by current source , which is one of
the two output transistors of the current mirror formed by .! The current mirror is fed by reference current .
5Q5 7 8, ,Q Q Q
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4Figure 10.1
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The Two-Stage CMOS Op Amp! is Miller-multiplied by the gain of the second stage, and the resu-
lting capacitance at the input of the second stage interacts with the total resistance there to provide the required dominant pole.
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5Figure 10.1
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The Two-Stage CMOS Op Amp! The systematic output dc offset voltage can be eliminated by sizing
the transistors so as to satisfy the following constraint:6 7
4 5
( ) ( )2
( ) ( )W W
L LW W
L L=
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6Figure 10.1
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Input Common-Mode Range! The lowest value of has to
be sufficiently large to keep and in saturation.
! should not be lower than the voltage at the drain of by more than .
ICMV1Q
2QICMV
1QtpV
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by more than . ! Thus,
or
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tpV
3ICM SS tn OV tpV V V V V + +
(min)ICMV
3ICM SS GS tpV V V V +
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Input Common-Mode Range! The highest value of sho-
uld ensure that remains in saturation.
! should not decrease below ! So,
ICMV5Q
5SDV 5OVV
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or equivalently
! Thus, the range of is
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5 1ICM DD OV SGV V V V
5 1ICM DD OV tp OVV V V V V
(max)ICMV
ICMV
3 5 1SS tn OV tp ICM DD OV tp OVV V V V V V V V V + +
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Output Swing! The signal swing allowed at
the output of the op amp is limited at the lower end by keeping saturated and at the upper end by keeping saturated.
6Q7Q
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saturated.! Thus,
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6 7SS OV O DD OVV V v V V +
(max)Ov
(min)Ov
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Voltage Gain! Each of the two stages is modeled as a transconductance amplifier.
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Figure 10.2
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Voltage Gain! The input resistance is infinite:
! The first-stage transconductance is equal to and :
! and are operated at equal bias current and overdrive voltage:
inR = 1mG 1Q 2Q
1 1 2m m mG g g= =1Q 2Q
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! and are operated at equal bias current and overdrive voltage:
! represents the output resistance of the first stage:, ,
1Q 2Q
11 1
2( )2m
OV OV
I IGV V
= =
1R
1 2 4o oR r r= !2
2
2
Ao
Vr I=
44
2
Ao
Vr I=
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Voltage Gain! The dc gain of the first stage is
1 1 1
1 2 04
1 2 4
( )2 1 1
m
m o
OV A A
A G Rg r r
V V V
=
=
= +
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! The second-stage transconductance is
! represents the output resistance of the second stage:
2mG
62 6
6
2 Dm m
OV
IG gV
= =
2R
7 762 6 7 6 7
6 7 6
, ,A AA
o o o o
D D D
V VVR r r r rI I I
= = = =!
1 2 4OV A AV V V
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Voltage Gain! The voltage gain of the second stage is
2 2 2
6 6 7
6 6 7
( )2 1 1
m
m o o
OV A A
A G Rg r r
V V V
=
=
= +
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! The overall dc voltage gain is the product :
! The output resistance of the op amp is equal to :
6 6 7OV A AV V V 1 2A A
1 2
1 1 2 2
1 2 4 6 6 7( ) ( )
v
m m
m o o m o o
A A AG R G Rg r r g r r
=
=
= ! !
2R
2 6 7( )o o oR R r r= = !
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Common-Mode Rejection Ratio (CMRR)! The CMRR of the two stage op amp is determined by the first stage,
so the CMRR is
! is the output resistance of the bias current source .[ ][ ]1 02 04 3CMRR ( ) 2m m SSg r r g R= !
SSR 5Q
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! Since is proportional to ,the CMRR is increased if long channels are used, and the transistors are operated at low overdrive voltage.
m og r 'A OV A OVV V V L V=
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Frequency Response! Consider the equivalent circuit in Fig.10.2.! : total capacitance at the output node of the first stage
! : total capacitance at the output node of the op amp, including
1C1 2 2 4 4 6gd db gd db gsC C C C C C= + + + +
2C LC
C C C C C= + + +
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2 6 7 7db db gd LC C C C C= + + +
6C gd CC C C+
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Frequency Response! The circuit has two poles and a positive real-axis zero:
11 2 2
12P m C
fR G R C
22
22m
PGf
C
2 2 2 2(1 )m C m CG R C G R C+
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! is the dominant pole formed by the Miller-multiplied and ! The unity-gain frequency is
2
2
2m
ZC
GfC
1Pf CC 1Rtf
1
1
2
t v P
m
C
f A fG
C
=
=
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Frequency Response! must lower than and ,so the design must satisfy the two con-
ditions:
! The uniform -20-db/decade gain rolloff obtained at frequencies the op amp can be represented by the simplified equivalent circuit in
tf 2Pf Zf1 2
1 22
,m m
m m
C
G G G GC C
<
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!
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if the current mirror turns off, the output distortion increases.
Finally, the relationship between and istSR f
12 t OVSR f V=
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Example 10.2
' 2 ' 2 '
Consider a design of the folded-cascode op amp of Fig. 10.9 for which 200 A,250 A, and for all transistors is 0.25V. Assume that the fabrication pro-
cess provides 100 A V , 40 A V , B OV
n p A
II V
k k V
=
=
= = 20 V m. 2.5V,
and 0.75V. Let all transistors have 1m, and assume that 5pF.Find , , , for all transistors, the allowable range of and output swing.
DD SS
t L
V V
V L CI g r W L V
= = =
= = =
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Find , , , for all transistors, the allowable range of and output swing. Determine the values of
D m o ICMI g r W L VA , , and .
What is the power dissipation of the op amp?v t Pf f SR
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Solution! The transconductance of each device is
2 2found using 0.25
D Dm
OV
I IgV
= =
' 2
220,
A Dio
iD D OV
V IWr
I I L k V
= = =
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iD D OVI I L k V
The result are as follows:
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11100 100 150 150 150 150 150 150 250 250 200
0.8 0.8 1.2 1.2 1.2 1.2 1.2 1.2 2.0 2.0 1.6
200 200 133 133 133 133 133 133 80 80 100
32 32 120 120 48 48 48 48 200 200 64
( A)DI
(mA V)mg
( )or k
W L
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Solution!
!
!
For all transistors, 160V V, 1.0Vm o GSg r V= =The range of is ICMV 1.25V 3VICMV The output swing is 1.25V 2VOv
4 160(200 80) 9.14MoR = = !6 21.28MoR =
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50
!
!
!
6 21.28MoR =
3 60.8 10 6.4 105120 V V
v m oA G R
= =
=
3
120.8 10 25.5MHz
2 5 10tf
= =
25.5MHz 5kHz5120
tp
v
ffA
= = =
4 6 6.4Mo o oR R R= =!
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Solution! The slew rate is
6
12200 10 40V s5 10L
ISRC
= = =
The total current is 500A=0.5mA, and the total supply voltage is 5V,thus
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5 0.5 2.5mWDP = =
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Increasing the Input Common-Mode Range: Rail-to-Rail Input Operation
!
!
We have found that the upper limit on the input common-mode range exceeds thesupply voltage , the magnitude of lower limit is significantly lower than .DD SSV V
The opposite situation occurs if the input differential amplifier is made up of PMOS.
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52
!
!
It follows that an NMOS and a PMOS differential pair placed in parallel wouldprovide an input stage with a common-mode range that exceeds the power supplyvoltage in both directions.
Figure. 10.11 is the circuit which is known as rail-to-rail input operation.
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Increasing the Input Common-Mode Range: Rail-to-Rail Input Operation
!
!
( )1 2 3 4.
Each of the current increments indica-ted is equal to 2 , wherem id
m m m m m
G VG g g g g= = = =
.
Thus, the total current feeding each ofthe two ouput nodes will be
m idG V
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!
53
.m id
So, 2o m o idV G R V=
The voltage gain will be
2v m oA G R=
Figure 10.11
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Increasing the Output Voltage Range: The Wide-Swing Current Mirror
! The cascode current mirror limits the negative swing to 2 above .OV t SSV V V + The cascode mirror reduces the voltage swing by volts. This point is further illustrated in Figure 10.12(a).
tV
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Figure 10.12
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Increasing the Output Voltage Range: The Wide-Swing Current Mirror
!
!
3
3
To permit the output voltage at the drain of to swing as low as 2 , we mustlower the voltage at the gate of from 2 2 to 2 .
OV
t OV t OV
Q VQ V V V V+ +
Fig. 10.12(b) is the modified mirror circuit, which is known as the wide-swing curr-ent mirror.
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55
!
!
ent mirror.
3
3
The gate of is now connected to a bias voltage = 2 .Thus the output voltage can go down to 2 with still in saturation.
BIAS t OV
OV
Q V V VV Q
+
1 1Also, the voltage at the drain of is now and thus is operating at the edgeof saturation.
OVQ V Q
-
10.3
56
The741 Op-Amp Circuit
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The 741 Op-Amp Circuit
Stage 1
Stage 3
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Stage 2
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Bias Circuit!
!
11 12 5
The bias current is generated by, , and .
REFIQ Q R
11 10 4 10
Using a Widlar current source formedby , , and , generates thebias current of the first stage.
Q Q R Q
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!
1.
2.
!
58
12 13 and form a two-output currentmirror: Q Q
13
17
provides bias current and actsas a current-source load for .
BQQ
13 provides bias current for theoutput stage of the op-amp.
AQ
18 19
14 20
The purpose of and is to establish two drops betweenthe bases of and .
BE
Q QV
Q Q
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The Input Stage!
!
1 7
8 9 10
The input stage consists of through ,with biasing performed by , , and .
Q QQ Q Q
5 6 7 1 2 3, , and and , , and formthe load circuit of the input stage.Q Q Q R R R
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!
!
59
3 4
Level shifting is done in the first stageusing the and .pnp Q Q
3 4
1 2
The transistors and canprotect the input-stage transistors
and against emitter-base jun-ction breakdown.
pnp Q Q
Q Q
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The Second Stage!
!
16
17 13 8 9
The second stage is composed of ,, , , and .B
QQ Q R R
16The emitter follower can give thesecond stage a high input resistance,
Q
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!
!
60
second stage a high input resistance, and can also minimize the loading on theinput stage and avoid loss of gain.
17
13
acts as a CE amplifier with a 100resistor in the emitter. Its load is composed of the high output resistance .B
QQ
17The output of the second stage is taken at the collector of . is connected in the feedback path of the second stage to provide frequency
compesation using the Miller-cmpensation technique.C
QC
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The Output Stage!
!
The purpose of the output stage is toprovide the amplifier with a low ouputresistance.
14 20
The output stage of the 741 consists of thecomplementary pair and .Q Q
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!
!
61
14 20
18 19
13 14 20
and are fed by current source and bias the and .A
Q QQ Q Q
23 acts as an emitter follower, thusminimizing the loading effect of theoutput stage on the second stage.
Q
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Device Parameters!
!
For the standard npn and pnp, the following parameters will be used:
14
14
: 10 A, 200, 125V: 10 A, 50, 50V
S A
S A
npn I Vpnp I V
= = =
= = =
13 13 13 will be assume to be equivalent to two transistors, and , with parallelA BQ Q Q
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62
!
!
13 13 13 will be assume to be equivalent to two transistors, and , with parallelbase-emitter junctions and haveing following saturation currents:
A BQ Q Q
14 140.25 10 A, 0.75 10 ASA SBI I
= =
14 20 and will be assumed to each have an area three times that of a standard device.Q Q
-
10.4
63
DC Analysis of the741
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Reference Bias Current! With reference to Fig. 10.13, we can write
12 11
5
( )CC EB BE EEREF
V V V VIR
=
11 12For 15V and 0.7V, CC EE BE EBV V V V= = =
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11 12
we have 0.73mA.CC EE BE EB
REFI =
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Input-Stage Bias! Fig. 10.14 is the Widlar current source that biases the input stage.
10Assume to be large, we have11 10 10 4BE BE CV V I R =
10 410
ln REFT CC
IV I RI
=
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10CI
10 11 10Assumed that , we can get 19A.S S CI I I= =
Figure 10.14
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Input-Stage Bias! From symmetry, 1 2C CI I=
3 4E EI I I=
92
1 2C PII = +
102 CI I
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!
66
102 CI I
10 19A, thus 9.5ACI I=
1 2 3 4So, 9.5AC C C CI I I I= = =
1 4 8 9
10
through , , and from anegative-feedback loop, which worksto stabilize the value of at approxima-tely 2.C
Q Q Q Q
II
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Input-Stage Bias! 3 4This part is fed by C CI I I=
5 6C CI I=
5 3C CI I I
6 4C CI I I 7 16neglect and B BI I
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!
67
6 27 7
3
2 BEC E
N
V IRII IR+
= +
7The bias current of can be determ-ined from
Q
6 lnBE TS
IV VI
=
146Substituing 10 A and 9.5A results in 517mV.S BEI I V
= = =
7Thus, at approximately 0.05A is negligible.BI
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Input Bias and Offset Currents! The input bias current of an op amp is defined as
1 2
2B B
BI II +=
For 741,
BN
II =
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68
NUsing 200, yields 47.5nAN BI = =This value is reasonably small and is typical of general-purpose op amps that use BJTs in the input stage.
Given the value of the mismatch, the input offset current is defined as1 2OS B BI I I=
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Second-Stage Bias!
23 17
13
If we neglect the , the is approximately equal to the current supplied by current source .
B C
B
I IQ
13 0.75C B REFI I assume that 1P 13 17Thus, 550A and 550A.C B CI I= =
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1717 ln 618mVCBE T
S
IV VI
= =
17 8 1716 16 17
9
So, E BEC E BI R VI I I
R+
= +
16This caculation yields =16.2A.CI
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Output-Stage Bias! 23 23 0.25 180AC E REFI I I= =
23 180 50 3.6A, which is negligible.BI = =
18So, 180 15 165AEI = =
18
10
Assume that is 0.6V, we can deter-mine the current in as 15A.
BEVR
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70
18So, 180 15 165AEI = =
18 18 165AC EI I =
19 19 15.8AC EI I =
1919 ln 530mVCBE T
S
IV VI
= =
18 19 588 530 1.118VBB BE BEV V V= + = + =
14 20
14 20
ln lnC CBB T TS S
I IV V VI I
= +
1414 20 14 20Substituing 3 10 A, so that 154A.S S C CI I I I
= = = =
-
10.5
71
Small-Signal Analysis of the 741
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The Input Stage!
4i
e
e
vir
=
25mV 2.63k9.5A
Te
Vr
I= = =
( )( )
4 14 200 1 2.63
id N eR r= += +
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!
72
( )4 200 1 2.632.1M
= +
=
2o ei i=
1 2o
m
i e
iGv r
=
1
Substituing 2.63k and 1 yields 1 5.26 mA V.
e
m
r
G=
=
Figure 10.19
Figure 10.18
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The Input Stage! Using the equation :
( )1o o m eR r g R r= + !Substituing 2.63k and
, where 50Vand 9.5A, and neglecting , results
e e
o A A
R rr V I VI r
= = = =
=
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!
73
4
9.5A, and neglecting , resultsin 10.5M .o
I rR
=
=
6 2
6
can be determine with .Thus 18.2M .
o e
o
R R RR
=
4 6
1
Combine and in parallel,the output resistance of input stageis 6.7M .
o o
o
R R
R =
Figure 10.20
Figure 10.21
Figure 10.21 shows the equivalent circuit of the input stage.
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Example10.3
1 2
We wish to find the input offset voltage resulting from a 2% mismatch between the resistances and in Fig. 10.13.R R
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74
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Solution! ( )( )5 6BE BEV IR V I I R R+ = + +
( )5 6BE BEV V I R I R R = + 5 6BE BE eV V Ir
I RI R R r
=
+ +
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75
eI R R r+ +
3
Substituing 1k and 2.63k shows that 5.5 10 .
eR r
I I= =
= 3
1 1
5.5 10So, OSm m
I IVG G
= =
1Substituting =9.5A and =1 5.26 mA V,mI G
0.3mVOSV
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Example10.4It is required to find the CMRR of the 741 input stage. Assume tha the circuit is balancdeexcept for mismatches in the current-mirror load that result in an error in the mirror'scurrent-transfer ra
m
tio; that is, the ratio becomes(1- ).m
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76
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Solution!
9 10o o oR R R= !
22 icmP o
viiR+ =
2icm
o
viR
assume 1P
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77
o
o mi i=
2
o mmcm
icm icm
m
o
i iGv v
R
=
=
11CMRR= 2m m o m
mcm
G g RG
=
( )1 9 10So, CMRR= 2 m o o mg R R !
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The Second Stage! Input Resistance
( ) ( )( ){ }2 16 16 9 17 17 81 1i e eR r R r R = + + + + !Transconductance
Shortcircuiting the output terminal of the second stage to ground.
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78
Figure 10.24
of the second stage to ground.17
1717 8
bc
e
vir R
=
+
( )( )
9 1717 2
9 17 16
ib i
i e
R Rv v
R R r=
+
!!
( )( )17 17 17 81i eR r R= + +17
22
cm
i
iGv
2For the 741 parameter values, 6.5mA V.mG =Figure 10.25?
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The Second Stage!
( )2 13 17o o B oR R R= !Output Resistance
13 13o B o BR r=
13For the 741 component value we obtain 90.9k .o BR =
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79
Figure 10.26
17Since the base resistance of is relatively small, we can assumethat the base is grounded.
Q
17For our case, the result is 787k.oR
13 17 2Combining and in parallel yields 81k.o B o oR R R =
-
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Thvenin Equivalent Circuit
2 2
The second-stage equivalent circuit can be converted to the Th venin form, as Figure 10.27.The stage open-circuit voltage gain is - .m o
G R
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80
Figure 10.27
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The Output Stage! Output Voltage Limits
(max) 14O CC CEsat BEv V V V=
13limited by the saturation of AQ
(min) 23 20O EE CEsat EB EBv V V V V= + + +
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81
(min) 23 20O EE CEsat EB EBv V V V V= + + +
17limited by the saturation of Q
Figure 10.28
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The Output Stage!
2 2 2 2o m o iv G R v=
Small-Signal Model
3 32 2 2
2 3 2
i inm o
i in o
v RA G Rv R R
= + Figure 10.29
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82
23
The total resistance in the emitter of is 100k 280k or 74k .Q !
3 23So, 74kinR 23 3For 50, 3.7M .inR =
32
ovo
o
vGv
= ( )LR =
14 20
23 3
With , the gain of or will be nearly unity. Also, the emitter resistance of will be very large. We thus conclude that 1.
L
vo
R Q QQ G
=
-
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The Output Stage! 223 23
23 1o
o e
RR r= ++2 23
23 23
Substituting 81k , 50, and 25 0.18 139 yields 1.73k
o
e o
Rr R
= == = =
13 23Since alone is much larger than ,o A or R
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83
Figure 10.30
13 23
20
23
the effective resistance at the base of is equal to .
o A o
o
QR
Now we can find as outR
2320
20 1o
out e
RR r= ++20For 50, 34outR = =
The output resistance of the 741 is typically 75 .
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The Output Stage!
6 15 14
14 6
and limits the current that would flow out of in the event of s short circuit.If the current in the emitter of exceeds about 20mA, the voltage drop across exceeds 540mV, which turns
R Q QQ R
15 on.Q
Output Short- Circuit Protection
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84
exceeds 540mV, which turns 1515 13
14
on.
As turns on, its collector robs some of the current supplied by , thus reducingthe base current of .This mechanism thus limits the maximum current that the op amp can source to about
A
QQ Q
Q
20mA.
-
10.6
85
Gain, Frequency Response, and Slew Rate of the 741
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Small-Signal Gain!
( )( )
2 2
2 2
1 1 2 2 2 3
o i o o
i i i o
Lm o i m o vo
L out
v v v v
v v v v
RG R R G R GR R
=
=
+!
Thus,v
=
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86
476.1 ( 526.5) 0.97
243147 V V107.7dB
oo
i
vAv
=
=
Figure 10.31
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Frequency Response!
16
From Miller's theorem, the effective capacitance due to at the base of
isCC
Q ( )21in CC C A= +2 515, results in 15480pF.inA C= =
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87
1 2
6.7M 4M 2.5Mt o iR R R== =
!!
Thus, the dominant pole is Pf1 4.1Hz
2P in tf
C R= =
0 3dB
243147 4.1 1MHztf A f=
=
Figure 10.32
assume that all the other poles are at very high frequency.
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A Simplified Model! 1
( )( ) ( )o m
i C
V s GA sV s sC
=
1( ) mC
GA j j C =
The magnitude of gain becomes unity at = ,
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88
Figure 10.33The magnitude of gain becomes unity at = ,where
t
1mt
C
GC
=
1Sustituting 1 5.26mA V and 30pF yields m CG C= =
1MHz2
ttf
=
-
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Slew Rate!
Figure 10.34
Consider the unity-gain follower of Fig. 10.34 with a step of 10V applied at the input.
This large signal causes the input stage to be overdriven.
Rather, half the stage cuts off and the other half conducts all the current
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89
So, the SR is given by
Figure 10.34half conducts all the current
Thus, we can see that the output voltage will be a ramp with a slope of 2 :CI C
2( )OC
Iv t t
C=
Figure 10.35
2C
ISRC
=
For the 741, 9.5A and =30pF, resulting in 0.63V s
CI CSR
=
=
-
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Relationship Between ft and SR!
1
2t
m
ISRG
=
1
4t
m
ISRg
=
1mT
IgV
=
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90
T
4 T tSR V =For the 741,
3 64 25 10 2 10 0.63V sSR = =
There is a relationship between SR and , which ist
tSR a=
1
where is the constant of proportionality relating the transconductance of the first stage , to the total bias current of the input differential stage.m
a
G
-
10.7
91
Modern Techniques for the Design of BJT Op Amps
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Special Performance Requirements! Many modern BJT op amps are required to operate from a single power supply of only
2V to 3V.This is done for the following reasons:
1. Modern small-feature-size IC fabrication technologies require low power-supply voltages.
2. Compatibility must be achieved with other parts of the system that use low-voltage supplies.
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92Figure 10.36
3. Power dissipation must be minimized, especially for battery-operated equipment.
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Special Performance Requirements! Consider first the inverting op-amp.
Since the positive input terminal is connected to ground, ground voltage has to be withinthe allowable input common-mode range.The input common-mode range should extend below the negative-supply rail.
Consider the unity-gain voltage follower.
The input common-mode voltage is equal to the signal .v
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93 Figure 10.37
The input common-mode voltage is equal to the signal .Iv
Thus, the input common-mode range shoulde include also the positive supply rail.
Therefore, the input common-mode range is more than rail-to-rail operation.
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Bias Design! Figure 10.38 shows a self-biased current-
reference source.
11
lnBE TS
IV VI
=
ln IV V
=
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94
Figure 10.38
22
lnBE TS
V VI
=
21 2
1
ln SBE BE TS
IV V VI
=
But,
1 2 2BE BEV V IR =Thus,
2
2 1
ln STS
IVIR I
=
-
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Bias Design!
1 1
The circuit in Fig 10.38 provides a bias line with a voltage equal to .BIAS BEV V
This bias line can be used to bias other transistors and thus generate constant currents proportional to by appropr-I
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95
currents proportional to by appropr-iately scaling emitter areas and emitter-degeneration resistances.
I
Figure 10.39
These ideas are illustraged in Fig. 10.39.
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Design of the Input Stage to Obtain Rail-to-Rail VICM
! Consider the Fig. 10.40(a).1
(min)
is limited by keeping in active mode, so is 0.1V, and the input common-mode range does not include ground voltage as required.
ICM
ICM
V QV
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96
Figure 10.40
ground voltage as required.
The minimum allowed value of in Fig. 10.40(b) is
ICMV
(min) 0.6VCICM RV V=
(min)
If is selected to be 0.2 to 0.3V, will be -0.4V to -0.3V, wh-
ich is exactly what we need.
CR
ICM
V
V
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Design of the Input Stage to Obtain Rail-to-Rail VICM
! The differential gain is
1,2
2 C
om C
id
RC
T T
v g Rv
VI RV V
=
= =
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97
T TV V
For 0.3V, the gain realized is only 12 V V.CR
V =
This problem can be solved by cascoding.
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Design of the Input Stage to Obtain Rail-to-Rail VICM
! Consider the upper end of the input common-mode range.
(max) 5In Fig. 10.40(b), has to keep in active mode.
ICMV Q
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98
(max)So, is ICMV
(max) 0.1 0.7 0.8ICM CC CCV V V= =
That is, the upper end of the input common-mode range is at least 0.8Vbelow .CCV
0.3 0.8ICM CCV V
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Design of the Input Stage to Obtain Rail-to-Rail VICM
! To extend the upper end of , weadopt a solution similar to that used inthe CMOS case.
ICMV
The Fig. 10.41 is the npn version of the circuit of Fig. 10.40(b), and has a
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99
the circuit of Fig. 10.40(b), and has acommon-input range of
0.8 0.3ICM CCV V +
Thus, the high end is above the positivesupply rail by 0.3V.
0.8 0.8ICM CCV V
There is a range of in which both the and the circuits will be active and properly operating.
ICMVpnp npn
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Design of the Input Stage to Obtain Rail-to-Rail VICM
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100Figure 10.42
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Design of the Input Stage to Obtain Rail-to-Rail VICM
!
1 2
3 4
Figure 10.42 shows an input stage that achieves more than rail-to-rail input common-mode range by utilizing a differential pair ( and ) and an differential pair ( and ) connected in pa
pnp Q Q npnQ Q rallel.
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101
The dependence of the differential gain on the input common-mode is usuallyundesirable and can be reduced considerably by arranging that on of the two differentialpairs is turned off when the oth
ICMV
er one is active.
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Example 10.5
3 4 5
7 1
It is required to find the input resistance and the voltage gain of the input stage shownin Fig. 10.42. Let 0.8V so that the pair is off. Assume that supplies10 A, that each of to
ICMV Q Q QQ Q
0 is biased at 10A, and that all four cascode transistors are operating in the active mode. The iuput resistance of the second stage of the op amp(not shown) is 2M. The emitter-degeneration resisLR = 7 8tances are 20K,R R
= =
= = = = =
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102
9 10and 30K. Recall that the device parameters are 40, 10, 30V,20V.
N P An
Ap
R R V
V
= = = = ==
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Solution! 1 12 2id P mR r g = =
61
1 35 10 0.2 mA V25 10
Cm
T
IgV
= = =
2 10 100k0.2id
R = =
7ciG =
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103
71 2
cm
id
iGv
=
11
20V 4M5A
Apo
C
Vr
I= = =
7 20kR =
77
30V 3M10A
Ano
C
Vr
I= = =
77 7
1 25mV 2.5k10A
Te
m C
Vr
g I= = =
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Solution! 77 1
7 7
1 1
2
20 0.892 20 2.5 2
ide m
e
id idm m
v Ri gR r
v vg g
+
= = +
7 10.89 2id
o e m
vi i g =
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104
2
1 10.89 0.89 0.2 0.18mA V2o
m m
id
iG gv
= = =
( )9 7 2o o LR R R R= ! !( )( )9 9 9 9 9 91o o o m oR r R r g r= + +!
99
20V 2M10A
Apo
C
Vr
I= = =
69
9 310 10 0.4mA V25 10
Cm
T
IgV
= = =
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Solution! 9
9
10 25k0.4 mA V
P
m
rg
= = =
( ) ( )3 39 2 30 25 10 1 0.4 2 1012.9M
oR
= + +
=
!
( )( )7 7 7 7 7 71o o m oR r R r g r= + +!
1 1
3
22
0.18 0.89 10 160 V V
odd m
id
vA G Rv
= =
= =
12.9 23 1 0.89MR = =! !
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105
67
7 310 10 0.4 mA V25 10
Cm
T
IgV
= = =
77
40 100k0.4 mA V
N
m
rg
= = =
( ) ( )3 37 3 20 100 10 1 0.4 3 1023M
oR
= + +
=
!
2M 1M2 2
LR= =
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Common-Mode Feedback to Control the dc Voltage at the Output of the Input Stage
! 7 10For the cascode circuit in Fig. 10.42, the cascode transistors through mustoperate in the active mode at all time.
Q Q
9 10
7 8.
However, the currents supplied by and will not be exactly equal to the currents supplied by and
Q QQ Q
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106
These changes in turn can cause one set of the current sources to saturate.
1 2
7 8.
Thus, we need a circuit that detects the change in the dc or of and , andadjusts the bias voltage on the bases of and , to restore current equality.
CM O O
B
V v vQ Q V
Therefore, we use a feedback loop to provide common-mode feedback (CMF).
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Common-Mode Feedback to Control the dc Voltage at the Output of the Input Stage
Figure 10.44 shows the cascode circuit with the CMF circuit shown as a black box.
The CMF circuit has the transfer char-acteristic:
0.4V V= +
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107
Figure 10.44
0.4B CMV V= +
7
8
By keeping higher than byonly 0.4V, the CMF ensures that and remain active.
B CMV VQ
Q
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Common-Mode Feedback to Control the dc Voltage at the Output of the Input Stage
! Figure 10.45 shows the second stage of an op-amp circuit.
1 2O CM dv V v= +
2 2O CM dv V v=
0.4B CMV V= +
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108
Figure 10.45
11,12 13,14E CM EB BEV V V V= +
Thus, .E CMV V
1
The voltage is simply equal to plus the voltage drop of diode .
B EV VD
So, 0.4B E D CMV V V V= + = +
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Example 10.6
3 4
1 2
Consider the operation of the circuit in Fig. 10.44. Assume that 0.8V and thusthe input pair (Fig. 10.42) is off. Hence 0. Also assume that only dc vol-tages are present and thus
ICMVnpn I I
I I= =
= =
7 10
3 7 8 9 10
5A. Each of to is biased at 10A, V 3V,1, 20k, 30k. Neglect base currents and neglect
the loading edffect of the CMF circuit on the ouput nodes of the cascode circui
CC
BIAS CC
Q QV V R R R R
=
= = = = =
t. TheCMF circuit provides 0.4.V V= +
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109
CMF circuit provides 0.4.B CMV V= +
7 10
(a) Determine the nominal values of and . Does the value of ensure operation in the active mode for through ?
B CM CMV V VQ Q
1 2
7 8 9 10
(b) If the CMF circuit were not present, what would be the change in and as a result of a current mismatch =0.3A between and ? Use the output resistance values found i
O Ov v
I Q Q Q Q n Example 10.5.
(c) Now, if the CMF circuit is connected, what change will it cause in to eliminate the current mismatch ? What is the corresponding change in from its nominal value?
B
CM
VI V
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Solution(a) 37 7 1 7( ) 0.7 (10 5) 10 20 1VB BE EV V I I R = + + + + =
0.4 1 0.4 0.6VCM BV V= = =
7,8 0.6CM BV V> 7 8for to be activeQ QThat is,
0.4VCMV >
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110
0.4VCMV >
3 0.6CM BIASV V< +
1 0.6CM CCV V< +2.6VCMV
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! In the band-pass (BP) case, one transmission zeros is at ,and the other is , the magnitude response peaks at also called center frequency of BP filter.
! The second-order BP filter is measured by its 3-dB bandwidth.bandwidth is the difference between the two frequencies