advanced silicon devices - massachusetts institute of technology

6.152J / 3.155J Spring Term 2005 Lecture 23 --- Advanced Si Devices

Advanced Si Devices 1

6.152J / 3.155J Spring Term 2005 Lecture 23 --- Advanced Silicon Devices 1

Lecture 23:Advanced Si Devices

Reading Assignment: Plummer Chapters 1 and 2

Outline1. Technology Modules/Components

– Tool Kit

2. CMOS Technology Process Integration3. 90 nm CMOS Technology (Intel)4. 65 nm CMOS Technology (Intel)

Some Figures and Slides are from Intel


Fabrication “Toolkit”• Insulating Layers

– Oxidation, Nitridation– Deposition (LPCVD, PECVD, APCVD)

• Selective Doping of Silicon– Diffusion (in-situ doping)– Implantation– Epitaxy (in-situ doping)

• Material Deposition (Silicon, Metals, Insulators)– LPCVD (Epitaxy)– PECVD– Sputter Deposition

• Patterning of Layers– Lithography (UV, deep UV, e-beam & x-ray)

• Etching of (Deposited) Material– Dry Etches—Plasma, RIE, Sputter Etch, DRIE– Wet Etches—Etch in Liquids, CMP etc




Silicon VLSI Technologies

• Si CMOS Logic– Microprocessors, Microcontrollers, Digital Signal Processing, etc– Gate Arrays, Field Programmable Gate Arrays, etc

• Dynamic Random Access Memories (DRAMs)• Static Random Access Memories(SRAMS)

– Cache Memories• Non Volatile Memories (NVRAMs)

– EEPROMs• Mixed Signal CMOS

– Analog & Digital functions– A-to-D, D-to-A


Si CMOS Logic Key Components

• Devices– NMOS, PMOS, Resistors, Capacitors, Inductors

• Contacts– Ohmic & Schottky contacts to silicon

• Isolation– Isolate devices from each other

• Interconnects– Wiring for devices to “communicate” with each other and the outside world

RC

VDD

NMOS

PMOS

Vin Vout

PMOS

NMOS




CMOS Devices

As

P

OxideSource Drain

Poly-SiGate

p-type Si

Body

B

B

OxideSourceDrain

Poly-SiGate

n-type Si

Body

N-MOS P-MOS

• CMOS (n-MOS & p-MOS) devices are required by logic circuits to reduce static power dissipation

• n-MOS & p-MOS require different channel background doping and source/drain region doping

The big challenge: How to integrate both PMOS & NMOS on the same substrate (including resistors, capacitors etc.)?


Oxide

CMP oxide & Nitride/oxide strip

Oxide

Oxide

P+

P+

Silicon substrate

Silicon substrate

Boron Implant

Silicon substrate

Resist

Resist

P+

Silcon Dioxide Silicon Nitride

Silicon substrate

Shallow Trench Isolation

• Growth of pad silicon dioxide and deposition of silicon nitride as in LOCOS• Implant trench to increase field threshold and growth of liner oxide for

passivation and smoothing• Trench fill with deposited oxide (high density plasma oxide)• CMP for planarization• Oxide densification• Nitride strip in hot H3PO4




n- and p- Well Formation

p- or n-type substrate

p-well n-well

p-well & n-well implants and drive-in


LOCOS Isolation


p-well n-well

Field Oxide

p-channel stop

n-channel stop

Channel stop implants




VTH Adjust Implants


p-well n-well

Field Oxide

p-channel stop

n-channel stop

As Implant B Implant


Gate OxidationPoly-Si Gate Definition


p-well n-well

Field Oxide

p-channel stop

n-channel stop

Poly GateGate

Oxide




Lightly Doped Drain Implants


p-well n-well

Field Oxide

p-channel stop

n-channel stop

Poly Gate

n- p-

n- Implant p- Implant


Side-Wall Spacer Formation &Source/Drain Implants


p-well n-well

Field Oxide

p-channel stop

n-channel stop

Poly Gate

n- p-

n+ Implant p+ Implant

n+ p+

Sidewall Spacer Formation

• Blanket deposition of oxide or nitride• Timed etch of oxide/nitride using very directional etch (RIE)

– Just enough time to remove oxide / nitride from the source, drain and gate regions




Salicide Formation


p-well n-well

Field Oxide

p-channel stop

n-channel stop

Polycide Gate

n- p-n+ p+

Silicide

Salicide Formation

Self-Aligned Silicide

Salicide reduces gate resistance, source / drain contact resistance


Contact Barrier Layer &Local Interconnect


p-well n-well

Field Oxide

p-channel stop

n-channel stopn- p-n+ p+

Al or W Local Interconnect

Contact Barrier Layer

Deposited Oxide Layer

• Typical contact metallization– TiSi2 / TiN /

• Oxide layer deposited by– LPCVD (conformal)– High density plasma PECVD (planarization)




Device Scaling( ) ( )

( )

2 2Dmax GSmax T DD T

0Dmax L

L 0 L DDD

Dmax Dmax

2DD T

Dmax

D L DD L DD

W WI K V V K V VL LdVI Cdt

C V C VI I

WK V VI1 LfC V C V

= − = −

=

∆τ = ≈

−= ≈ ≈τ

Frequency increases as IDmax increasesIDmax increases as L decreases

PD is average power consumed

PDτD = Power-Delay Productis the average energy dissipated per switching event

PD = ID maxVDD

2

PDτD =12

CLVDD2

Power =12

CLVDD2 f


Drain Engineering• High electric field exists at the reverse biased drain pn junction• Leads to impact ionization, reliability problems and possibly breakdown• Maximum E-field reduced by lightly doped drain structure

εmax =2qNAND Vbi − VDD( )

εs NA +ND( )

Other Issues• Gate Leakage Current• Gate Oxide reliability• Latch-up• Short Channel Effects (Device Electrostatics)




CMOS Drivers & Delay

RC

VDD

NMOS

PMOS

Vin Vout

PMOS

NMOS

RCVin Vout

+

-

Vout

Vin

tp >> RC

tp << RC

timetp

tp time

( )p

p

t t )(

tt0 1)(

≥=

≤≤⎟⎠⎞⎜

⎝⎛ −=

−−

−

RCtt

DDout

RCt

DDout

p

eVtV

eVtV

VDD


Interconnect Metal RC Delay

W

tmtox

L

Metal Ground PlaneSilicon Dioxide

Metal Line

RI =ρ

tm

LW

; CI =εi

toxLW

RICI =ρ

tm

LW

εitox

LW

= ρtm

εitox

L2• need low ρ to minimize RC delay• need low εi to minimize RC delay• need to increase tm and tox to minimize RC delay

ρ is the resistivity of metalεi is the dielectric constant




Logic Technology Evolution


90 nm Generation Transistor




Gate Length Scaling


Gate Oxide Scaling




90 nm Gate Oxide

1.2 nm SiO2


Strained Silicon Transistors




Intel’s Strained Si Technology


Intel’s Strained Si Technology




90 nm Generation Interconnects


Low-k Carbon Doped Oxide

• Low-k Carbon Doped Oxide for interconnect dielectric

• Low-k CDO provides ≈20% reduction in capacitance.

• Reduced Interconnect capaciatnce provides improved performance and lower chip power




90 nm Processors in Production


Moore’s Law is Alive and Well!




Itanium Processor Family


Logic Technology Evolution




Scaling of Key Technology Indicator


65 nm Transitorr




Reduced Gate Capacitance• Gate oxide thickness is held

constant at 1.2 nm to avoid increased gate leakage.

• Gate capacitance CGATEreduced ≈20% due to shorter gate length (35 nm).

• Lower gate capacitance reduces dynamic power consumption of chip.

• Combination of higher drive current and lower gate capacitance provides ≈1.4x increase in switching frequency.


Lithography Challenge




Lithography Challenge


Optical Proximity Correction

• Sub-resolution Optical Proximity Correction features added during mask making to enable improved pattern definition.

• OPC requires sophisticated algorithms for adding sub-resolution features.




Alternating Phase Shift Mask

• Phase shift masks enable patterning of lines that are less than 40 nm using 193 nm lithography.

• APSM requires both new mask making technology and new circuit layout design rules.


65 nm Interconnects




65 nm Interconnects

• Eight Metal layers added to improve density and performance.

• Low-k carbon doped oxide dielectric reduces capacitance.

• Interconnect capacitance reduced with 0.7x line length scaling.

• Lower capcitanceimproves interconnect performance and reduces chip power.


0.57 µm2 6-T SRAM Cell

• Ultra-small SRAM cell used in 65 nm process– six transistors in an area of 0.57 µm2.

• Cell is optimized for both small area and noise margin.




10 Million Transistors in 1 mm2

Ten Million Transistors Fit in 1 mm2, roughly the size of the tip of a ball point pen.


SUMMARY• Advanced Silicon CMOS configured

using a fabrication “Tool-Kit”– Process / Technology modules

• New generations of Si devices require the introduction of new materials and technologies. Examples are

– Strained Si– SiGe or Ge– Silicon on Insulator (SOI)– High k dielectrics (gate)– Low k dielectrics (interconnect)– Carbon doped oxide– Cu– etc

advanced silicon devices - massachusetts institute of technology

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