advanced silicon devices - infineon technologies

Advanced Silicon Devices – Applications and Technology Trends

Gerald Deboy Winfried Kaindl, Uwe Kirchner, Matteo Kutschak, Eric Persson, Michael Treu

APEC 2015

Content

Silicon devices versus GaN devices: An unbiased view on key performance indicators

Applications: Comparison of devices in hard-switching and resonant circuits

Summary

March 2015 Copyright © Infineon Technologies AG 2015. All rights reserved.

Comparing competing device concepts

n+-Implantation

n-Epitaxy

p+-Implantation

p-Implantation

Oxide

Metal/Poly-Si

Buffer layer

Si Substrate

AlN/AlGaN Barrier

S G

D

Si Superjunction

p n

p+ n+

D

S G

SiC vertical drift zone

S G

D

D

2DEG

GaN lateral HEMT

RON×A scales with cell pitch Inherently fast switching dv/dt scales inversely with

cell pitch Reverse recovery charge and

snappyness of body diode as major drawbacks

Pitch influences RON×A by improved utillization of the semiconductor volume

Normally-on; turns into normally-off by Cascode or direct-driven concept

Good body diode; Qrr close to SiC Schottky diodes

Good starting point for low RON×A and QOSS due to high electron mobility

Device capacitances are strongly influenced by the metal re-routing

Excellent reverse behavior


How far can the Superjunction concept be exploited in terms of RDSon*A?

CoolMOSTM C3 CoolMOSTM CP

Other 1 Other 2

Other 3 1.55 Ωmm2

CoolMOSTM C7 1.0 Ωmm2

0,01

0,10

1,00

2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020

RD

SO

N,

max ×

A [

Ωm

m2]

Si Superjunction MOSFET

SiC FET

GaN HEMT

Still a long way until the limit is reached with Si Superjunction. Si limit potentially lower than 0.5 Ωmm2

Si Superjunction limit D. Disney, G. Dolny ISPSD 2008

nepi

D

p-

n+s

ub

G

p+ n

p

S

SiC and GaN devices


The output capacitance of SJ devices gets more non-linear with every generation! 190 mOhm, 600V / 650V devices

lower Eoss

higher dv/dt

lower switching losses

Stronger non-linearity

longer delay times


The Qoss characteristic will become more and more flat! 190 mOhm, 600V / 650V devices

GaN significantly better in absolute FoM and linearity

longer delay times in resonant applications

trend reversed for next gen CoolMOS™

more rectangular voltage waveforms


Eoss scales with cell pitch and can be brought below the level of 1st gen GaN devices 190 mOhm, 600V / 650V devices

next gen CoolMOS™

FoM Ron*Eoss scales with pitch of SJ device


40% Eoss reduction versus earlier SJ generation fully translates into lower turn-off losses! 190 mOhm / 600V

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32Rg [Ohm]

0

0,001

0,002

0,003

0,004

0,005

0,006

0,007

0,008

0,009

0,01

0,011

0,012

0,013

Eof

f2 [

mJ]

LEGEND

GRP

G1

G2

G3

BoxPlot Eoff2 [mJ] (Subset:Iset2 [A] ('5,3')) grouped by GRPlo -- hi -- qty 36/36 mean 0.008648 sigma 0.002466 cp -- cpk --

Turn

-off losses @

5.3

A [

mJ]

40% reduction of switching losses (CoolMOS™ CP vs next gen CoolMOS™)

Fully relieved switching up to around 10 Ohm gate resistor

CoolMOS™ CP 600V

next gen CoolMOS™


4 6 8 10 12 14 16 18 20 22 24 26 28 30 32Rg [Ohm]

0

0,005

0,01

0,015

0,02

0,025

0,03

0,035

Eon [

mJ]

LEGEND

GRP

G1

G2

G3

BoxPlot Eon [mJ] (Subset:Iset2 [A] ('5,3')) grouped by GRPlo -- hi -- qty 36/36 mean 0.0172 sigma 0.007441 cp -- cpk --

Turn-on losses are mainly determined by package and no longer benefit from silicon improvements! 190 mOhm / 600V

Turn

-on losses @

5.3

A [

mJ]

Turn-on losses mainly limited by parasitic package inductances

Significant improvement potential for 4pin & SMD packages

CoolMOS™ CP next gen CoolMOS™


Package and switching cell optimization are mandatory to fully benefit from fast switching devices!

TO-247 4pin Kelvin contact to source, decoupling of gate drive,

Eon improvement

Package level

- Source inductance most critical

- Solved by Kelvin contact

- however inductance still in the commutation loop

Switching cell level

- True SMD solution allows compact, low-inductive switching cell

- Symmetric coupling capacitances to heatsink are important from EMI point of view

- Top side cooling optional in DSO-20

Heatsink

ThinPAK, TOLL, DSO-20


SMD packages will be important for SJ devices and mandatory for GaN!

85-265VAC400V

s1

s2

d1

d2

Cheatsink TO = ~20 pF

ECpar = 1.6 µJ

Edev = 3 µJ

Losses

Voltage overshoot

85-265VAC400V

s1

s2

d1

d2

Lpar TO = ~20 nH

Elpar_10A = 1 µJ

Vovershoot = 100V @ 5kA/µs

Lpar = 3- 6 nH

C T_HS T_LS

Top Layer

Mid Layer

Current flow:

heatsink

PCB top view:

T_HS

T_LS

Power loop caps

Commutation loop 3.2 nH


In case of layout constraints…

With C6 a integrated Gate Resistor was introduced to damp Oscillations

Optimization tradeoff efficiency and Layout with each new technology

Layout Sensitivity

0

5

10

CP C7 CM1 P6 E6 CFD II CFD I C3 C6

Rg

int

Layout sensitiviity - +

high efficiency

Package

dV/ dt dI/ dt Oscillation circuit triggered by

Cparasitic

Layout

Lparasitic

Layout

Possible Ringing Circuit

Damping Element

Damping behavior of Rg Internal

-30

-20

-10

0

10

20

30

0 20 40 60 80 100Vgs

[V

]

Ids [A]

Exam

ple

19

0mΩ

Cp

arasit

ic =

5p

F

Less layout dependencies can be achieved by choosing a technology with higher values of the damping resistor.

C3

E6

P6

C6

CP

C7 η

dV/ dt

Low switching losses are inevitably coupled to high dv/dt and di/dt values both at turn-on and turn-off.

0

50

100

150

200

250

0 5 10 15 20

Turn

Off

dV

/dt

[V

/ns]

Current ID [A]

P6

C7

CP

E6

C6

C3

η

Example 190 mΩ

How to use fast switching SJ devices

Avoid a coupling capacitance between G,D

Place the gate resistor close to the gate

Avoid Stray inductance in the Power Loop

Use the mutual inductance effect (opposite current flow, forced current) in the power loop

Add ferrite beads if necessary

current

Best performance Cost/performance segment Ease of Use optimized

nG


Content



Summary


SJ devices will prevail in classic and dual boost GaN offers significant value in Totem Pole PFC

Classic PFC Dual Boost PFC Totem Pole PFC

Less System Cost

Less Efficiency

High Power Density

High System Cost

High Efficiency

Less Power Density

Less System Cost

High Efficiency

High Power Density

GaN enables hard commutation on internal “diode”

Superjunction (S1)

SiC (D1)

Superjunction (S1, S2)

SiC (D1, D2)

Superjunction (S1, S2)

GaN, SJ, IGBT (S3, S4)


Best competing silicon alternative in terms of power density and efficiency: TCM PFC 3 kW, 4.5 kW/l (74W/in³)

Source: U. Badstübner, J. Miniböck, J. Kolar, „ Experimental Verification of the Efficiency/Power-Density (n-p) Pareto Front of Single-Phase Double-Boost and TCM PFC Rectifier Systems”, Proc. APEC 2013.


Advantage of GaN: very high frequency operation with Ron*Qoss and Qg as key parameters

85%

87%

89%

91%

93%

95%

97%

99%

0 100 200 300 400 500

Eff

icie

ncy

Po [W]

2.5 MHz

High efficiency possible by frequency control

Input Caps Output Caps

RF Inductor

Gate Driver

GaN Switches


Comparison of hard-switching PFC stages: Reference: CoolMOS™ C7 / SiC G5

Reference: CCM PFC 100 kHz;

CoolMOS™ C7 65 mOhm, 4pin;

SiC G5 SBD 16A

diode rectification bridge


Advantage of GaN: CCM modulation in Totem Pole PFC, close to 99% efficiency with simple half bridge solution


CoolMOS C7 65 mOhm, 4 pin;

SiC G5 SBD 16A

half bridge Totem Pole, 65 kHz;

GaN 70 mOhm

return path: bridge rectifier (one diode only)

0.5% better efficiency


Advantage of GaN: > 99% efficiency with combination of SJ and GaN in Totem Pole full bridge



SiC G5 SBD 16A

full bridge Totem Pole, 65 kHz;

GaN 70 mOhm / IGBT F5 40A + 16A SiC SBD

return path: CoolMOS™ C7 35 mOhm

0.2% better than half bridge

0.4% better than IGBT solution


Advantage of GaN: > 99% efficiency across wide low range with low frequency Totem Pole PFC



SiC G5 SBD 16A

full bridge Totem Pole, 45 kHz;

GaN 70 mOhm

return path: CoolMOS™ C7 35 mOhm

>99% efficiency from 20..70% load

0.1% better than 65 kHz solution


Resonant LLC DC/DC Converter (750 W, 400 kHz)

Expected performance of GaN versus latest SJ devices

Cr Lr n:1:1VIN

Q1

Q2

S2

VO

S1

RL

Lm

A

0

D1

D2

350V…410 V to 12 V

Power density > 200W/in³

Pure convection cooled

GaN expected to be 0.7% better in partial load range

GaN, 70 mOhm

GaN, 190 mOhm

P6, 190 mOhm


Latest SJ devices will benefit from parallel cap to counterbalance non-linearity

Same dv/dt at 1/5th of magnetizing current

Potential path to further efficiency increase for narrow range Vin applications


Last but not least! Recent improvements in key Figure-of-Merits for low voltage MOSFETs …


0

0,5

1

1,5

2

2,5

3

3,5

4

4,5

5

RDSon / SSO8[mOhm]

RDSon*Qoss[mOhm*nC *100]

Gen 3

Gen 4

100 V MOSFET: smaller area-specific on-resistance and charges through further optimization of trench structure

n-

sub

G S

p n

n+sub

n

D

… Allow new solutions by using cascaded multi-cell architectures!


Cascaded converter topology, Totem Pole + phase shift ZVS Efficiency target > 98% 100 V OptiMOS™ BSC034N10NS5

3 kW AC/DC converter, 48V out

FinSix 65 W Adapter, 19V out

Switching frequency > 10 MHz 200 V OptiMOS™ BSZ22DN20NS3

Content



Summary


Summary

Superjunction devices will continue to deliver better Best-in-Class RDSon devices with further improved FoM Ron*Eoss

Recent improvements in low voltage devices FoMs allow to rethink classic architectures and consider the use of LV devices in HV applications

The use of good layout practice, transition to 4pin packages and finally to SMD packages will become more and more important and is mandatory for GaN

GaN offers specifically advantages both in terms of power density and efficiency at hard switching topologies with continuous use of the reverse characteristic and at very high switching frequencies in resonant converters


advanced silicon devices - infineon technologies

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