adsp-bf533 ez-kit lite evaluation system manual · natural merging of risc, media functions, and...

ADSP-BF533 EZ-KIT Lite®

Evaluation System Manual

Revision 2.0, January 2005

Part Number82-000730-01

Analog Devices, Inc.One Technology WayNorwood, Mass. 02062-9106 a

Copyright Information© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc.

Printed in the USA.

Limited WarrantyThe EZ-KIT Lite evaluation system is warranted against defects in materi-als and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer.

DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli-cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark NoticeThe Analog Devices logo, VisualDSP++, VisualDSP++ logo, Blackfin, CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

Regulatory Compliance The ADSP-BF533 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark.

The ADSP-BF533 EZ-KIT Lite evaluation system had been appended to Analog Devices Development Tools Technical Construction File refer-enced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file.

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electro-static charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.

CONTENTS

PREFACE

Purpose of This Manual ................................................................. xiv

Intended Audience .......................................................................... xv

Manual Contents ............................................................................ xv

What’s New in This Manual ........................................................... xvi

Technical or Customer Support ...................................................... xvi

Supported Processors ..................................................................... xvii

Product Information ..................................................................... xvii

MyAnalog.com ........................................................................ xvii

Processor Product Information ................................................ xviii

Related Documents ................................................................ xviii

Online Technical Documentation .............................................. xx

Accessing Documentation From VisualDSP++ ....................... xx

Accessing Documentation From Windows ............................ xxi

Accessing Documentation From Web ................................... xxi

Printed Manuals ....................................................................... xxi

VisualDSP++ Documentation Set ........................................ xxii

Hardware Tools Manuals ..................................................... xxii

Processor Manuals ............................................................... xxii

ADSP-BF533 EZ-KIT Lite Evaluation System Manual v

CONTENTS

Data Sheets ........................................................................ xxii

Notation Conventions ................................................................. xxiii

USING EZ-KIT LITE

Package Contents ......................................................................... 1-2

Default Configuration .................................................................. 1-3

Installation Session Startup ........................................................... 1-4

Evaluation License Restrictions ..................................................... 1-5

Memory Map ............................................................................... 1-6

SDRAM Interface ......................................................................... 1-7

Flash Memory .............................................................................. 1-8

Flash Memory Map ................................................................. 1-9

Flash General-Purpose IO ..................................................... 1-10

Configuring Flash Memory ................................................... 1-12

LEDs and Push Buttons .............................................................. 1-13

Audio Interface ........................................................................... 1-13

Video Interface ........................................................................... 1-15

Example Programs ...................................................................... 1-16

Background Telemetry Channel .................................................. 1-16

VisualDSP++ Interface ................................................................ 1-16

Trace Window ...................................................................... 1-17

Enabling Trace Buffer ....................................................... 1-17

Reading Trace Buffer Data ................................................ 1-18

Boot Load ............................................................................. 1-18

Target Options ...................................................................... 1-18

vi ADSP-BF533 EZ-KIT Lite Evaluation System Manual

CONTENTS

Reset Options ................................................................... 1-19

On Emulator Exit ............................................................. 1-19

Other Options .................................................................. 1-19

Restricted Software Breakpoints ............................................. 1-20

EZ-KIT LITE HARDWARE REFERENCE

System Architecture ...................................................................... 2-2

External Bus Interface Unit ...................................................... 2-3

SPORT0 Audio Interface ......................................................... 2-3

SPI Interface ........................................................................... 2-4

Programmable Flags ................................................................. 2-4

PPI Interface ........................................................................... 2-5

Video Output Mode ........................................................... 2-7

Video Input Mode .............................................................. 2-7

UART Port .............................................................................. 2-8

Expansion Interface ................................................................. 2-8

JTAG Emulation Port .............................................................. 2-9

Jumper and Switch Settings ........................................................... 2-9

Boot Mode Select Jumpers (JP2–1) ........................................ 2-10

Test DIP Switches (SW2–1) ................................................... 2-10

Video Configuration Switch (SW3) ....................................... 2-10

Push Button Enable Switch (SW9) ......................................... 2-11

LEDs and Push Buttons .............................................................. 2-13

Programmable Flag Push Buttons (SW7–4) ............................ 2-13

Reset Push Button (SW8) ...................................................... 2-14

ADSP-BF533 EZ-KIT Lite Evaluation System Manual vii

CONTENTS

Power LED (LED1) .............................................................. 2-14

Reset LEDs (LED3–2) .......................................................... 2-14

User LEDs (LED9–4) ........................................................... 2-15

USB Monitor LED (LED11) ................................................. 2-15

Connectors ................................................................................. 2-16

Expansion Interface (J3–1) .................................................... 2-16

Audio (J5–4) ......................................................................... 2-17

Video (J8) ............................................................................. 2-17

Power (J9) ............................................................................ 2-17

FlashLINK (P1) .................................................................... 2-18

RS232 (P2) ........................................................................... 2-19

SPORT0 (P3) ....................................................................... 2-19

JTAG (P4) ............................................................................ 2-20

BILL OF MATERIALS

INDEX

viii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

CONTENTS

ADSP-BF533 EZ-KIT Lite Evaluation System Manual ix

CONTENTS

x ADSP-BF533 EZ-KIT Lite Evaluation System Manual

PREFACE

Thank you for purchasing the ADSP-BF533 EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for Blackfin® processors.
The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics towards delivering signal processing performance in a microprocessor-like environment.

The evaluation board is designed to be used in conjunction with the Visu-alDSP++® development environment to test the capabilities of the ADSP-BF533 Blackfin processors. The VisualDSP++ development envi-ronment gives you the ability to perform advanced application code development and debug, such as:

• Create, compile, assemble, and link application programs written in C++, C and ADSP-BF533 assembly

• Load, run, step, halt, and set breakpoints in application program

• Read and write data and program memory

• Read and write core and peripheral registers

• Plot memory

Access to the ADSP-BF533 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF533 processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xi

communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.com/dsp/tools/.

ADSP-BF533 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.

The ADSP-BF533 EZ-KIT Lite installation is part of the Visu-alDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires:

• VisualDSP++ allows a connection to the ADSP-BF533 EZ-KIT Lite via the USB Debug Agent interface only. Connections to sim-ulators and emulation products are no longer allowed.

• The linker restricts a users program to 20 KB of internal memory for code space with no restrictions for data space.

Refer to the VisualDSP++ Installation Quick Reference Card for details.

The board features:

• Analog Devices ADSP-BF533 processor

Performance to 756 MHz160-pin Mini-BGA package27 MHz CLKIN oscillator

• Synchronous Dynamic Random Access Memory (SDRAM)

MT48LC32M16 - 64 MB (32M x 16 bits)

• Flash Memory

2 MB (512K x 16 x 2chips)

xii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface

• Analog Audio Interface

AD1836 – Analog Devices 96 kHz audio codec 4 input RCA phono jacks (2 channels)6 output RCA phono jacks (3 channels)

• Analog Video Interface

ADV7183 video decoder w/ 3 input RCA phono jacksADV7171 video encoder w/ 3 output RCA phono jacks

• Universal Asynchronous Receiver/Transmitter (UART)

ADM3202 RS-232 line driver/receiverDB9 male connector

• LEDs

10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 6 general purpose (amber), and 1 USB monitor (amber)

• Push Buttons

5 push buttons with debounce logic: 1 reset, 4 programmable flags

• Expansion Interface

PPI, SPI, EBIU, Timers2-0, UART, programmable flags, SPORT0, SPORT1

• Other Features

JTAG ICE 14-pin header

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xiii

Purpose of This Manual

The EZ-KIT Lite board has two Flash memories with a total of 2 MB of memory. The Flash memories can be used to store user-specific boot code, allowing the board to run as a stand-alone unit. For more information, see “Flash Memory” on page 1-8. The board also has 64 MB of SDRAM, which can be used by the user at runtime.

SPORT0 interfaces with the AD1836 audio codec to aid development of audio signal processing applications. SPORT0 also attaches to an off-board connector for communication with other serial devices. For information about SPORT0, see “SPORT0 Audio Interface” on page 2-3.

The Parallel Peripheral Interface (PPI) of the processor connects to both a video encoder and video decoder, facilitating development of video signal processing applications.

The UART of the processor connects to an RS232 line driver and a DB9 male connector, providing an interface to a PC or other serial device.

Additionally, the EZ-KIT Lite board provides access to most of the pro-cessor’s peripheral ports. Access is provided in the form of a three-connector expansion interface. For information about the expansion interface, see “Expansion Interface” on page 2-8.

Purpose of This Manual The ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes the operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF533 EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs.

The product software installation is detailed in the VisualDSP++ Installa-tion Quick Reference Card.

xiv ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface

Intended AudienceThe primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts (such as the ADSP-BF533 Processor Hardware Reference and the Blackfin Processor Instruction Set Reference) that describe your target architecture.

Programmers who are unfamiliar with VisualDSP++ should refer to the VisualDSP++ online Help and user’s or getting started guides. For the locations of these documents, see “Related Documents”.

Manual ContentsThe manual consists of:

• Chapter 1, “Using EZ-KIT Lite” on page 1-1Describes the EZ-KIT Lite functionality from a programmer’s per-spective and provides an easy-to-access memory map.

• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1Provides information on the EZ-KIT Lite hardware components.

• Appendix A, “Bill Of Materials” on page A-1Provides a list of components used to manufacture the EZ-KIT Lite board.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xv

What’s New in This Manual

• Appendix B, “Schematics” on page B-1Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design.

This appendix is not part of the online Help. The online Help viewers should go to the PDF version of the ADSP-BF533 EZ-KIT Lite Evaluation System Manual located in the Docs\EZ-KIT Lite Manuals folder on the installation CD to see the schematics. Alter-natively, the schematics can be found on the Analog Devices Web site, www.analog.com/processors.

What’s New in This Manual This revision of the ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides an updated listing of related documents and updated licensing information.

Technical or Customer SupportYou can reach DSP Tools Support in the following ways.

• Visit the Embedded Processing and DSP products Web site athttp://www.analog.com/processors/technicalSupport

• E-mail tools questions [email protected]

• E-mail processor questions [email protected]

• Phone questions to 1-800-ANALOGD

xvi ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface

• Contact your Analog Devices, Inc. local sales office or authorized distributor

• Send questions by mail to:

Analog Devices, Inc.

One Technology Way

P.O. Box 9106

Norwood, MA 02062-9106

USA

Supported ProcessorsThis evaluation system supports Analog Devices ADSP-BF533 Blackfin processors.

Product InformationYou can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at www.analog.com. Our Web site provides infor-mation about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

MyAnalog.comMyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xvii

Product Information

Registration:

Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as means for you to select the information you want to receive.

If you are already a registered user, just log on. Your user name is your e-mail address.

Processor Product InformationFor information on embedded processors and DSPs, visit our Web site at www.analog.com/processors, which provides access to technical publica-tions, data sheets, application notes, product overviews, and product announcements.

You may also obtain additional information about Analog Devices and its products in any of the following ways.

• E-mail questions or requests for information to [email protected]

• Fax questions or requests for information to1-781-461-3010 (North America)+49 (89) 76 903-557 (Europe)

• Access the FTP Web site atftp ftp.analog.com or ftp 137.71.23.21 ftp://ftp.analog.com

Related DocumentsFor information on product related development software, see the follow-ing publications.

xviii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface

If you plan to use the EZ-KIT Lite board in conjunction with a JTAG emulator, also refer to the documentation that accompanies the emulator.

All documentation is available online. Most documentation is available in printed form.

Visit the Technical Library Web site to access all processor and tools man-uals and data sheets:

http://www.analog.com/processors/resources/technicalLibrary

Table 1. Related Processor Publications

Title Description

ADSP-BF533 Embedded Processor Datasheet General functional description, pinout, and timing.

ADSP-BF533 Blackfin Processor Hardware Ref-erence

Description of internal processor architecture and all register functions.

Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions.

Table 2. Related VisualDSP++ Publications

Title Description

VisualDSP++ User’s Guide Description of VisualDSP++ features and usage.

VisualDSP++ Assembler and Preprocessor Manuals

Description of the assembler function and com-mands.

VisualDSP++ C/C++ Complier and Library Manual for Blackfin Processors

Description of the complier function and com-mands for Blackfin processors.

VisualDSP++ Linker and Utilities Manual Description of the linker function and com-mands.

VisualDSP++ Loader Manual Description of the loader/splitter function and commands.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xix

Product Information

Online Technical Documentation Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary .PDF files of most manuals are provided in the Docs folder on the VisualDSP++ installation CD.

Each documentation file type is described as follows.

If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD at any time by run-ning the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site.

Accessing Documentation From VisualDSP++

To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP++ documentation via the Start menu.

File Description

.CHM Help system files and manuals in Help format

.HTM or

.HTMLDinkum Abridged C++ library and FlexLM network license manager software doc-umentation. Viewing and printing the .HTML files requires a browser, such as Internet Explorer 4.0 (or higher).

.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF). Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

xx ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface

To view ADSP-BF533 EZ-KIT Lite Help, which is part of the Visu-alDSP++ Help system, use the Contents or Search tab of the Help window.

Accessing Documentation From Windows

In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documenta-tion from Windows.

Help system files (.CHM) are located in the Help folder, and .PDF files are located in the Docs folder of your VisualDSP++ installation CD-ROM. The Docs folder also contains the Dinkum Abridged C++ library and the FlexLM network license manager software documentation.

Your software installation kit includes online Help as part of the Win-dows® interface. These help files provide information about VisualDSP++ and the ADSP-BF533 EZ-KIT Lite evaluation system.

Accessing Documentation From Web

Download manuals at the following Web site: http://www.analog.com/processors/resources/technicalLibrary/man-

uals.

Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files.

Printed ManualsFor general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xxi

Product Information

VisualDSP++ Documentation Set

To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit.

If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir/continent.asp.

Hardware Tools Manuals

To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual.

Processor Manuals

Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual.

Data Sheets

All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site.

To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.

xxii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface

Notation ConventionsText conventions used in this manual are identified and described as follows.

Example Description

Close command (File menu)

Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).

{this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required.

[this | that] Optional items in syntax descriptions appear within brackets and sepa-rated by vertical bars; read the example as an optional this or that.

[this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this.

.SECTION Commands, directives, keywords, and feature names are in text with letter gothic font.

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this

symbol.

Caution: Incorrect device operation may result if ...Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xxiii

Notation Conventions

Additional conventions, which apply only to specific chapters, may appear throughout this document.

xxiv ADSP-BF533 EZ-KIT Lite Evaluation System Manual

1 USING EZ-KIT LITE

This chapter provides specific information to assist you with development
of programs for the ADSP-BF533 EZ-KIT Lite evaluation system.
The information appears in the following sections.

• “Package Contents” on page 1-2Lists the items contained in your ADSP-BF533 EZ-KIT Lite package.

• “Default Configuration” on page 1-3Shows the default configuration of the ADSP-BF533 EZ-KIT Lite.

• “Installation Session Startup” on page 1-4Instructs how to start a new or open an existing ADSP-BF533 EZ-KIT Lite session using VisualDSP++.

• “Evaluation License Restrictions” on page 1-5Describes the restrictions of the VisualDSP++ demo license shipped with the EZ-KIT Lite.

• “Memory Map” on page 1-6Defines the ADSP-BF533 EZ-KIT Lite board’s memory map.

• “SDRAM Interface” on page 1-7·Defines the register values to configure the on-board SDRAM.

• “Flash Memory” on page 1-8Describes the on-board flash memory.

• “LEDs and Push Buttons” on page 1-13Describes the board’s general-purpose IO pins and buttons.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-1

Package Contents

• “Audio Interface” on page 1-13Describes the board’s audio interface.

• “Video Interface” on page 1-15Describes the board’s video interface.

• “Example Programs” on page 1-16Provides information about the example programs included in the ADSP-BF533 EZ-KIT Lite evaluation system.

• “Background Telemetry Channel” on page 1-16Highlights the advantages of the Background Telemetry Channel feature of VisualDSP++.

• “VisualDSP++ Interface” on page 1-16Describes the trace, boot loading, context switching, and target options facilities of the EZ-KIT Lite system.

For more detailed information about programming the ADSP-BF533 Blackfin processor, see the documents referred to as “Related Documents”.

Package ContentsYour ADSP-BF533 EZ-KIT Lite evaluation system package contains the following items.

• ADSP-BF533 EZ-KIT Lite board

• VisualDSP++ Installation Quick Reference Card

• CD containing:

VisualDSP++ softwareADSP-BF533 EZ-KIT Lite debug softwareUSB driver files

1-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Using EZ-KIT Lite

Example programsADSP-BF533 EZ-KIT Lite Evaluation System Manual (this document)

• Universal 7.5V DC power supply

• USB 2.0 type cable

• Registration card (please fill out and return)

If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc.

Default Configuration

The ADSP-BF533 EZ-KIT Lite board is designed to run outside your per-sonal computer as a stand-alone unit. You do not have to open your computer case.

When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which may dam-age some components. Figure 1-1 shows the default jumper settings, DIP switch, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before using the board.

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Per-manent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.


Installation Session Startup

Installation Session StartupFor correct operation, install the software and hardware in the order presented in the VisualDSP++ Installation Quick Reference Card.

1. Verify that the yellow USB monitor LED (LED11, located near the USB connector) is lit. This signifies that the board is communicat-ing properly with the host PC and is ready to run VisualDSP++.

2. From the Start menu, navigate to the VisualDSP++ environment via the Programs menu.If you are running VisualDSP++ for the first time, the New Session

Figure 1-1. EZ-KIT Lite Hardware Setup


Using EZ-KIT Lite

dialog box appears on the screen (skip the rest of the procedure and go to step 3).If you have run VisualDSP++ previously, the last opened session appears on the screen.To switch to another session, via the Session List dialog box, hold down the Ctrl key while starting VisualDSP++ (go to step 5).

3. In Debug target, select EZ-KIT Lite (ADSP-BFxxx).In Platform, select ADSP-BFxxx EZ-KIT Lite.In Processor, choose the appropriate processor, ADSP-BF533. In Session name, type a new name or accept the default.

4. Click OK to return to the Session List.

5. Highlight the session and click Activate.

Evaluation License RestrictionsThe ADSP-BF533 EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unre-stricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires:

• VisualDSP++ allows a connection to the ADSP-BF533 EZ-KIT Lite via the USB Debug Agent interface only. Connections to sim-ulators and emulation products are no longer allowed.

• The linker restricts a users program to 20 KB of internal memory for code space with no restrictions for data space.

The EZ-KIT Lite hardware must be connected and powered up to use VisualDSP++ with a valid evaluation or permanent license.

Refer to the VisualDSP++ Installation Quick Reference Card for details.


Memory Map

Memory MapThe ADSP-BF533 processor has internal SRAM that can be used for instruction or data storage. The configuration of internal SRAM is detailed in the ADSP-BF533 Processor Hardware Reference.

The ADSP-BF533 EZ-KIT Lite board includes two types of external memory, SDRAM and flash memory.

The size of the SDRAM is 64 Mbytes (32M x 16-bits). The processor’s memory select pin ~SMS0 is configured for the SDRAM.

The flash memory is implemented with two Dual-Bank flash memory devices. These devices include primary and secondary flash memory as well as internal SRAM and registers. Primary flash memory totals 2 Mbytes mapped into two separate asynchronous memory banks, 1 Mbyte each. Secondary flash memory, along with SRAM and registers, occupies the third bank of asynchronous memory space. The processor’s ~AMS0, ~AMS1, and ~AMS2 memory select pins are used for that purpose.

Table 1-1. EZ-KIT Lite Evaluation Board Memory Map

Start Address End Address Content

External Memory

0x0000 0000 0x07FF FFFF SDRAM Bank 0 (SDRAM). See “SDRAM Interface” on page 1-7.

0x2000 0000 0x200F FFFF ASYNC Memory Bank 0 (Primary Flash A). See “Flash Memory” on page 1-8.

0x2010 0000 0x201F FFFF ASYNC Memory Bank 1 (Primary Flash B). See “Flash Memory” on page 1-8.

0x2020 0000 0x202F FFFF ASYNC Memory Bank 2 (Flash A and B Secondary Memory, SRAM and Internal Registers). See “Flash Memory” on page 1-8.

All other locations Not used


Using EZ-KIT Lite

SDRAM InterfaceThe three SDRAM control registers must be initialized in order to use the MT48LC32M16 - 64 MB (32M x 16 bits) SDRAM memory.

If you are in an EZ-KIT Lite or emulator session, the SDRAM registers are set to the values in Table 1-2 automatically when a reset operation is performed. Clearing the Use XML reset values check box on the Target Options dialog box, which is accessible through the Settings pull-down menu, disables this feature. For more information see the “Target Options” on page 1-18.The numbers were derived for maximum flexibil-ity and work for a system clock frequency between 54 MHz and 133 MHz.

Automatic configuration of SDRAM is not optimized for any SCLK fre-quency. Table 1-2 shows the optimized configuration for the SDRAM registers using a 118.8 MHz, 126 MHz, and 133 MHz SCLK. The fre-

Internal Memory

0xFF80 0000 0xFF80 3FFF Data Bank A SRAM 16 KB

0xFF80 4000 0xFF80 7FFF Data Bank A SRAM/CACHE 16 KB

0xFF90 0000 0xFF90 3FFF Data Bank B SRAM 16 KB

0xFF90 4000 0xFF90 7FFF Data Bank B SRAM/CACHE 16 KB

0xFFA0 0000 0xFFA0 FFFF Instruction SRAM 64 KB

0xFFA1 0000 0xFFA1 3FFF Instruction SRAM /CACHE 16 KB

0xFFB0 0000 0xFFBO 0FFF Scratch Pad SRAM 4 KB

0xFFC0 0000 0xFFDF FFFF System MMRs 2 MB

0xFFE0 0000 0xFFFF FFFF Core MMRs 2 MB

All other locations Reserved

Table 1-1. EZ-KIT Lite Evaluation Board Memory Map (Cont’d)



Flash Memory

quency of 118.8 MHz is the maximum SCLK frequency when using a 594 MHz core frequency, the maximum frequency for the EZ-KIT Lite when using the internal voltage regulator. Only the EBIU_SDRRC register needs to be modified in the user code to achieve maximum performance.

An example program is included in the EZ-KIT installation directory to demonstrate how to set up the SDRAM interface.

Flash MemoryThe following sections describe how to use the memory and general-pur-pose IO pins, as well as how to configure the flash memory device.

The ADSP-BF533 EZ-KIT Lite board employs two PSD4256G6V Flash/General-Purpose IO devices from STMicroelectronics. These devices not only have flash memory but also extra IO pins, which are memory mapped.

Example code is provided in the EZ-KIT installation directory to demon-strate how to program the flash memory as well as to demonstrate the functionality of the general-purpose IO pins.

Table 1-2. SDRAM Optimum Settings

Register SCLK = 133 MHz(Processor MAX)

SCLK = 126 MHz(CCLK = 756 MHz)

SCLK = 118.8 MHz(CCLK = 594 MHz)

EBIU_SDGCTL 0x0091 998D 0x0091 998D 0x0091 998D

EBIU_SDBCTL 0x0000 0025 0x0000 0025 0x0000 0025

EBIU_SDRRC 0x0000 0406 0x0000 03CF 0x0000 0397


Using EZ-KIT Lite

Flash Memory MapEach device includes the following memory segments:

• 1M byte of primary flash memory

• 64K bytes of secondary flash memory

• 32 Kbytes of internal SRAM

• 256 Bytes of configuration registers (IO control)

Access to each segment can be 8-bit or 16-bit. The processor’s ~AMS0, ~AMS1, and ~AMS2 memory select pin are used for that purpose. Asynchro-nous memory Bank 0 is always enabled after a hard reset, while Banks 1 and 2 need to be enabled by software. Table 1-3 provides an example on asynchronous memory configuration registers.

Each flash chip is initially configured with the memory sectors mapped into the processor’s address space as shown in Table 1-4.

Table 1-3. Asynchronous Memory Control Registers Settings Example

Register Value Function

EBIU_AMBCTL0 0x7BB07BB0 Timing control for Banks 1 and 0

EBIU_AMBCTL1 bits 15-0 0x7BB0 Timing control for Bank 2 (Bank 3 is not used)

EBIU_AMGCTL bits 3-0 0xF Enable all banks

Table 1-4. Flash Memory Map


0x2000 0000 0x200F FFFF Flash A Primary (1MB)

0x2010 0000 0x201F FFFF Flash B Primary (1MB)

0x2020 0000 0x2020 FFFF Flash A Secondary (64KB)


Flash Memory

Flash General-Purpose IOThis section describes general-purpose IO signals that are controlled by means of setting appropriate registers of the Flash A or Flash B. These reg-isters are mapped into the processor’s address space, as shown in Table 1-4.

Flash device IO pins are arranged as 8-bit ports labeled A through G. There is a set of 8-bit registers associated with each port. These registers are: Direction, Data In, and Data Out. Note that the Direction and Data Out registers are cleared to all zeros at power-up or hardware reset.

The Direction register controls IO pins direction. When a bit is 0, a cor-responding pin functions as an input. When the bit is 1, a corresponding pin is an output. This is a 8-bit read-write register.

The Data In register allows reading the status of port’s pins. This is a 8-bit read-only register.

The Data Out register allows clearing an output pin to 0 or setting it to 1. This is a 8-bit read-write register.

0x2024 0000 0x2024 7FFF Flash A SRAM (32KB)

0x2027 0000 0x2027 00FF Flash A Registers (256 Bytes)

0x2028 0000 0x2028 FFFF Flash B Secondary (64KB)

0x202C 0000 0x202C 7FFF Flash B SRAM (32KB)

0x202E 0000 0x202E 00FF Flash B Registers (256 Bytes)

All other locations Reserved

Table 1-4. Flash Memory Map (Cont’d)



Using EZ-KIT Lite

The ADSP-BF533 EZ-KIT Lite board employs only Flash A and Flash B ports A and B. Table 1-5 and Table 1-6 provide configuration register addresses for Flash A and Flash B, respectively (only ports A and B are listed). The following bits connect to the Expansion Board connector.

• Flash A port B bits 7 and 6

• Flash B port A bits 7–0 and port B bits 7–0

Table 1-7 and Table 1-8 depict the IO assignments.

Table 1-5. Flash A Configuration Registers for Port A, B

Register Name Port A Address Port B Address

Data In (Read-only) 0x2027 0000 0x2027 0001

Data Out (Read-Write) 0x2027 0004 0x2027 0005

Direction (Read-Write) 0x2027 0006 0x2027 0007

Table 1-6. Flash B Configuration Registers for Port A, B

Register Name Port A Address Port B Address

Data In (Read-only) 0x202E 0000 0x202E 0001

Data Out (Read-Write) 0x202E 0004 0x202E 0005

Direction (Read-Write) 0x202E 0006 0x202E 0007

Table 1-7. Flash A Port A Controls

Bit # User IO Bit Value

7 Not defined Any

6 Not defined Any

5 PPI Clock Select bit 1 00 = Local OSC (27 MHz)

4 PPI Clock Select bit 0 01= Video Decoder Pixel Clock1X = Expansion Board PPI Clock


Flash Memory

Configuring Flash MemoryThe flash memory is completely configurable. To modify the default setup of each flash, you must use PSDsoft Express™ software. After the project has been modified, the flash memory must be re-programmed using FlashLINK™. The default project file is provided in \…\Black-fin\EZ-KITs\ADSP-BF533\PSDConfigFiles directory. Analog Devices does not provide any support for setting up the PSD4256G6V with PSDsoft Express or programming it using FlashLINK. Email STMicroelectronics at [email protected] for technical assistance.

3 Video Decoder Reset 0= Reset ON; 1= Reset OFF

2 Video Encoder Reset 0= Reset ON; 1= Reset OFF

1 Reserved Any

0 Codec Reset 0= Reset ON; 1= Reset OFF

Table 1-8. Flash A Port B Controls


7 Not used Any

6 Not used Any

5 LED9 0= LED OFF; 1= LED ON






Table 1-7. Flash A Port A Controls (Cont’d)



Using EZ-KIT Lite

The PSD4256G6Vcan be re-programmed using the FlashLINK JTAG programming cable available from STMicoreclectronics (www.st.com/psd) for approximately $59. FlashLINK plugs into any PC parallel port. The PSDsoft Express development software is required to modify the DSM2150 configuration and to operate the FlashLINK cable. PSDsoft Express can be downloaded at no charge from www.st.com/psd.

LEDs and Push ButtonsThe EZ-KIT Lite provides four push buttons and six LEDs for gen-eral-purpose IO.

The six LEDs, labeled LED4 through LED9, are accessed via some of the general-purpose IO pins of flash memory interface. For information on how to program the pins, see “Flash General-Purpose IO” on page 1-10.

The four general-purpose push button are labeled SW4 through SW7. A sta-tus of each individual button can be read through programmable flag (PF) inputs, PF8 through PF11. A PF reads “1” when a corresponding switch is being pressed-on. When the switch is released, the PF reads “0”. A connec-tion between the push button and PF input is established through the SW9 DIP switch. See “Push Button Enable Switch (SW9)” on page 2-11 for details.

An example program is included in the EZ-KIT installation directory to demonstrate the functionality of the LEDs and push buttons.

Audio InterfaceThe AD1836 audio codec provides three channels of stereo audio output and two channels of multichannel 96 kHz input. The SPORT0 interface of the processor is linked with the stereo audio data input and output pins of


Audio Interface

the AD1836 codec. The processor is capable of transferring data to the audio codec in time-division multiplexed (TDM) or Two-Wire Interface (TWI) mode.

The TWI mode allows the codec to operate with a 96 kHz sample rate but only allows you to use two channels of output. TDM mode can operate at a maximum of 48 kHz sample rate but allows for simultaneous use of all input and output channels. When using TWI mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and RFS0 pins of the processor, must be tied together external to the processor. This is accomplished with the SW9 DIP switch (see “Push Button Enable Switch (SW9)” on page 2-11 for more information).

The AD1836 audio codec’s internal configuration registers are configured using the processor’s SPI port. The processor’s PF4 programmable flag pin is used as the select for this device. For information on how to configure the multichannel codec, go to www.analog.com/UploadedFiles/Datasheets/344740003AD1836_prc.pdf.

The reset for the AD1836 codec comes from the general-purpose IO pin PA0 of Flash A. For information on how to use the pin, see “Flash Gen-eral-Purpose IO” on page 1-10.

Example programs are included in the EZ-KIT installation directory to demonstrate the AD1836 codec operation.


Using EZ-KIT Lite

Video InterfaceThe board supports video input and output applications. The ADV7171 video encoder provides up to three output channels of analog video, while the ADV7183 video decoder provides up to three input channels of analog video. Both the encoder and the decoder connect to the Parallel Peripheral Interface (PPI) of the ADSP-BF533 processor. For additional information on the video interface hardware, refer to “PPI Interface” on page 2-5.

For the video interface to be operational, the following basic steps must be performed.

1. Configure the SW3 DIP switch as required by the application. Refer to “Video Configuration Switch (SW3)” on page 2-10 for details.

2. Remove reset to the video device. Refer to “Flash General-Purpose IO” on page 1-10 for details.

3. If using the decoder:

Enable device by driving programmable flag output PF2 to “0”.Select PPI clock (see Table 1-7 on page 1-11).

4. Program internal registers of the video device in use. Both video encoder and decoder use a 2-wire serial interface to access internal registers. A programmable flag PF0 functions as a serial clock (SCL), and PF1 functions as a serial data (SDAT).

5. Program the ADSP-BF533 processor’s PPI interface (configuration registers, DMA, etc.).

Example programs are included in the EZ-KIT installation directory to demonstrate the capabilities of the video interface.


Example Programs

Example ProgramsExample programs are provided with the ADSP-BF533 EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in the \…\Blackfin\EZ-KITs\ADSP-BF533\Examples subdirectory of the Visu-alDSP++ installation directory. Please refer to the readme file provided with each example for more information.

Background Telemetry ChannelThe ADSP-BF533 USB debug agent supports the Background Telemetry Channel (BTC), which facilitates data exchange between VisualDSP++ and the processor without interrupting processor execution.

The BTC allows the user to view a variable as it is updated or changed, all while the processor continues to execute. For increased performance of the BTC, including faster reading and writing, please check out our latest line of processor emulators at www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULA-

TORS,00.html. For more information about the Background Telemetry Channel, see the VisualDSP++ User’s Guide or online Help.

VisualDSP++ InterfaceThis section provides information on the following parts of the Visu-alDSP++ graphical user interface:

• “Trace Window” on page 1-17

• “Boot Load” on page 1-18

• “Target Options” on page 1-18


Using EZ-KIT Lite

• “Restricted Software Breakpoints” on page 1-20

Trace WindowChoosing the Trace command from the View–>Debug Windows menu opens the Trace window (Figure 1-2).

The trace buffer stores a history of the last 16 changes in program flow taken by the program sequencer. View the history to recreate the program sequencer’s most recent path.

The trace buffer does not track changes in flow caused by zero-overhead loops or while in the reset service routine.

To use the trace buffer, ensure your program leaves the reset service routine.

Enabling Trace Buffer

To view trace history in the Trace window, first, enable the trace buffer (choose Enable Trace from the Tools–>Trace menu). On each halt, the Trace window is updated with the changes that occurred since the last halt. Reading the trace buffer destroys the trace buffer’s contents and dis-cards the information previously stored before the last run.

Figure 1-2. Trace Window


VisualDSP++ Interface

Reading Trace Buffer Data

The first column between the square brackets (in blue) indicates the line number in the Trace window.

The second column between square brackets, which comes in vertical pairs, shows the trace number. For each discontinuity, the first (top posi-tion) is the source trace, and the second (bottom position) is the destination trace. The third column in between square brackets shows the addresses of the instructions. Each address is followed by the assembly instruction.

The trace grows upward. In Figure 1-2, trace 0 occurred before trace 1, which occurred before trace 2, and so on.

Boot LoadChoosing Boot Load from the Settings menu runs the processor and per-forms a hard reset on the board. This command saves you from having to shut down VisualDSP++, reset the EZ-KIT Lite board, and bring up Visu-alDSP++ again when you want to perform a hard reset.

Use this feature when loading debug boot code from an external part or when you want to put the device into a known state.

Target OptionsChoosing Target Options from the Settings menu opens the Target Options dialog box (Figure 1-3). Use target options to control certain aspects of the processor on the ADSP-BF533 EZ-KIT Lite evaluation system.


Using EZ-KIT Lite

Reset Options

Reset options control how the processor behaves when a reset occurs. The reset options are described in Table 1-9.

On Emulator Exit

This target option controls processor behavior when VisualDSP++ relin-quishes processor control (for example, when exiting VisualDSP++). The option is described in Table 1-10.

Other Options

Table 1-11 describes other available target options.

Figure 1-3. Target Options Dialog Box

Table 1-9. Reset Options

Option Description

Core reset Resets the core when the debugger executes a reset.

System reset Resets the peripherals when the debugger executes a reset.



Restricted Software Breakpoints

The EZ-KIT Lite development system restricts breakpoint placement when certain conditions are met. That is, under some conditions, breakpoints can-not be placed effectively. Such conditions depend on bus architecture, pipeline

Table 1-10. On Emulator Exit Target Options

Option Description

On Emulator Exit Determines the state the processor is left in when the emulator relinquishes control of the processor:Reset DSP and Run causes the processor to reset and begin execution from its reset vector location.Run from current PC causes the processor to begin running from its current location. Stall the DSP resets the processor and then writes a JUMP 0 to the first loca-tion in internal memory so the processor is stuck in a tight loop after exit-ing.

Table 1-11. Miscellaneous Target Options

Option Description

Verify all writes to target memory

Validates all memory writes to the processor. After each write, a read is performed and the values are checked for a matching condition.Enable this option during initial program development to locate and fix initial build problems (such as attempting to load data into non-existent memory). Clear this option to increase performance while loading executable files, since VisualDSP++ does not perform the extra reads that are required to verify each write.

Reset cycle counters on run

Resets the cycle count registers to zero before a Run command is issued. Select this option to count the number of cycles executed between breakpoints in a program.

Use XML reset values Uses a section in the processor-specific .XML file located in the installation’s system folder. The file defines registers that are reset to certain values. The values are read at startup and subsequently used to set the registers when a reset is performed through Visu-alDSP++.


Using EZ-KIT Lite

depth, and ordering of the EZ-KIT Lite and its target processor.


2 EZ-KIT LITE HARDWARE REFERENCE

This chapter describes the hardware design of the ADSP-BF533 EZ-KIT
Lite board. The following topics are covered.
• “System Architecture” on page 2-2Describes the configuration of the ADSP-BF533 EZ-KIT Lite board and explains how the board components interface with the processor.

• “Jumper and Switch Settings” on page 2-9Shows the location and describes the function of the configuration jumpers and switches.

• “LEDs and Push Buttons” on page 2-13Shows the location and describes the function of the LEDs and push buttons.

• “Connectors” on page 2-16Shows the location and gives the part number for all of the connec-tors on the board. Also, the manufacturer and part number information is given for the mating parts.


System Architecture

System ArchitectureThis section describes the processor’s configuration on the EZ-KIT Lite board.

The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF533 Blackfin processor. The processor has IO voltage of 3.3V. The core voltage is derived from this 3.3v supply and uses the internal reg-ulator of the processor. The core voltage and the core clock rate can be set on the fly by the processor. Refer to the Hardware Reference Manual for more information.

Figure 2-1. System Architecture

ADSP-BF533Processor

AD1836Codec

JTAG Header

PowerRegulation

LEDs (6)

EBUI

JTA G

Port

A5V

+7.5

VC

onne

ctor

32.768 KHzOscillator RTC

SPI

32 MBSDRAM

(16M x 16-bit)

ExpansionConnectors

(3)

2 MBFlash

(1M x 8-bit x 2-chips)

27 MHzOscillator

ADV7183Video

Decoder

ADV7171Video

Encoder

Video OutPhono

Jacks (3)

Video InPhono

Jacks (3)

3.3V

StereoOut

PhonoJacks (6)

Stereo InPhono

Jacks (4)

UART SPORT1 PBs (4)

RS-232Male

ADM3202RS-232TX/RX

SPORT0 PPI/PFs

SPORT0


EZ-KIT Lite Hardware Reference

The default mode for the processor is flash boot. See “Boot Mode Select Jumpers (JP2–1)” on page 2-10 for information about changing the default boot mode.

External Bus Interface UnitThe External Bus Interface Unit (EBIU) connects an external memory to the ADSP-BF533 device. It includes a 16-bit wide data bus, an address bus, and a control bus. Both 16-bit and 8-bit access are supported. On the EZ-KIT Lite, the EBI unit connects to SDRAM and flash memory.

64 MB (32M x 16 bits) of SDRAM connect to the synchronous memory select 0 pin (~SMS0). Refer to “SDRAM Interface” on page 1-7 for infor-mation about configuring the SDRAM. Note that SDRAM clock is the processor’s Clock Out (CLK OUT), which frequency should not exceed 133 MHz.

Two flash memory devices are connected to the asynchronous memory select signals, ~AMS2 through ~AMS0. The devices provide total of 2 Mbytes of primary flash memory, 128 Kbytes of secondary flash memory, and 64 Kbytes of SRAM. The processor can use this memory for both booting and storing information during normal operation. Refer to “Flash Mem-ory” on page 1-8 for details.

All of the address, data, and control signals are available externally via the extender connectors P3–1. The pinout of these connectors can be found in Appendix B, “Schematics” on page B-1.

SPORT0 Audio InterfaceThe SPORT0 interface is connected to the AD1836 audio codec, the SPORT connector (P3), and the expansion interface. The AD1836 codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio input and outputs.


System Architecture

The pinout of the SPORT connector and the expansion interface connec-tors can be found in Appendix B, “Schematics” on page B-1.

SPI InterfaceThe processor’s Serial Peripheral Interconnect (SPI) interface is connected to the AD1836 audio codec and the expansion interface. The SPI connec-tion to the AD1836 is used to access the control registers of the device. The PF4 flag of the processor is used as the devices select for the SPI port.

Programmable Flags

The processor has 15 programmable flag pins (PFs). The pins have multi-ple functions, depending on the setup of the processor. Table 2-1 shows how the programmable flag pins are used on the EZ-KIT Lite.

Table 2-1. Programmable Flag Connections

Processor PF Pin Other Processor Function EZ-KIT Function

PF0 Serial clock for programming ADV7171 and ADV7183

PF1 Serial data for programming ADV7171 and ADV7183

PF2 ADV7183 ~OE

PF3 FS3 ADV7183 Field Pin. See “Video Configuration Switch (SW3)” on page 2-10.

PF4 AD1836 SPI Select

PF5

PF6

PF7



PPI InterfaceThe Parallel Peripheral Interface (PPI) of the ADSP-BF533 processor is a half-duplex, bi-directional port that can accommodate up to 16 bits of data. The interface has a dedicated input clock (27 MHz), three multi-plexed frame sync signals, and four bits of dedicated data. The remaining data bits come from re-configured programmable flag pins. For informa-tion about the pins, which multiplexed with the PPI, see “Programmable Flags” on page 2-4. For information about the ADSP-BF533 processor

PF8 Push button (SW4). See “LEDs and Push But-tons” on page 1-13 and “Push Button Enable Switch (SW9)” on page 2-11 for information on how to disable the push button.




PF12 PPI7 ADV7171 and ADV7183 Data (MSB)

PF13 PPI6 ADV7171 and ADV7183 Data



Table 2-1. Programmable Flag Connections (Cont’d)

Processor PF Pin Other Processor Function EZ-KIT Function


System Architecture

PPI interface, refer to the ADSP-BF533 Blackfin Processor Hardware Refer-ence. Table 2-2 describes the PPI pins and their use on the EZ-KIT Lite board.

The ADSP-BF533 EZ-KIT Lite board employs 8-bit PPI interface for video output and video input.

Table 2-2. PPI Connections

Processor PPI Pin Other Processor Function EZ-KIT Function

PPI7 PF12 ADV7171 and ADV7183 Data (MSB)

PPI6 PF13 ADV7171 and ADV7183 Data



PPI3 ADV7171 and ADV7183 Data




PF3 FS3 ADV7183 Field Pin. For more information, see “Video Configuration Switch (SW3)” on page 2-10.

TMR1 PPI_HSYNC ADV7171 and ADV7183 HSYNC. For more information, see “Video Configuration Switch (SW3)” on page 2-10.

TMR2 PPI_FSYNC ADV7171 and ADV7183 VSYNC. For more information, see “Video Configuration Switch (SW3)” on page 2-10.

PPI_CLK Input from either the ADV7183 output clock or the same 27 MHz oscillator driving the processor. For more information, see “Video Interface” on page 1-15.



Video Output Mode

In the video output mode, the PPI interface is configured as output and connects to the on-board video encoder device, ADV7171. The ADV7171 encoder device generates three analog video channels on DAC B, DAC C, and DAC D outputs. The PPI data connects to P7–0 of the encoder’s pixel inputs. The encoder’s PPI input clock runs at 27 MHz, and it is in phase with CLK IN of the ADSP-BF533 processor.

The encoder’s synchronization signals, HSYNC and VSYNC, can be config-ured as inputs or outputs. Video Blanking control signal is at level “1”. The HSYNC and VSYNC signals can be connected to the ADSP-BF533 pro-cessor’s multiplexed sync pins and to the on-board video decoder, ADV7183, via the SW3 switch, as described in “Video Configuration Switch (SW3)” on page 2-10.

Video Input Mode

In the video input mode, the PPI interface is configured as input and con-nects to the on-board video decoder device, ADV7183. The ADV7183 decoder receives three analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel data outputs P15–8 drive the PPI data (PPI3–0 and PF15–12). The decoder’s 27 MHz pixel clock output can be selected to drive PPI clock, as shown in Table 1-7 on page 1-11.

Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and FIELD can connected to the ADSP-BF533 processor’s multiplexed sync pins and to the on-board video encoder, ADV7171, via the SW3 DIP switch, as described in “Video Configuration Switch (SW3)” on page 2-10.


System Architecture

UART PortThe processor’ Universal Asynchronous Receiver/Transmitter (UART) port is connected to the ADM3202 RS232 line driver as well as to the expansion interface. The RS232 line driver is connected to the DB9 male connector, allowing you to interface with a PC or other serial device.

Expansion InterfaceThe expansion interface consists of the three 90-pin connectors. Table 2-3 on page 2-8 shows the interfaces each connector provides. For the exact pinout of these connectors, refer to Appendix B, “Schematics” on page B-1. The mechanical dimensions of the connectors can be obtained from Technical or Customer Support.

Limits to the current and to the interface speed must be taken into consid-eration when you use the expansion interface. The maximum current limit is dependent on the capabilities of the regulator used. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed.

Analog Devices does not support and is not responsible for the effects of additional circuitry.

Table 2-3. Connector Interfaces

Connector Interfaces

J1 5V, G ND, Address, Data, PPI

J2 3.3V, GND, SPI, NMI, TMR2–0, SPORT0, SPORT1, PF15–0, EBUI control signals

J3 5V, 3.3V, GND, UART, Flash IO, Reset, Video control signals



JTAG Emulation PortThe JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emu-lation port of the processor is also connected to the USB debugging interface. When an emulator is connected to the board at P4, the USB debugging interface is disabled. See “JTAG (P4)” on page 2-20 for more information about the JTAG connector.

To learn more about available emulators, contact Analog Devices (see “Product Information”).

Jumper and Switch SettingsThis section describes the operation of the jumpers and DIP switches. The jumpers and switch locations are shown in Figure 2-2.

Figure 2-2. Jumper and Switch Locations


Jumper and Switch Settings

Boot Mode Select Jumpers (JP2–1)The JP1 and JP2 jumpers determine the boot mode of the processor. Table 2-4 shows the available boot mode settings. By default, the proces-sor boots from the on-board flash memory.

Test DIP Switches (SW2–1)Two DIP switches (SW1 and SW2) are located on the bottom of the board. The switches are used only for testing and should always be in the “OFF” position.

Video Configuration Switch (SW3)The video configuration switch (SW3) controls how some video signals from the ADV7183 video decoder and ADV7171 video encoder are routed to the processor’s PPI. The switch also determines if the PF2 pin controls the OE of the ADV7183 video decoder outputs. Table 2-5 shows which processor’s signals are connected to the encoder and decoder when in the “ON” position.

Table 2-4. Boot Mode Settings

JP1 (BMODE1) JP2 (BMODE0) Boot Mode

Installed Installed 16-Bit External Memory

Installed 1

1 Default settings

Not installed Flash Memory

Not installed Installed Reserved

Not installed Not installed SPI EEPROM



Positions 1 thorough 5 of SW3 determine how and if the VSYNC, HSYNC, and FIELD control signals are routed to the processors PPI. In standard config-uration of the encoder and decoder, this is not necessary because the processor is capable of reading the embedded control information, which is in the data stream.

Position 6 of SW3 determines whether PF2 is connected to the ~OE signal of the ADV7183. When the switch “OFF”, PF2 can be used for other opera-tions, and the decoder output enable is held “HIGH” with a pull-up resistor.

Push Button Enable Switch (SW9)The push button enable switch (SW9) positions 1 through 4 allow the user to disconnect the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6 are used to connect the transmit and receive the frame syncs and clocks of SPORT0. This is important when the AD1836 video decoder and the processor are communicating in I2S mode. Table 2-6 shows which PF is driven when the switch is in the “ON” position.

Table 2-5. Video Configuration Switch (SW3)

Switch Position (Default) Processor Signal Video Signal

1 (OFF) TMR1 (HSYNC) HSYNC (ADV7171)

2 (OFF) TMR1 (HSYNC) HS (ADV7183)

3 (OFF) TMR2 (VSYNC) VS (ADV7183)

4 (OFF) TMR2 (VSYNC) VSYNC (ADV7171)

5 (OFF) PF3 (FIELD) FIELD (ADV7183)

6 (ON) PF2 ~OE (ADV7183)


Jumper and Switch Settings

Table 2-6. Push Button Enable Switch (SW9)

Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2)

1 ON 1 SW4 12 PF8

2 ON 2 SW5 11 PF9

3 ON 3 SW6 10 PF10

4 ON 4 SW7 9 PF11

5 OFF 5 TFS0 8 RFS0

6 OFF 6 RSCLK0 7 TSCLK0



LEDs and Push ButtonsThis section describes the functionality of the LEDs and push buttons. Figure 2-3 shows the locations of the LEDs and push buttons.

Programmable Flag Push Buttons (SW7–4)Four push buttons, SW7–4, are provided for general-purpose user input. The buttons connect to the processor’s programmable flag pins PF11–8. The push buttons are active “HIGH” and, when pressed, send a High (1) to the processor. Refer to “LEDs and Push Buttons” on page 1-13 for more information on how to use the PFs when programming the processor. The push button enable switch (SW9) is capable of disconnecting the push but-

Figure 2-3. LED and Push Button Locations


LEDs and Push Buttons

tons from the PF (refer to “Push Button Enable Switch (SW9)” on page 2-11 for more information). The programmable flag signals and their corresponding switches are shown in Table 2-7.

Reset Push Button (SW8)The RESET push button resets all of the ICs on the board. One exception is the USB interface chip (U34). The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communi-cation has been correctly initialized with the PC. After USB communication has been initialized, the only way to reset the USB is by powering down the board.

Power LED (LED1)When LED1 is lit (green), it indicates that power is being properly supplied to the board.

Reset LEDs (LED3–2)When LED2 is lit, it indicates that the master reset of all the major ICs is active. When LED3 is lit, the USB interface chip (U34) is being reset. The USB chips only reset on power-up, or if USB communication has not been initialized.

Table 2-7. Programmable Flag Switches

Processor Programmable Flag Pin Push Button Reference Designator

PF8 SW4

PF9 SW5

PF10 SW6

PF11 SW7



User LEDs (LED9–4)Six LEDs are connected to six of the flash memory (U5) general-purpose IO pins. The LEDs are active “HIGH” and are lit by writing a “1” to the correct memory address in the flash memory. Refer to “LEDs and Push Buttons” on page 1-13 for more information about how to use the flash when programming the LEDs.

USB Monitor LED (LED11)The USB Monitor LED (LED11) indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP++ EZ-KIT Lite session. This should take approximately 15 seconds. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver.

When VisualDSP++ is actively communicating with the EZ-KIT Lite target board, the LED can flicker, indicating communications handshake.

Table 2-8. User LEDs

LED Reference Designator Flash Port Name

LED4 PB0

LED5 PB1

LED6 PB2

LED7 PB3

LED8 PB4

LED9 PB5


Connectors

ConnectorsThis section describes the connector functionality and provides informa-tion about mating connectors. The locations of the connectors are shown in Figure 2-4.

Expansion Interface (J3–1)Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information about the expansion interface, see on page 2-8. For the availability and pricing of the J1, J2, and J3 connec-tors, contact Samtec.

Figure 2-4. Connector Locations



Audio (J5–4)

Video (J8)

Power (J9)The power connector provides all of the power necessary to operate the EZ-KIT Lite board. The power connector supplies DC power to the board. The following table shows the power connector pinout.

Part Description Manufacturer Part Number

90 Position 0.05" Spacing, SMT (J1, J2, J3)

Samtec SFC-145-T2-F-D-A

Mating Connector

90 Position 0.05” Spacing (Through Hole)

Samtec TFM-145-x1 Series

90 Position 0.05” Spacing (Surface Mount)

Samtec TFM-145-x2 Series

90 Position 0.05” Spacing (Low Cost)

Samtec TFC-145 Series


2x2 RCA Jacks (J5) SWITCHCRAFT PJRAS2X2S01


Mating Connector

Two channel RCA interconnect cable

Monster Cable BI100-1M




Connectors

The power connector supplies DC power to the EZ-KIT Lite board. Table 2-9 shows the power supply specifications.

FlashLINK (P1)The FlashLINK connector allows you to configure and program the STMicroelectronics DSM2150 flash/PLD chip. See “Configuring Flash Memory” on page 1-12 for more information about the FlashLINK connector.


2.5 mm Power Jack (J9) SWITCHCRAFT RAPC712

Digi-Key SC1152-ND

Mating Power Supply (shipped with EZ-KIT Lite)

7.5V Power Supply GlobTek TR9CC2000LCP-Y

Table 2-9. Power Supply Specification

Terminal Connection

Center pin +7.5 VDC@2amps

Outer Ring GND


Right-angle 7X2 Shrouded 0.1 spacing (J10)

TYCO 2-767004-2

Mating Assembly

FlashLINK JTAG Programmer ST Micro FL-101B



RS232 (P2)The RS232-compatible connector is described in Table 2-10.

SPORT0 (P3)The SPORT0 connector is linked to a 20-pin connector. The connector’s pinout can be found in “Schematics” on page B-1. For pricing and avail-ability on these connectors, contact AMP.

Table 2-10. RS232 Connector


DB9, Male, Right Angle (P2) Digi-Key A2096-ND

Mating Assembly

2m Female to female cable Digi-Key AE1016-ND


20 position AMPMODU system 50 receptacle (P3)

AMP 104069-1

Mating Connectors

20 position ribbon cable connec-tor

AMP 111196-4

20 position AMPMODU system 20 connector

AMP 2-487937-0

20 position AMPMODU system 20 connector (w/o lock)

AMP 2-487938-0

Flexible film contacts (20 per connector)

AMP 487547-1


Connectors

JTAG (P4)The JTAG header is the connecting point for a JTAG in-circuit emulator pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled.

Pin 3 is missing to provide keying. Pin 3 in the mating connector should have a plug.

When using an emulator with the EZ-KIT Lite board, follow the connection instructions provided with the emulator.


A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website, http://www.analog.com/Processors/Processors/DevelopmentTools/tec
hnicalLibrary/manuals/DevToolsIndex.html#Evalua-

tion%20Kit%20Manuals.

ADSP-BF533 EZ-KIT Lite Evaluation System Manual A-1

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R12

0–12

1

PHIL

IPS

9C12

063A

75R

0JL

HFT

812

30P

F 10

0V 5

% 1

206

C

206–

207

AV

X12

061A

300J

AT

2A

821

68U

F 6.

3V 2

0% D

TA

NT

CT

28PA

NA

SON

ICE

CS-

TO

JD68

6R

836

680P

F 50

V 1

% 8

05

NP

O

C

14,C

19,C

24,

C29

,C34

,C39

AVX

0805

5A68

1FA

T2A

843

10U

F 25

V +

80-2

0% 1

210

Y5V

C

198–

200

MU

RA

TA

GR

M23

5Y.5

V10

6Z02

5

Ref

.#

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber


Bill Of Materials

856

2.74

K 1

/8W

1%

120

6

R

41,R

47,R

57,

R65

,R73

,R81

PAN

ASO

NIC

ER

J-8E

NF2

741V

8612

5.49

K 1

/8W

1%

120

6

R

35,R

40,R

42,

R49

,R51

,R56

,R

59

PAN

ASO

NIC

ER

J-8E

NF5

491V

876

3.32

K 1

/8W

1%

120

6

R

36,R

43,R

52,

R60

,R68

,R76

DA

LE

CR

CW

1206

3321

FRT

1

886

1.65

K 1

/8W

1%

120

6

R

37,R

44,R

53,

R61

,R69

,R77

PAN

ASO

NIC

ER

J-8E

NF1

651V

8910

10U

F 16

V 2

0% C

AP

002

EL

EC

CT

3–12

DIG

01P

CE

3062

TR

-ND

901

53.6

K 1

/10W

1%

805

R

184

PHIL

IPS

9C08

052A

5362

FKR

T/R

911

10U

H 4

7 +

/-20

IN

D00

1

L12

DIG

0144

5-12

02-2

-ND

922

10K

50M

W 5

% B

GA

36

RN

1–2

CT

SR

T13

0B7

9315

0.00

100

MW

5%

805

R

3,R

22,R

24–2

5,R

111,

R13

2,R

135–

136,

R14

1,R

186–

189,

R21

0,R

222

VIS

HA

YC

RC

W08

05 0

.0 R

T1

941

190

100M

HZ

5A

FE

R00

2

FE

R23

MU

RA

TA

DLW

5BSN

191S

Q2

951

3.32

K 1

00M

W 1

% 8

05

C18

8 D

IG01

P3.

32K

CC

TR

-ND

963

22 1

/10W

5%

805

R14

, R18

0–18

1V

ISH

AY

/DA

LE

CR

CW

0805

220J

RT

1

976

0.68

UH

0.7

2 10

% 8

05

L

4–9

MU

RA

TA

LQ

G21

NR

68K

10T

1

Ref

.#

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber


981

1A Z

HC

S100

0 SO

T23

D

SCH

OT

TK

Y

D

5Z

ET

EX

ZH

CS1

000

991

5.6K

1/1

0W 5

% 8

05

R14

0V

ISH

AY

CR

CW

0805

562J

RT

1

100

32.

2UH

0.6

3 10

% 8

05

L1–

3M

UR

AT

AL

QG

21N

2R2K

10

101

31U

F 10

V 1

0% 8

05

C

60–6

1,C

104

AVX

0805

ZC

105K

AT

2A

102

218

PF

50V

DC

5%

805

CE

RM

C

1, C

3PA

NA

SON

ICE

CJ-

2VC

1H18

0J

103

110

M 1

/8W

5%

805

R20

AVX

CR

21-1

06J-

T

104

1D

B9

9PIN

DB

9MR

IGH

T A

NG

LE

MA

LE

P

23M

7872

03-2

105

71K

1/8

W 5

% 1

206

R

115,

R11

8–11

9,R

125–

126,

R13

1AV

XC

R32

-102

J-T

106

310

0K 1

/8W

5%

120

6

R11

2,R

130,

R17

6C

R12

06-1

003F

RT

1

107

222

1/8

W 5

% 1

206

R

200,

R20

7D

AL

EC

RC

W12

0622

0JR

T1

108

927

0 1/

8W 5

% 1

206

R

146–

147,

R16

0–16

2,R

164–

165,

R16

8,R

195

AVX

CR

32-2

71J-

T

109

168

0 1/

8W 5

% 1

206

R

163

AVX

CR

32-6

81J-

T

110

115

0 1/

8W 1

% 1

206

R

122

PAN

ASO

NIC

ER

J-8E

NF1

500V

111

2R

ED

-SM

T L

ED

001

GU

LL

-WIN

G

L

ED

2–3

PAN

ASO

NIC

LN

1261

C

Ref

.#

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber


Bill Of Materials

112

1G

RE

EN

-SM

T L

ED

001

GU

LL

-WIN

G

LE

D1

PAN

ASO

NIC

LN

1361

C

113

660

4 1/

8W 1

% 1

206

R

39,R

46,R

55,

R63

,R71

,R79

PAN

ASO

NIC

ER

J-8E

NF6

040V

114

41u

F 25

V 2

0% A

TA

NT

-55

+125

C

T17

–20

PAN

ASO

NIC

EC

S-T

1EY

105R

115

2A

DG

774A

QSO

P16

QU

ICK

SWIT

CH

-257

U37

–38

AN

ALO

G

DE

VIC

ES

AD

G77

4AB

RQ

116

1ID

C 7

X2

IDC

7X2

HE

AD

ER

P4

BE

RG

5410

2-T

08-0

7

117

12.

5A R

ESE

TA

BL

E F

US0

01

F1

RA

YC

HE

M

CO

RP.

SMD

250-

2

Ref

.#

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber


A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of

DEVICESANALOG 20 Cotton Road

DNP = Do Not Populate

ADSP-BF533 EZ-KIT Lite

1212-21-2004_15:13 1

ADSP-BF533 EZ-KIT LITE - TITLE

3.3V

3.3V

3.3V

3.3V

3.3V

IN

O1

O10

O2

O3

O4

O5

O6

O7

O8

O9

NC1 NC2

TERM1 TERM2

CLK2

CLK1

GND

CLK3VDD

CLK4

CLKOUTREF

3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



OE OUT

OE OUT

JUMPERSHORTING

JUMPERSHORTING

A1

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

A3

A4

A5

A6

A7

A8

A9

AMS3ARDY

CLKIN

CLKOUT

D0

D1

D10

D11

D12

D13

D14

D15

D2

D3

D4

D5

D6

D7

D8

D9

NMI

SA10

SCKE

VROUT1

VROUT2

XTALO

~ABE0/SDQM0

~ABE1/SDQM1

AMS0

AMS1

AMS2

AOE

ARE

AWE

BG

BGH

BR

RESET

SCAS

SMS

SRAS

SWE

BMODE0

BMODE1

DR0PRI

DR0SEC

DR1PRI

DR1SEC

DT0PRI

DT0SEC

DT1PRI

DT1SEC

PF0

PF1

PF10

PF11

PF12

PF13

PF14

PF15

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PP0

PP1

PP2

PP3

PPI_CLK

RFS0

RFS1

RSCLK0

RSCLK1

RTXI

RTXO

RX

SCK

TCK

TDI

TDO

TFS0

TFS1

TMR0

TMR1

TMR2 TMS

TSCLK0

TSCLK1

TX

EMU

TRST

MOSI

MISO

RTC

Can be used to provide DSP clock frequencyother than that of the Video Interface.

Not populated in standard EZ-KIT Configuration.

DEFAULT BOOT MODE = FLASH BOOT

12212-21-2004_15:13

N4

P3

K1

J2

G3

F3

H1

H2

F2

E3

D2

C1

A4

A5

B5

B6

A6

C6

C2

C3

B1

B2

B3

B4

A2

A3

C8

B8

A7

B7

C9

J3

G2

L1

G1

A9

A8

L3

D1

P2

M3

N3

H3

E1

L2

M1

K2 N2

J1

F1

K3

M2

N1

D3

E2

U1

MINIBGA160ADSP-BF533-750

J14

M13

M14

N14

N13

N12

M11

N11

P13

P12

P11

K14

L14

J13

K13

L13

K12

L12

M12

E13

A12

B14

M9

N9

N6

P6

M5

N5

P5

P4

P9

M8

N8

P8

M7

N7

P7

M6

B10

E12

B13

A13

A11

H13

H12

E14

F14

F13

G12

G13

G14

H14

P10

N10

D14

C10

C14

C13

D13

D12

B12

U1

ADSP-BF533-750MINIBGA160

2

1

2X1IDC2X1

JP1

BMODE1

BMODE0

SJ3

DEFAULT=JP2=NOT INSTALLED

DEFAULT=JP1=INSTALLED

SJ2

R3

8050.00

DNP

1

2

JP2

IDC2X12X1

1 3

U3

OSC00327MHZ27MHZ

31

DNP

30.0000MHZOSC003

U36R224

DNP

33805

DSP_CLK

R22510K805

EXT_DSP_CLK

R19DNP805

80533R179

R2

80510K

ADSP-BF533 EZ-KIT LITE - DSP

2

3

4

56

7

81

IDT2305-1DCSOIC8

U46

2

1

3

4

U2

OSC00832.768KHZ

1

3

19

5

7

9

11

12

14

16

18

U4

QSOP20IDT74FCT3807AQ

R18022805

CLK_OUT_EXP1

CLK_OUT_EXP2

80522R181

R109

DNP

22805

CLK_OUT

CLK_OUT

80522R14

R7

DNP

33805

80533R8

C3

80518PF

C1

80518PF

R2010M805

R533805

PPI_27MHZ_CLK

ADV7183_27MHZ_CLK

ADV7171_27MHZ_CLK

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D[0:15]

D15

A11

A10

A8

A9

A12

A4

A1

A19

A17

A15

A[1:19]

A5

A2

A3

A6

A7

A13

A14

A16

A18

BG

NMI

RESET

VROUT

DSP_CLK

RTXORTXI

10K805

R10

DNP

0.00805

R11

10K805

R1810K805

R15

4.7K805

R17

R16

80510K

PPI_CLK

TSCLK1

DSCLK1

TSCLK0

RSCLK0

TDO

TDI

R4

80510K

ARDY

R933805

C2

8050.1UF

DNP

DR1SEC

TRST

TMS

PP1

PP[0:3]

PP3

PP2

PP0

TCK

10K805

R12

80533R6

PF[0:15]PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

80510KR1

RTXO

RTXI

TMR0

TMR1

TMR2

MOSI

MISO

SCK

TX

RX

EMU

RFS1

DR1PRI

TFS1

DT1PRI

DT1SEC

RFS0

DR0PRI

TFS0

DT0PRI

DT0SEC

DR0SEC

10K805

R13

AMS0

AMS1

AMS2

AMS3

BGH

BR

~ABE1/SDQM1

~ABE0/SDQM0

AWE

ARE

AOE

SRAS

SCAS

SWE

SCKE

SA10

SMS

3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



3.3V

COM2

R16

R15

R14

R13

R12

R10

R24

R23

R22

R21

R20

R19

R27

R28

R29

R30

R31

R32

R2

R3

R4

R5

R6

R7

R8

R26

R1

R18

COM1

R9

R11

COM4

R25

COM3

R17

3.3V

COM2

R16

R15

R14

R13

R12

R10

R24

R23

R22

R21

R20

R19

R27

R28

R29

R30

R31

R32

R2

R3

R4

R5

R6

R7

R8

R26

R1

R18

COM1

R9

R11

COM4

R25

COM3

R17

PE7

PE3/TDO

PE2/TDI

PE1/TCK

PE0/TMS

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0CNTL1/~RD

CNTL0/~WR

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PC7

PC6

PC5

PC4

PC3

PC0

CNTL2

PF7

PF6

PF4

PF5

PF3

PF2

PF1

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

PD3

PF0

PD1

PC2

PC1

RESET

PD2

PD0PE6

PE5/~TERR

PE4/TSTAT

PE7

PE3/TDO

PE2/TDI

PE1/TCK

PE0/TMS

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0CNTL1/~RD

CNTL0/~WR

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PC7

PC6

PC5

PC4

PC3

PC0

CNTL2

PF7

PF6

PF4

PF5

PF3

PF2

PF1

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

PD3

PF0

PD1

PC2

PC1

RESET

PD2

PD0PE6

PE5/~TERR

PE4/TSTAT

A0

A1

A10

A11

A12_NC

A2

A3

A4

A5

A6

A7

A8

A9

CKE

CLK

DQ0

DQ1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQMH

DQML

CAS

CS

RAS

WE

BA1

BA0

512K x 16512K x 16FLASH A (1MB) FLASH B (1MB)

FlashLINK JTAG HEADER

SDRAM 512Mb(64MB - 32M x 16)

1212-21-2004_15:12 3

23

24

22

35

36

25

26

29

30

31

32

33

34

37

38

2

4

45

47

48

50

51

53

5

7

8

10

11

13

42

44

39

15

17

19

18

16

21

20

U8

TSOP54MT48LC32M16A2TG-75

8050.00R231

FLASH_B_RESET

R2280.00805

75

76

77 79

1

39

42

43

80

31

2

3

4

5

6

7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

32

33

34

36

35

37

38

40

41

44

45

46

47

48

51

52

53

54

55

56

57

58

59

60 61

62

63

64

65

66

67

68

71

72

73

74

78

PSD4256G6V-10UITQFP80

U6

PA1_B

~ABE0/SDQM0

RESET

32

1

74LVC00ADSOIC14

U9FLASH_RESET_C

1

3

5

7

9

11

13

2

4

6

8

10

12

14

IDC7X2SRDRA7X2

P1

~ABE1/SDQM1

~ABE0/SDQM0

SRAS

SCAS

SWE

CLK_OUT

FLASH_RESET1 2

74LVC14ASOIC14

U10

FLASH_TSTAT

78

74

73

72

71

68

67

66

65

64

63

62

6160

59

58

57

56

55

54

53

52

51

48

47

46

45

44

41

40

38

37

35

36

34

33

32

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

7

6

5

4

3

2

31

80

43

42

39

1

7977

76

75

TQFP80PSD4256G6V-10UI

U5

1UF805

C5

SMS

SCKE

SA10

PA7_A

PA6_A

PPICLK_ONBOARD_SELECT

PPICLK_AD7183_SELECT

ADV7183_RESET

ADV7171_RESET

AD1898_RESET

AD1836_RESET

LED5

LED4

LED3

LED2

LED6

LED[6:1]LED1

LED2

LED5

LED4

LED3

LED1LED[6:1]

LED6

FLASH_TCK_IN

FLASH_RESET_C

FLASH_TDO

PA5_B

PA6_B

PA7_B

PD1_B

PE7_B

PD0_B

PE6_B

FLASH_TERR

FLASH_TMS

ADV7171_RESET

ADV7183_RESET

PE6_A

PE7_A

PD2_A

PD1_A

PD0_A

E2

F3

F2

F1

E3

E1

D2

G1

G2

G3

H1

H3

J1

M1

L3

L1

K3

K2

K1

A2

A3

B1

B3

C1

C2

C3

M2

A1

J2

B2

D1

D3

L2

M3

H2

J3

BGA3610K

RN1

PB7_A

PB6_A

24

1

SOT23-5SN74LVC1G125

U7FLASH_TMS

J3

H2

M3

L2

D3

D1

B2

J2

A1

M2

C3

C2

C1

B3

B1

A3

A2

K1

K2

K3

L1

L3

M1

J1

H3

H1

G3

G2

G1

D2

E1

E3

F1

F2

F3

E2

BGA3610K

RN2

8050.00

DNPR21

8050.00

DNPR23

8050.00R22

8050.00R25

8050.00R24

80510KR26

PE6_A

PE7_A

FLASH_TDO_A

FLASH_TDI FLASH_TSTAT

FLASH_TERR

FLASH_TCK_IN

FLASH_TDO

FLASH_TMS

FLASH_TCK

FLASH_TDI_A

PD0_A

PD1_A

PD2_A

AWE

PC4_A

PC5_A

AMS0

ADSP-BF533 EZ-KIT LITE - MEMORY

~ABE1/SDQM1

FLASH_RESET

FLASH_TERR

FLASH_TSTAT

FLASH_TDO_A

AOE

AWE

AMS2

FLASH_TDI

FLASH_TDO

FLASH_TDI_A

FLASH_TDO_B

FLASH_TCK

FLASH_TDI_B

FLASH_TDI_A

PB7_A

PB6_A

PA6_A


PA7_A


AD1898_RESET

AD1836_RESET

PC5_A

PC4_A

PB4_B

PB5_B

PB6_B

PB3_B

PB7_B

PB2_B

PB1_B

PB0_B

PA4_B

PA3_B

PA2_B

PC5_B

PD2_B

PA0_B

PC4_B

0.1UF805

C125

FLASH_RESET

PE7_B

PB7_B

PB6_B

PB5_B

PB4_B

PB3_B

PB2_B

PB1_B

PB0_B

PA7_B

PA6_B

PA5_B

PA4_B

PA3_B

PA2_B

PA1_B

PA0_B

PC5_B

PC4_B

~ABE1/SDQM1

~ABE0/SDQM0

AWE

PD1_B

PD2_B

PD0_BPE6_B

FLASH_TERR

FLASH_TSTAT

D12

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

D0D0

D1

D2

D4

D6

D11

D12

D13

D14

D15

D8

D7

D0

D1

D2

D3

D4

D5

D6

D9

D10

D11

D12

D13

D14

D15

D[0:15]

D8

D9

D7

D3D3

D5

D10

D14

D13

D15

FLASH_TDO_B

FLASH_TDI_B

FLASH_TCK

FLASH_TMS

AOE

AWE

AMS2

AMS1

A18

A19

A5

A9A10

A1A1

A2

A3

A4

A6

A7

A8

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

A15

A16

A19

A18

A17

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A[1:19]

A2

A3

A4

A5

A6

A7

A8

A9

A12

A13

A1

AGND

AGND

AGND

AGND

3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



AGND

12

45

6

ON

3

OE OUT

3.3V

PD/RST

IN2R+/CR2/CR2

IN2R-/CR1/CR1

NC/IN2R1/IN2R+

NC/IN2R2/IN2R-

NC/IN2L2/IN2L-

NC/IN2L1/IN2L+

IN2L-/CL1/CL1

IN2L+/CL2/CL2

FILTD

FILTR

OUT3R-

OUT3R+

OUT3L-

OUT3L+

OUT2R-

OUT2R+

OUT2L-

OUT2L+

OUT1R-

OUT1R+

OUT1L-

OUT1L+

IN1R-

IN1R+

IN1L-

IN1L+

COUT

CDATA

CCLK

CLATCH

MCLK

DLRCLK

DBCLK

ASDATA1

ASDATA2

ALRCLK

ABCLK

DSDATA2

DSDATA1

DSDATA3

DAC1 LEFT

DAC1 LEFT

DAC1 RIGHT

DAC2 LEFT

DAC2 RIGHT

DAC3 LEFT

DAC3 RIGHT

ADC2 LEFT

ADC2 RIGHT

ADC1 LEFT

ADC1 RIGHT

AUDIO CODEC

For test only

DAC1 RIGHT

DA

C1

DA

C2

DA

C3

AD

C1

AD

C2

IN (J5)OUT (J4)

RIGHT (RED)

LEFT (WHITE)

12412-21-2004_15:12

R2290.00805

8050.00R230

3

27

26

25

24

23

22

21

20

12

13

34

35

5

4

32

33

7

6

30

31

9

8

19

18

17

16

49

2

51

50

45

38

41

42

36

37

47

48

44

43

MQFP52AD1836AAS

U14

10K805

R33

RFS0

RSCLK0

PF4

TFS0

TSCLK0

R29

12060.00

12060.00R28

0.001206

R27

6

5

7

SOIC8AD8606AR

U12

1

3

2

AD8606ARSOIC8

U12

1

3

2

AD8606ARSOIC8

U13

R300.001206

DAC1_LEFT

CAP00210UFCT4

49.9K1206

R45

DAC1_RIGHT

CAP00210UFCT3

OUT3R+

DT0PRI

DT0SEC

OUT3R-

OUT3L-

OUT2R-

OUT2L-

OUT1L-

OUT1R+

OUT1R-

AD1836_VREF

12062.74KR41

1 3

OSC00312.288MHZ

U11

9

7

J4

CON0243X2

8

9

J4

CON0243X2

1

2

3

4

5

6 7

8

9

10

11

12

SWT017DIP6

SW1

AD1836_CLK

SCK

8050.001UFC7

0.1UF805

C810UFB

CT2

8050.1UFC6

B10UFCT1

ADC1_RIGHT

ADC1_LEFT

DAC2_LEFT

DAC3_LEFT

DAC3_RIGHT

DAC2_RIGHT

DAC1_RIGHT

DAC1_LEFT

33805

R31

AD1836_CLK

ADSP-BF533 EZ-KIT LITE - AUDIO CODEC

80510KR32

ADC2_LEFT

ADC2_RIGHT

0.001UF805

C9

8050.001UFC10

0.001UF805

C11

AD1836_RESET

IN2R1

IN2R2

IN2L2

IN2L1

OUT1L+

OUT1L-

OUT1R+

OUT1R-

OUT2L+

OUT2R+

OUT3L+

IN1R-

IN1R+

IN1L-

IN1L+

MISO

MOSI

7

5

6

AD8606ARSOIC8

U13

5.49K1206

R49

11.0K1206

R48

12062.74KR47

1206604R46

220PF1206

C21

1.65K1206

R44

100PF1206

C20

3.32K1206

R43

5.49K1206

R42

680PF805

C19

330PF805

C18

2200PF1206

C17

5.49K1206

R40

1206604R39

220PF1206

C16

1.65K1206

R37

100PF1206

C15

3.32K1206

R36

5.49K1206

R35

680PF805

C14

330PF805

C13

11.0K1206

R34

2200PF1206

C12

OUT1L+

AD1836_VREF

AD1836_VREF49.9K1206

R38

0.001206

R193

R106

80510K10K

805

R107R108

80510K

DR0SEC

DR0PRI

AGND

AGND

AGND

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



AGND

DAC2 RIGHT

DAC3 RIGHT

DAC3 LEFTDAC2 LEFT

12512-21-2004_15:12

ADSP-BF533 EZ-KIT LITE - AUDIO OUT

1

3

2

AD8606ARSOIC8

U15

49.9K1206

R62

DAC3_RIGHT

CAP00210UFCT6

DAC3_LEFT

49.9K1206

R54

CAP00210UFCT5

49.9K1206

R78

DAC2_LEFT

CAP00210UFCT8

49.9K1206

R70

DAC2_RIGHT

CAP00210UFCT7

OUT3R-

OUT3R+

2

3

J4

CON0243X2

1206604R63

2200PF1206

C27

7

5

6

AD8606ARSOIC8

U15

5.49K1206

R64

11.0K1206

R58

2200PF1206

C22

1206604R55

1.65K1206

R53

220PF1206

C26

100PF1206

C25

3.32K1206

R52

5.49K1206

R51

11.0K1206

R50

5.49K1206

R56

12062.74KR65

220PF1206

C31

1.65K1206

R61

100PF1206

C30

3.32K1206

R60

5.49K1206

R59

680PF805

C29

330PF805

C28

12062.74KR57

680PF805

C24

330PF805

C23

AD1836_VREF

AD1836_VREF

3

1

J4

CON0243X2

OUT3L-

OUT3L+

7

5

6

AD8606ARSOIC8

U16

12062.74KR81

5.49K1206

R80

1206604R79

220PF1206

C41

1.65K1206

R77

100PF1206

C40

3.32K1206

R76

5.49K1206

R75

680PF805

C39

330PF805

C38

11.0K1206

R74

2200PF1206

C37

5

6

J4

CON0243X2

1

3

2

AD8606ARSOIC8

U16

12062.74KR73

5.49K1206

R72

1206604R71

220PF1206

C36

1.65K1206

R69

100PF1206

C35

3.32K1206

R68

5.49K1206

R67

680PF805

C34

330PF805

C33

11.0K1206

R66

2200PF1206

C32

4

6

J4

CON0243X2

AD1836_VREF

OUT2L+

OUT2L-

OUT2R+

OUT2R-

AD1836_VREF

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



AGND

AGND

AGND

ADC1 RIGHT

ADC1 LEFT

ADC2 RIGHT

ADC2 LEFT

1212-21-2004_15:12 6

6

5

7

AD8606AR

U17

SOIC8

7

5

6 U18

AD8606ARSOIC8

100PFC48

1206

C530.001UF805

C500.001UF805

C51100PF1206

0.001UFC49

805

0.001UFC52

805

2

3

1

AD8606AR

U17

SOIC8

1

3

2 U18

AD8606ARSOIC8

2

3

1

AD8606AR

U20

SOIC8

6

5

7

AD8606AR

U20

SOIC8

3

1

J5

CON0132X2

IN2R2

IN2R1

750KR90

1206

1206

C42120PF

5.76KR83

12065.76KR82

1206

120PFC44

1206

5.76KR88

12065.76KR89

1206CAP00210UFCT9

1206100PFC47

1206600FER2

ADC2_RIGHT

IN1R-

237R95

1206

120PFC59

1206

R925.76K1206

R1005.76K1206

10UFCT11

CAP002

ADC1_RIGHT

FER46001206

100PFC56

1206

750KR94

1206

R1045.76K1206

R1035.76K1206

1206

C55120PF

237R93

1206

IN1R+

ADC1_LEFT2

3

J5

CON0132X2

IN1L+

IN1L-

7

5

6 U19

AD8606ARSOIC8

1

3

2 U19

AD8606ARSOIC8

FER36001206

IN2L1

IN2L2

ADC2_LEFT5

6

J5

CON0132X2

6

4

J5

CON0132X2

AD1836_VREF

ADSP-BF533 EZ-KIT LITE - AUDIO IN

R1055.76K1206

CT1210UFCAP002

R1025.76K1206

1206120PFC58

R1015.76K1206

C57120PF1206

R992371206

R985.76K1206

C54100PF1206

R972371206

R96750K1206

12065.76KR91 R87

5.76K1206

R86750K1206

FER16001206

C46100PF1206

C45120PF1206

R855.76K1206

R845.76K1206

1206120PFC43

CT1010UFCAP002

AD1836_VREF

AD1836_VREFAD1836_VREF

AD1836_VREF

AD1836_VREF

AD1836_VREF

AD1836_VREF

AGND2

AGND2

AGND2AGND2

AGND2

A3V

A3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



12

45

6

ON

3

A3V

SOT23DAD1580

AGND2

AGND2

P15

P14

P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

CLOCK

RESET

ALSB

SDATA

SCLOCK

SCRESET/RTC

TTX

TTXREQ

DAC_A

DAC_B

DAC_C

DAC_D

COMP

VREF

RSET

HSYNC

FIELD/VSYNC

BLANK

VAA1

VAA2

VAA3

VAA4

VAA5

GND1

GND2

GND3

GND4

GND5

0


0


0

1

1 X

PPCLK

PPI_27MHZ_CLK (DEFAULT)

ADV7183_CLKOUT

EXPANSION_CLK CVSB

Component Video

S Video

Composite Video

Differential Component Video

DAC D

CVSB

GRB

C Y

U V Y

DAC B DAC C

DAC B

DAC C

DAC D

VIDEO ENCODER

1212-21-2004_15:12 7

PF1_SDATAPF1

PF0_SCLOCKPF0

R2260.00805

12060.00R182

PF0_SCLOCK

PF1_SDATA

3V_B

TP4

14

13

12

9

8

7

6

5

4

3

2

42

41

40

39

38

44

22

18

24

23

35

37

36

32

31

26

27

25

33

34

15

16

17

11

1

20

30

28

21

29

43

19

10

U27

TQFP44ADV7171KSU

PPI_CLK

PPI_27MHZ_CLK

ADV7183_CLKOUT

8050.00R132

2.2UH805

L2

8

9

J8

CON0243X2

3

2

J8

CON0243X2

5

6

J8

CON0243X2

0.1UF805

C72

ADV7171_RESET

1501206

R122

1

2

D1

805330PFC74

4

6

3

1

U26

SOT23-6ADG752BRT

1

2

5

3

4

AD8061ART

U23

SOT23-5

2.2UH805

L3

2.2UH805

L1

8050.68UHL8

0.68UH805

L9

0.68UH805

L6

8050.68UHL7

8050.68UHL5

0.68UH805

L4

3V_B

4

3

5

2

1

AD8061ART

U22

SOT23-5

1

2

3

4

5

6 7

8

9

10

11

12

SWT017DIP6

SW2

ADV7171_VSYNC

ADV7171_HSYNC

4

3

5

2

1

AD8061ART

U24

SOT23-5

10K805

R128

ADV7171_27MHZ_CLK

VIDEO_DAC_C

VIDEO_DAC_B

VIDEO_DAC_D

ADSP-BF533 EZ-KIT LITE - VIDEO OUT

330PF805

C73

12061KR131

100K1206

R130

12061.2KR129

8050.1UFC71

120675R127

12061KR126

12061KR125

805330PFC70

751206

R124

120675R123

330PF805

C69

805330PFC67

751206

R121

120675R120

330PF805

C68

1K1206

R119

1K1206

R118

751206

R117

120675R116

12061KR115

751206

R114

120675R113

1206100KR112

PF[15:12]PF12

PF13

PF14

PF15

PP[3:0]PP3

PP2

PP1

PP0

1

3

6

4

U25

SOT23-6ADG752BRT


EXPANSION_PPI_CLK


VIDEO_DAC_D

VIDEO_DAC_B

VIDEO_DAC_CVIDEO_AVIN5

VIDEO_AVIN4

VIDEO_AVIN1

3V_B

8050.00R227

AGND2

AGND2

A5V

3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



3.3V

3.3V

A3V

1.8V

A1.8V

12

45

6

ON

3

AGND1

AGND2

AGND3

AGND4

AGND5

AIN1

AIN10

AIN11

AIN12

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

ALSB

AVDD

CAPC1

CAPC2

CAPY1

CAPY2

CML

DGND1

DGND2

DGND3

DGND4

DGND5

DVDD1

DVDD2

DVDD3

DVDDIO1

DVDDIO2

ELPF

FIELD

HS

LLC1

LLC2

NC[AEF]

NC[AFF]

NC[AGND6]

NC[CLKIN]

NC[GPO0]

NC[GPO1]

NC[GPO2]

NC[GPO3]

NC[ISO]

NC[DV]

NC[HREF]

NC[LLCREF]

NC[RD]

NC[VREF]

P0

P1

P10

P11

P12

P13

P14

P15

P2

P3

P4

P5

P6

P7

P8

P9

PVDD

REFOUT

SCLK

SDA

SFL[HFF]

VS

XTAL

XTAL1

OE

PWRDN

RESET

AGND2

CVBSCVBSComposite Video

AVIN1 AVIN4 AVIN5

Y U V

CYS Video

Differential Component Video

AVIN5

AVIN4

AVIN1

VIDEO DECODER

CVBS

(RED) IN

DA

C_B

DA

C_C

DA

C_D

AV

IN4

AV

IN1

AV

IN5

(WHITE) OUT

1212-21-2004_15:12 8

R232

80510K

10K805

R145

1

24

SN74LVC1G32SOT23-5

U21

39

40

47

53

56

42

57

59

61

44

46

58

60

62

41

43

45

66

50

54

55

48

49

52

3

9

14

31

71

30

10

72

4

15

37

80

2

27

26

13

11

63

16

78

35

34

18

17

70

65

77

69

25

33

32

6

5

76

75

74

73

24

23

22

21

20

19

8

7

38

51

68

67

12

1

29

28

79

36

64

U28

LQFP80ADV7183AKST

DNP

6001206

FER10

6001206

FER8

DVDD_ADV7183

1206600FER13

1206600

DNPFER11

1206600FER12

PVDD_ADV7183

8050.01UFC82

80582NFC83

1.5K805

R140

PVDD_ADV7183

1206600

DNPFER9

R183

80533

33805

R144

8050.01UFC87

0.1UF805

C86

8050.1UFC84

1

2

3

4

5

67

8

9

10

11

12

DIP6SWT017

SW3

PF0_SCLOCK

ADV7183_27MHZ_CLK

ADV7183_RESET

10UFB

CT15

B10UFCT16

B10UFCT14

1

3

J8

CON0243X2

6

4

J8

CON0243X2

7

9

J8

CON0243X2

0.01UF805

C85

ADV7183_VS

ADV7183_FIELD

ADV7183_HS

PF1_SDATA

VIDEO_AVIN5

VIDEO_AVIN4

8050.00R141

80510KR143

10K805

R142

0.1UF805

C880.00805

R136

VIDEO_AVIN1

ADSP-BF533 EZ-KIT LITE - VIDEO IN

8050.1UFC90

8050.1UFC89

80510KR139

10K805

R138

0.1UF805

C81120675R137

8050.00R135

751206

R134

120675R133

0.1UF805

C80

0.1UF805

C79

8050.1UFC78

0.1UF805

C77

8050.1UFC76

8050.1UFC75

PP2PP[3:0]

PP3

PP1

PP0

PF13PF[15:12]

PF12

PF14

PF15

ADV7183_VREF

ADV7183_HREFTP5

TP6

TP7

ADV7171_HSYNC

ADV7183_HS

ADV7183_VS

ADV7171_VSYNC

ADV7183_FIELD

PF2

PF3

TMR2

TMR1

ADV7183_CLKOUT

3.3V

3.3V

3.3V

3.3V

1A1

1A2

1A3

1A4

2A2

2A3

2A4

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2A1

2Y4

2Y3

OE1

OE2

3.3V

5V

3.3V 3.3V

3.3V

3.3V

3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



PFI

RESETMR

PFO

RESET

C1+

C1-

C2+

C2-

R1INR1OUT

R2INR2OUT

T1OUT

T2IN T2OUT

V-

V+

T1IN

12

45

6

ON

3

3.3V

USB RESET

POWER

PF8

PF9

PF10

PF11

RESET

UART

RESET

Required when AD1836 is in I2S mode

FunctionConnects the push buttons to the Programmable Flags of the DSPUseful if using the PFs for another purpose.

Position

1-4

5,6Connects SPORT0 frame sync and clock together external to the DSP

SW8 PB Enable Switch

1212-21-2004_15:12 9

2

1P5

IDC2X12X1

R1110.00805

DNP

0.00805

R169

R110

8050.00

DNP

3

4

5

1

6

2

7

8

9

P2

DB9M9PIN

4

56

SOIC1474LVC00AD

U9

SWT013SPST-MOMENTARY

SW4

SPST-MOMENTARYSWT013SW5


SW6

SPST-MOMENTARYSWT013SW7

100805

R152

12060.00R158

5 6

SOIC1474LVC14A

U10

1

2

3

4

5

6 7

8

9

10

11

12

DIP6SWT017

SW9

805100R154

0.001206

R148

89

SOIC1474LVC14A

U10

TFS0 RFS0

TSCLK0RSCLK0

LED5

LED6LED[6:1]

LED1

LED4

LED2

LED3

AMBER-SMTLED001

LED4

LED001AMBER-SMTLED5

AMBER-SMTLED001

LED6AMBER-SMTLED001

LED7AMBER-SMTLED001

LED8

LED001AMBER-SMTLED9

RESET

USB_RESET

PF7

PF6

603600FER16

600603

FER14

600603

FER17

603600FER15

1

3

4

5

1312

89

14

10 7

6

2

11

ADM3202ARN

U30

SOIC16

1206270R160

8050.1UFC92

4

81

5

7

SOIC8ADM708SAR

U29


SW8

9

108

SOIC1474LVC00AD

U9

ADSP-BF533 EZ-KIT IO/RESET/UART

0.1UF805

C94

0.1UF805

C91

8050.1UFC93

TX

RX

LED001RED-SMTLED2

1206270R164

13 12

74LVC14ASOIC14

U10

10K805

R171

1113

12

74LVC00ADSOIC14

U9

80510KR170

10K805

R153

1206680R163

GREEN-SMTLED001

LED1

2701206

R146

80510KR166

RED-SMTLED001

LED3

2701206

R165

2

4

6

8

13

15

17

18

16

14

12

9

7

11

3

5

1

19

SSOP20IDT74FCT3244APY

U31

1206270R168

12060.00R167

2701206

R1622701206

R161

10K805

R159

11 10

74LVC14ASOIC14

U10

0.001206

R157

80510KR156

100805

R155

43

74LVC14ASOIC14

U10

A1UFCT20

1UFA

CT19

10K805

R151

80510KR150

805100R149

1UFA

CT18

A1UFCT17

1206270R147

USB_CONFIGURED

80510KR172

PF10

PF11

PF8

PF9

SOFT_RESET

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



5V

3.3V

5V 3.3V3.3V

SPORT0

EXPANSION INTERFACE (TYPE B)

All USB interface circuitry is considered proprietary and hasbeen omitted from this schematic.

When designing your JTAG interface please refer to theEngineer to Engineer Note EE-68 which can be found athttp://www.analog.com

DSP JTAG HEADER

1212-21-2004_15:11 10

1

3

5

7

9

11

13

2

4

6

8

10

12

14

P4

IDC7X27X2

CLK_OUT_EXP2

CLK_OUT_EXP1

A1

A2

A18

A16

A14

A12

A10

A8

A6

A4

A19

A17

A15

A13

A11

A9

A7

A5

A3

A[1:19]

87

85

83

81

77

75

73

69

67

65

63

61

59

57

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

5

50

6

78

9

49

55

51

53

52

54

56

58

60

62

66

70

68

72

74

76

78

80

82

84

86

88

90 89

64

71

79

J1

45X2CON019

PP1

PP3

PF10

PF12

PF14

PF2

PF6

PF8

PF13

PF11

PF9

PF7

PF5

PF3

PF15

PF1PF0

PF4

PF[0:15]

BGH

BG

BR

DT0SEC

RSCLK0

DR0PRI

DR0SEC

0.001206

R175

EMULATOR_TCK

EMULATOR_TMS

EXT_DSP_CLK

EMULATOR_TDO

EMULATOR_TDI

EMULATOR_TRST

PB6_A

PA6_APA7_A

PB7_A

ADV7183_VREF

ADV7183_FIELD ADV7183_VS

ADV7183_HS

NMI

EMULATOR_EMU

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

10X2CON014

P3

87

85

83

81

77

75

73

69

67

65

63

61

59

57

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

5

50

6

78

9

49

55

51

53

52

54

56

58

60

62

66

70

68

72

74

76

78

80

82

84

86

88

90 89

64

71

79

CON01945X2

J3

10K805

R173

TX RX

TSCLK0

TSCLK0

TSCLK1 DSCLK1

RSCLK0

SCK

EXPANSION_PPI_CLK

PP2

PP0

~ABE1/SDQM1

SRAS

SWE

D[0:15]

D10

D14

D12

D4

D6

D8

D0

D2D3

D5

D7

D9

D11

D13

D15

D1

RESET

ADSP-BF533 EZ-KIT LITE - CONNECTOR

RFS0

DT0PRI

TFS0

EMULATOR_SELECT

12060.00R174

RESET

MISO

DT1SEC

DT1PRI

TFS1 RFS1

DR1PRI

DR1SEC

ARE

SMS

SCKE

TMR2

TMR0

AMS0

AMS1

AMS2

AMS3

ARDY

~ABE1/SDQM1

AWE

SA10 SCAS

~ABE0/SDQM0

~ABE0/SDQM0

AOE

DR0SEC

DR0PRI

RFS0TFS0

DT0PRI

DT0SEC

TMR1

MOSI

87

85

83

81

77

75

73

69

67

65

63

61

59

57

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

5

50

6

78

9

49

55

51

53

52

54

56

58

60

62

66

70

68

72

74

76

78

80

82

84

86

88

90 89

64

71

79

J2

45X2CON019

ADV7183_HREF

PA6_B

PA4_B

PA2_B

PA0_B

PA5_B

PA7_B

PA3_B

PA1_B

SHGND

SHGND

1.8V

5V A5V

A1.8V3.3V

SHGND

GNDINPUT OUTPUT

3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



SHGND

3.3VGND

INPUT OUTPUT

GNDINPUT OUTPUT

GNDINPUT OUTPUT

CHOKE_COIL

OUT1

OUT2

OUT3

IN1

IN2

FBSD GND

OUT1

OUT2

OUT3

IN1

IN2

FBSD GND

A3V

JUMPERSHORTING

Position

1 and 2

Function

be populated and the DSP_VDD_INT will be hard-wired with R222to use the processor internal regulator.

DSP_VDD_INT = 1.4V Fixed

DSP_VDD_INT = DSP Internal Voltage Regulation

2 and 3

SW10: Core Voltage Source SelectDEFAULT: Not Populated

Note: For boards without a 750MHz processor this jumper will not

1212-21-2004_15:11 11

4

3

2

1

8

7

6

5

U32

SO-8FDS9431A

0.00805

R222

SJ1

DEFAULT=2 & 3

DNP

0.00805

R211

1V4

DSP_VDD_INT

64.9KR184

805

340KR185

805

8051UFC61

CT28

D68UF

IND00110UHL12

TP12

TP15

3.32KR223

805

VROUT

UNREG_IN

8051UFC103

10K805

R192

10K805

R214

8051UFC102

1206FER20

147KR191

1206

76.8KR190

1206

1

2

3

7

8

56

4MSOP8ADP3336ARM

VR2

1

2

3

7

8

56

4MSOP8ADP3336ARM

VR6

DSP_VDD_INT

8050.00R186

8050.00R187

DSP_VDD_EXT

CT13

C10UF

CT24

C10UF

2ADO-214AA

D4

UNREG_IN

4

1

3

2

FER23

FUS0012.5AF1

8050.00R210

8051UFC60

8051UFC104

C105

8050.1UF

0.00805

R188

8050.00R189

12060.00R177

TP11

3

1

2

ADP3339AKC-5SOT-223

VR5

2

1

3

VR3

SOT-223ADP3339AKC-33

3

1 1A

ZHCS1000SOT23D

D5

DSP_VDD_EXT

3

1

2

ADP3339AKC-33SOT-223

VR4

8050.1UFC98

10UFC

CT230.1UF805

C175

C10UFCT21

C1000.1UF805

0.001206

R178

10UFC

CT26

UNREG_IN

TP10

12061000PFC96

DO-214AA2AD3

12061000PFC97

1

3

2

CON0052.5MM_JACK

7.5V_POWER

J9

ADSP-BF533 EZ-KIT LITE - POWER

1206600FER18

3V_B

2

1

3

ADP3338AKC-33SOT-223

VR1

TP8

1206600FER19

UNREG_IN

6001206

FER21

MH2 MH1 MH5MH4MH3

DO-214AA2AD2

1206100KR176

C10UFCT22

1206600FER22

TP9

8050.1UFC143

TP14 TP13

CT2510UFC

8050.1UFC101

C10UFCT27

VDDRTC

3

1

2

DNP3X1IDC3X1

JP3

3.3V

AGND2

3.3V3.3V

3.3V3.3V3.3V3.3V3.3V3.3V

3.3V 3.3V

A0167-2001 1.6C

4

3

2

1

A B C D

Nashua, NH 03063

A B C D

4

3

2

1

PH: 1-800-ANALOGD

C

Approvals Date

Drawn

Checked

Engineering Date

Size

Title

Board No. Rev

Sheet of



A3V A3V A3VA5V A5VA5V

AGND

AGND AGND AGND

A5V

AGND

A5V

AGND

AGND

A5V

AGND

A5V A5V

5V

AGND

A5V

3.3V

3.3V3.3V

3.3V

AGND2AGND2

3.3V

RES IN PLACE OF C188

AD8606 AD8606AD8606AD8606 AD8606 AD8061AD8061U23 U24U22

AD8061U15 U17U16 U20U18

U4IDT74FCT3807

ADG752 ADG752U26U25

U30ADM3202

U29ADM708SARADV7171

U27ADV7183

U28IDT74FCT3244APY

U31

AD1836U14

PSD4265 AU5

PSD4265 BU6

SN74LVC1G125U7

SDRAMU8

74LVC00ADU9

74LVC14AU10 AD8606

U12AD8606

U13

ADSP-21533

AD8606U19

IDT2305U46

U21SN74AHC1G08

U1

121212-21-2004_15:11

8050.01UFC188

8050.01UFC190

DSP_VDD_EXT

8050.01UFC146

0.01UF805

C1470.1UF805

C145

8050.1UFC148

0.1UF805

C1440.1UF805

C95

8050.1UFC119

8050.1UFC132

0.01UF805

C128 C204

8050.01UF

8050.1UFC156

0.1UF805

C157

8050.1UFC158

0.01UF805

C1520.01UF805

C1630.01UF805

C161

8050.01UFC171

8050.01UFC172

8050.01UFC113

8050.1UFC109C112

8050.01UF0.1UF

805

C1110.01UF805

C108

8050.1UFC110

0.22UF805

C1420.22UF805

C1400.22UF805

C1410.22UF805

C1390.22UF805

C1370.22UF805

C1290.1UF805

C178

8050.1UFC176

8050.1UFC99

8050.1UFC177

0.01UF805

C165

0.22UF805

C138

8050.22UFC130

0.01UF805

C151C208

8050.01UF

C201

8050.01UF

8050.01UFC167

8050.01UFC168

8050.01UFC166

8050.01UFC173

0.01UF805

C1740.01UF805

C1230.01UF805

C1690.01UF805

C124

8050.01UFC127

8050.01UFC126

0.01UF805

C136

8050.01UFC149

8050.01UFC150C154

8050.01UF0.01UF

805

C155

8050.01UFC153

0.01UF805

C159

0.1UF805

C197

8050.1UFC192

0.1UF805

C195

8050.1UFC193

8050.01UFC194

0.01UF805

C196

8050.1UFC191

0.1UF805

C186

8050.1UFC189

0.1UF805

C18710UF1210

C19810UF1210

C200

121010UF

C1990.01UF805

C181

8050.01UFC183

8050.1UFC184

0.1UF805

C182

8050.1UFC185

0.1UF805

C180

8050.00

DNPR194

8050.1UFC179

ADSP-BF533 EZ-KIT LITE - BYPASS CAPS

BBBYPDSP_VDD_INT

DVDD_ADV7183

3V_B

8050.1UFC209

C2100.1UF805

I INDEX

A C
AD1836 codec, 1-14, 2-4, 2-11ADSP-BF533 processor
address space, 1-9audio interface, see SPORT0Clock In (CLK IN), 2-7Clock Out (CLK OUT), 2-3core voltage, 2-2External Bus Interface Unit (EBIU), 2-3internal SRAM, 1-6IO voltage, 2-2parallel peripheral interface (PPI), 2-5peripheral ports, -xiv

ADV7171 video encoder, 1-15, 2-6, 2-7, 2-10ADV7183 video decoder, 1-15, 2-6, 2-7, 2-10~AMS0-2, memory select pins, 1-6, 1-9, 2-3ASYNC, memory banks 0-3, 1-6audio

applications, -xivcodec, 1-13connectors (J4, J5), 2-17interface, see SPORT0see also AD1836

Bbackground telemetry channel (BTC), 1-16bill of materials, A-1boot

load, 1-18mode select (JP1-2), 2-10

breakpoints, restrictions, 1-20

clock frequency, 1-7codecs, 2-3configuration registers (IO), 1-9connectors, 1-3, 2-16

extender connectors (P3-1), 2-3FlashLINK (P1), 2-18J1 (expansion interface), 2-8J2 (expansion interface), 2-8J3 (expansion interface), 2-8J4 (audio), 2-17J5 (audio), 2-17J8 (video), 2-17J9 (power), 2-17P4 (JTAG), 2-9, 2-20P9 (SPORT0), 2-19RS232 (P2), 2-19see also expansion interface

contents, EZ-KIT Lite package, 1-2core frequency, 1-8customer support, -xvi

DDIP switches, 2-9

see also SWdual bank flash memory, 1-6

Eevaluation license restrictions, 1-5example programs, 1-16

ADSP-BF533 EZ-KIT Lite Evaluation System Manual I-1

INDEX

expansionboard, 1-11interface, 2-4, 2-8, 2-16

extender connectors (P3-1), 2-3external

bus interface unit (EBIU), 2-3flash memory, see flash memory

external memory, 2-9bank 0 (primary A), 1-6bank 0 (SDRAM), 1-6

EZ-KIT Litearchitecture, 2-2features, -xiimemory map, 1-6

Ffeatures, EZ-KIT Lite, -xiiflag pins, see programmable flags (PFs)flash A, 1-10

configuration registers, 1-11port A controls, 1-11port B controls, 1-12primary, 1-9registers, 1-10secondary, 1-9SRAM, 1-10

flash B, 1-10configuration registers, 1-11primary, 1-9registers, 1-10secondary, 1-10SRAM, 1-10

flash memory, -xiv, 1-8, 2-3, 2-10configuring, 1-12general-purpose IO pins (U5), 2-15map, 1-9modifying, PSDsoft Express, 1-12primary, 1-6, 2-3programming, FlashLINK, 1-12reserved, 1-10secondary, 2-3

flash ports, PB0-5, 2-15frequency, 1-7

Ggeneral-purpose IO, 1-13, 1-14graphical user interface (GUI), 1-16

Hhard reset, 1-18Help, online, -xxiHSYNC signal, 2-6, 2-7, 2-11

Iinterfaces

SDRAM, 1-7see graphical user interface (GUI)

internal memory, 1-7, 2-9core MMRs, 1-7data bank A SRAM, 1-7data bank B SRAM, 1-7instruction SRAM, 1-7instruction SRAM/CACHE, 1-7reserved, 1-7scratch pad SRAM, 1-7system MMRs, 1-7

IOconfiguration registers, 1-9signals, 1-10voltage, 2-2

I-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual

INDEX

IO port registers, 1-10Data In, 1-10Data Out, 1-10Direction, 1-10

JJTAG

connector (P4), 2-20emulation port, 2-9programming cable, 1-13

jumpers, 2-9JP1-2 (boot mode select), 2-10

jumper settings, 1-3

LLEDs, 1-3, 1-13, 2-13

LED1, 2-14LED11, 1-4, 2-15LED2-3, 2-14LED4-9, 1-12, 2-15

Mmemory

flash configuration, 1-9SDRAM configuration, 1-7select pins, see ~AMS0-2, ~SMS0

memory map, 1-6

Nnotation conventions, -xxiii

PP3, SPORT connector, 2-3package contents, 1-2Parallel Peripheral Interface (PPI), -xiv, 1-15,

2-5PC parallel port, 1-13

PFs, see programmable flagspower

connector (J9), 2-17specifications, 2-18supply, 2-18

PPI interface, 1-15, 2-7primary flash memory, 1-9primary processor pins

PF3, 2-6PPI0-7, 2-6PPI_CLK, 2-6TMR1-2, 2-6

programmable flags (PFs), 2-4, 2-5PF0, 1-15, 2-4PF1, 1-15PF10-11, 2-5, 2-12, 2-14PF12-15, 2-5, 2-6PF2, 1-15, 2-4, 2-10PF3, 2-4PF4, 1-14, 2-4PF5-7, 2-4PF8-11, 1-13, 2-5, 2-12, 2-14PF9, 2-5, 2-12, 2-14push buttons, see also push buttons

push buttons, 1-13, 2-13connecting to PF pins, 2-13SW4-7 (general input), 2-5, 2-12, 2-14SW8 (reset), 2-14SW9 (enable), 1-14, 2-11, 2-13

Rregistering, this product, 1-3reset

board, 1-18options, 1-19processor, 2-14push button (SW8), 2-14service routines, 1-17

RFS0, signal, 2-12


INDEX

RSCLK0register, 1-14signals, 2-12

SSCLK, 1-7SDRAM, -xiv, 1-6, 1-7, 1-8, 2-3secondary flash memory, 1-9serial

clock (SCL), 1-7, 1-15data (SDAT), 1-15

Serial Peripheral Interconnect (SPI), 2-4setting

EZ-KIT Lite hardware, 1-3target options, 1-18

~SMS0, memory select pin, 1-6, 2-3software breakpoints, 1-20SPI port, 1-14SPORT0, -xiv, 1-13, 2-3, 2-11, 2-19SRAM, 1-6, 1-9, 2-3starting EZ-KIT Lite, 1-4SW1-2, test DIP switches, 2-10SW3, DIP switch, 1-15, 2-7, 2-9, 2-10system

architecture, EZ-KIT Lite, 2-2clock, 1-7

Ttarget options

dialog box, 1-18miscellaneous, 1-19on emulator exit, 1-19reset, 1-19

test DIP switches (SW1-2), 2-10TFS0 signal, 2-12TMR1-2, primary processor pins, 2-6

tracebuffer, 1-17destination, 1-18instruction addresses, 1-18number, 1-18source, 1-18

Trace window, 1-17, 1-18TSCLK0

register, 1-14signal, 2-12

Two-Wire Interface (TWI) mode, 1-14

UUART port, 2-8Universal Asynchronous Receiver Transmitter

(UART), -xiii, -xiv, 2-8USB

cable, 1-3connector (P7), 2-18, 2-19interface, 2-9interface chip (U34), 2-14monitor LED (LED11), 2-15

user LEDs (LED9-4), 2-15see also LEDs

Vvideo, 1-15

configuration switch (SW3), 2-10connector (J8), 2-17decoder, -xivencoder, -xivinput mode, 2-7interface, 1-15output mode, 2-7

VisualDSP++documentation, -xxiionline Help, -xxi

VSYNC signal, 2-6, 2-7, 2-11


INDEX

XXML register reset values, 1-7, 1-20


INDEX
