a novel converter topology for high step-down conversion ...a novel converter topology for high...

www.ijatir.org

ISSN 2348–2370

Vol.07,Issue.19,

December-2015,

Pages:3764-3774

Copyright @ 2015 IJATIR. All rights reserved.

A Novel Converter Topology for High Step-Down Conversion Ratio DC-DC

Converter with Low Voltage Switch Stress K. S. SAMBAIAH

1, N. VENUGOPAL

2

1PG Scholar, Dept of EEE, Kuppam Engineering College, Kuppam, Chittoor, AP, India, E-mail: [email protected].

2Professor & HOD, Dept of EEE, Kuppam Engineering College, Kuppam, Chittoor, AP, India, E-mail: [email protected].

Abstract: In this paper, a novel converter topology for

interleaved high step-down conversion ratio dc–dc converter

with low switch voltage stress is proposed. In the proposed

converter, two input capacitors are series-charged by the

input voltage source and parallel discharged by a new two-

phase interleaved buck converter topology without adopting

an extreme short duty cycle for delivering a much higher

step-down conversion ratio. Based on the capacitive voltage

division, the main objectives of the new voltage-divider

circuit in the converter are for both storing energy in the

blocking capacitors for increasing the step-down conversion

ratio and reducing voltage stresses of active switches. As a

result, the proposed converter topology procures the low

switch voltage stress ascribe. This will allow one to choose

lower voltage rating MOSFETs to reduce both switching

and conduction losses. The overall efficiency is

subsequently enriched. The converter features automatic

uniform current sharing characteristic of the interleaved

phases without adding extra circuitry or complex control

methods due to the charge balance of the blocking capacitor.

The operation principles and relevant evaluation of the

propositioned converter are offered in this project. Finally, a

400-V input voltage, 25-V output voltage, and 400-W

output power prototype circuit and simulated using

MATLAB to verify the performance.

Keywords: Converter Topology, Interleaved Control, High

Step-Down Conversion Ratio, Low Switch Voltage Stress.

I. INTRODUCTION

Newly, high enactment dc–dc converters have been

called for the increasing high step-down ratios with high

output current rating applications, such as battery chargers,

VRMs of CPU boards, and distributed power systems [1]–

[4]. An interleaved buck converter (IBC) [5]–[8] has

received a lot of attention due to its low control complexity

and simple structure for non-isolation applications with low

output current ripple requirement. Though, in the

conventional IBC shown in Fig. 1(a), here active switch

devices suffer from the input voltage which requires high

voltage devices rated above the input voltage should be

applied. High-voltage-rated devices are in general with poor

characteristics such as large voltage drop, large ON-

resistance, severe reverse recovery, and high cost etc. These

limit the switching frequency of the converter and effect the

power density perfection. For high-input and low-output

voltage regulation applications, pursuing advanced power

density and enhanced dynamics, it is required to operate at

higher switching frequencies [9] that will increase together

switching and conduction losses. Consequently, the efficacy

is further deteriorated. Also, it experiences an exceptionally

short duty cycle in the case of high input and low-output

voltage applications. To overcome the drawbacks of the

conventional IBC, many step-down converters have been

proposed [10]–[20]. A quadratic buck converter [10] is

synthesized by cascading two dc–dc buck converters, in

which the voltage conversion ratios of two cascaded

converters with fewer switches. It can operate without an

extremely short duty ratio with wider ranges of step-down

conversion ratio than those of conventional single-switch

converters.

Fig.1. Configuration of (a) conventional IBC and (b)

two-phase extended duty ratio IBC.

mailto:[email protected]

K. S. SAMBAIAH, N. VENUGOPAL

International Journal of Advanced Technology and Innovative Research

Volume.07, IssueNo.19, December-2015, Pages: 3764-3774

However, operating two cascaded converters processes

energy so that the efficacy is worse. To reduce the switch

voltage stress to half of the input voltage a three-level buck

converter is proposed in [11] and [12]. By using the

aforementioned converter, low-voltage MOSFETs have

better performance and higher efficacy when compared with

the conventional buck converter. However, so many

components are essential for the use of IBC. In [13], an IBC

with a single-capacitor turnoff snubber is presented. Its

advantages are that the switching loss related with turn-off

transition can be reduced, and a single coupled inductor

implements the converter as two output inductors. However,

it operates at discontinuous conduction mode (DCM), and

all elements suffer from high-current stress, resulting in high

conduction and core losses. In addition, the voltages across

all semiconductor devices are still the input voltage. To

reduce switching losses, an active-clamp IBC is proposed in

[14]. In the converter, all active switches are turned on with

zero-voltage switching (ZVS). Moreover, a high step-down

conversion ratio can be obtained, and the voltage stress

across the freewheeling diodes can be reduced. However, it

requires additional passive elements and active switches,

which increases the cost at low or middle levels of power

applications. Recently, a study on step-down converter with

efficient ZVS operation with load variation has been

presented in [20]; the authors used an auxiliary switch, a

diode, and a coupled winding to the buck inductor for the

ZVS operation. Based on their analysis, the converter

conduction loss will be minimized efficiently. An IBC with

two winding coupled inductors is introduced in [15] and

[16]. It can be operated at continuous conduction mode

(CCM). The voltages across all semiconductor devices can

be reduced by adjusting the turn ratio of the coupled

inductors, and the switching losses can be reduced.

Additionally, a high step-down conversion ratio can also

be obtained. However, the leakage energy needs to recycle.

To deal with a small duty cycle of the IBC in high-input and

low-output voltage regulation applications, anew extended

duty ratio multiphase (Extended-D) topology has been

proposed. The two-phase and four-phase versions of the

topology have been discussed in [17] and [18]. The two-

phase extended duty ratio IBC [17] is shown in Fig. 1(b).

Extended duty ratio (ExtD) mechanisms are very efficient

input voltage dividers which reduce the switching voltage

and associated losses. However, the voltage stress of the

input switch devices remains rather high. In this paper, a

novel converter topology for interleaved high step-down

conversion ratio dc–dc converter with low switch voltage

stress is proposed. In the proposed converter, two input

capacitors are series-charged by the input voltage source

and parallel discharged by a new two-phase interleaved

buck converter topology without adopting an extreme short

duty cycle for delivering a much higher step-down

conversion ratio. Based on the capacitive voltage division,

the main objectives of the new voltage-divider circuit in the

converter are for both storing energy in the blocking

capacitors for increasing the step-down conversion ratio and

reducing voltage stresses of active switches. As a result, the

proposed converter topology procures the low switch

voltage stress ascribe. This will allow one to choose lower

voltage rating MOSFETs to reduce both switching and

conduction losses. The overall efficiency is subsequently

enriched. The converter features automatic uniform current

sharing characteristic of the interleaved phases without

adding extra circuitry or complex control methods due to the

charge balance of the blocking capacitor.

Fig.2. Configuration of proposed converter.

The remaining contents of this paper may be outlined as

follows. First, the novel circuit topology and operation

principle are given in Section II. Then, the corresponding

steady state analysis is made in Section III to provide some

basic converter characteristics. A prototype is then

constructed, and some simulation and experimental results

are then presented in Section IV for demonstrating the

merits and validity of the proposed converter. Finally, the

conclusion is presented in the last section.

II. OPERATING PRINCIPLE

The proposed a novel converter topology IBC is shown in

Fig2.From Fig. 2, one can see that the proposed converter

consists of two inductors, four active power switches, two

diodes, and four capacitors. The main objectives of the four

capacitors are twofold. First, they are used to store energy as

usual. Second, based on the capacitive voltage division

principle, they are used to reduce the voltage stress of active

switches as well as to increase the step-down conversion

ratio as will be obvious from later explanation. Basically,

the operating principle of the proposed converter can be

classified into four operation modes. The interleaved gating

signals with an 180◦ phase shift as well as some key

operating waveforms are shown in Fig. 3. As the main

objective is to obtain a high step-down conversion ratio and

as such characteristic can only be achieved when the duty

cycle is less than 0.5 and in CCM, hence the steady-state

analysis is made only for this case. However, in DCM, as

there is not enough energy transfer from the blocking

capacitors to the inductors, output capacitors, and load side,

and as, consequently, it is not possible to get the charge

balance of the blocking capacitor, then the nice automatic

A Novel Converter Topology for High Step-Down Conversion Ratio DC-DC Converter with Low Voltage Switch Stress



uniform current sharing property will be lost, and additional

current-sharing control between phases should be included

under this condition.

Fig.3. Key operating waveforms of proposed converter

at CCM.

Mode 1 [t0 < t ≤ t1]: During this mode, S1a, S1b, and D1 are

turned on, while S2a, S2b, and D2 are turned off. The

corresponding equivalent circuit is shown in Fig. 4(a). From

Fig. 4(a), one can see that, during this mode, current

iL1freewheels through D1, and L1 is releasing energy to the

output load. However, current iL2 provides two separate

current paths through CA and CB. The first path starts from

C1, through S1a, CA, L2, CO and R, and D1 and then back to

C1 again. Hence, the stored energy of C1 is discharged to

CA, L2, and output load. The second path starts from CB,

through L2, CO and R, and S1b and then back to CB again.

In other words, the stored energy of CB is discharged to L2

and output load. Therefore, during this mode, iL2 is

increasing, and iL1 is decreasing, as can be seen from Fig.

3. Also, from Fig. 4(a), one can see that VC1 is equal to VCA

plus VCB due to conduction of S1a, S1b, and D1. Since VC1

= Vin/2 and VCA = VCB = VC1/2 = Vin/4, one can observe

from Fig. 4(a) that the voltage stress of D2 is equal to VCB =

Vin/4 and the voltage stresses of S2a and S2b are clamped to

VC2 = Vin/2 and VC1 = Vin/2, respectively. The

corresponding state equations are given as follows:

(1)

(2)

(3)

(4)

(5)

(6)

Mode 2 [t1 < t ≤ t2]: During this mode, S1a, S1b, S2a, and

S2b are turned off. The corresponding equivalent circuit is

shown in Fig. 4(b). From Fig. 4(b), one can see that both

iL1 and iL2 are freewheeling through D1 and D2,

respectively. Both VL1 and VL2 are equal to −VCO, and

hence, iL1 and iL2 decrease linearly. During this mode, the

voltage acrossS1a, namely, VS1a, is equal to the difference

of VC1 and VCA, and VS1b is clamped at VCB. Similarly, the

voltage across S2a, namely, VS2a, is equal to the difference

of VC2 and VCB, and VS2b is clamped at VCA. The

corresponding state equations are given as follows:

(7)

(8)

(9)

(10)

(11)

(12)

Mode 3 [t2 < t ≤ t3]: During this mode, S2a, S2b, and D2are

turned on, while S1a, S1b, and D1 are turned off. The

corresponding equivalent circuit is shown in Fig. 4(c). From

Fig. 4(c), one can see that, during this mode, current iL2 is

freewheeling through D2, and L2 is releasing energy to the

output load. However, current iL1 provides two separate




current paths through CA and CB. The first path starts from

C2, through L1, CO and R, D2, CB, and S2a and then back to

C2 again. Hence, the stored energy of C2 is discharged to

CB, L1, and output load. The second path starts from CA,

through S2b, L1, CO and R, and D2 and then back to CA

tored energy of CA is discharged to L1 and output load.

Therefore, during this mode, iL1 is increasing, and iL2 is

decreasing, as can be seen from Fig. 3. Also, from Fig. 4(c),

one can see that VC2 is equal to VCA plus VCB due to

conduction ofS2a and S2b. Since VC2 = Vin/2 and VCA = VCB

= VC2/2 =Vin/4, one can observe from Fig. 4(c) that the

voltage stress of D1 is equal to VCA = Vin/4 and the voltage

stresses of S1a and S1b are clamped to VC1 = Vin/2 and VCB

= Vin/4, respectively. The corresponding state equations are

given as follows:

Fig.4. Equivalent circuit of the proposed converter. (a)

Mode 1. (b) Modes 2 and 4. (c) Mode 3.

(13)

(14)

(15)

(16)

(17)

(18)

Mode 4 [t3 < t ≤ t4]: For this operation mode, as can be

observed from Fig. 3, S1a, S1b, S2a, and S2b are turned off.

The corresponding equivalent circuit turns out to be the

same as Fig. 4(b), and its operation is the same as that of

mode 2.From the aforementioned illustration of the

proposed converter, one can see that not only the control is

very simple but also the operations of two-phase are both

symmetric and rather easy to understand. Also, from the key

operating waveforms of the proposed converter shown in

Fig3 one can see clearly the low voltage stress characteristic

of four active switches and two diodes as well as the

uniform current sharing.

III. STEADY-STATE ANALYSIS

In order to simplify the circuit analysis of the proposed

converter, some assumptions are made as follows.

All components are ideal components.

The capacitors are sufficiently large such that the

voltages across them can be considered constant.

Also, assume that C1 = C2 and CA = CB.

The system is under steady state and is operating in

CCM with duty ratio being lower than 0.5 for high

step-down conversion ratio purposes.

A. Conversion Ratio

Referring to Fig. 4(a) and (c), from the volt–second

relationship of inductor L1 (or L2), one can obtain the

following relations:

(19)

(20)

Also, from the equivalent circuits in Fig. 4(a) and (c),

voltages VC1, VC2, VCA, and VCB can be derived as follows:

(21)

(22)




TABLE I: Comparison of the Steady-State

Characteristics

The output voltage can be obtained by substituting (22)

into (19) or (20) as follows:

(23)

Thus, the conversion ratio M of the proposed converter

can be obtained as follows:

(24)

B. Voltage Stresses on Semiconductor Components

To simplify the voltage stress analyses of the components

of the proposed converter, the voltage ripples on the

capacitors are ignored. From Fig. 4(a) and (c), one can see

that the voltage stresses on diodes D1 and D2 can be

obtained directly as shown in the following equation:

(25)

From (25), one can see that the voltage stress of the diodes

of the proposed converter is equal to one fourth of the input

voltage. Hence, the proposed converter enables one to adopt

lower voltage rating devices to further reduce conduction

losses. As can be observed from the equivalent circuits in

Fig. 4(a) and (c), the open circuit voltage stress of active

power switches S1a, S2a, S1b, and S2b can be obtained

directly as shown in

(26)

In fact, one can see from (26) that the maximum resulting

voltage stress of the active power switches is equal to

Vin/2.Hence, the proposed converter enables one to adopt

lower voltage rating active switches to further reduce both

switching and conduction losses.

C. Characteristic of Uniform Output Inductor Current

Sharing

By using the state space averaging technique, one can

repeat the previous process to get the averaged state

equations quite straight forward as follows:

(27)

(28)

(29)

(30)

(31)

(32)

(33)

(34)

Where

It follows from (29) to (32) that one can get the

corresponding dc solutions of the two-phase inductor

current as follows:

(35)

From (35), one can see that the proposed converter indeed

possesses the inherent automatic uniform current sharing

capability.

D. Performance Comparison

For demonstrating the performance of the proposed

converter, the proposed converter is compared with

conventional IBC and extended duty ratio IBC [17] as

shown in Table I. Table I summarize the conversion ratio

and normalized voltage stress of active as well as passive

switches for reference. As an illustration, Fig. 5 shows the

corresponding characteristic curve of the proposed

converter. For comparison, the voltage stress is normalized

by the input voltage Vin, the conversion ratio M, and the

normalized switch stresses, and the normalized output diode

stresses of the conventional IBC and the extended duty ratio

IBC [17] are also shown in the same figure to provide better

view. It is seen from Fig. 5(a) that the proposed converter

can achieve a higher step-down conversion ratio than that of

the other two IBC converters. Therefore, the proposed

converter is rather suitable for use in applications requiring

a high step-down conversion ratio. From Fig. 5(c), one can

see that the proposed converter can achieve the lowest

voltage stress for the active switches. Also, from Fig. 5(d), it

is seen that the proposed converter can achieve the lowest

voltage stress for the diodes. As a result, one can expect

that, with proper design, the proposed converter can adopt

switch components with lower voltage ratings to achieve

higher efficiency.

E. Loss Analysis

For loss analysis, it is assumed that the IBCs are operated

when the duty cycle is less than 0.5. The equations for loss




analysis can be obtained by referring to [17] and Appendix

A and can be summarized as in Table II.

Fig.5. Comparison of the steady-state characteristics of

three different converters. (a) Conversion ratio. (b)

Normalized voltage stress of active switch Sa.(c)

Normalized voltage stress of active switch Sb. (d)

Normalized voltage stress of diodes.

TABLE II: Loss Equation at Steady State

First of all, the specifications of the proposed converter are

the following: 1) input voltage of 400 VDC; 2) output

voltage of 25 VDC; 3) power rating of 400 W; and 4)

switching frequency of 40 kHz. According to the

specifications, proper components are chosen, and the

corresponding parameters are given in Appendix B.

Generally speaking, high-voltage-rated devices are

generally with poor characteristics such as high cost, large

ON-resistance, large voltage drop, severe reverse recovery,

etc. These limit the switching frequency of the converter

and impact the power density improvement. The situation

will be even worse for short duty cycle in the case of high-

input and low-output voltage applications. The loss analysis

of the conventional IBC [17] and the proposed converter is

shown in Fig. 6. From Fig. 6, one can see that, due to the

reducing voltage stress of diodes, the total loss of the

proposed converter is still reduced in spite of using more

active switches. It means that the proposed converter can

provide a much higher step-down conversion ratio without

adopting a short duty cycle as shown in Table I. Moreover,

the proposed converter topology possesses a low switch

voltage stress characteristic. This will allow one to choose

lower voltage rating MOSFETs to reduce both switching

and conduction losses, and the overall efficiency is

consequently enhanced.

Fig.6. Loss analysis results.




IV. SIMULATION AND EXPERIMENTAL RESULTS

To facilitate understanding the merits and to serve as a

verification of the feasibility of the proposed converter, a

prototype with 400-V input, 25-V output, and 400-W rating

is constructed, as shown in Fig. 2. The switching frequency

is chosen to be 40 kHz, both duty ratios of (S1a, S1b)

and(S2a, S2b) are equal to 0.25, and the corresponding

component parameters are listed in Table III for reference.

TABLE III: Component Parameters Of The Prototype

System

Due to the lows witch voltage stress of the proposed

converter, three power MOSFETs with a rating of 250 V

and a conductive resistance of 27 mΩ, namely,

IXFH100N25P, and one power MOSFET with a rating of

150 V and a conductive resistance of 13 mΩ, namely,

IXFH150N15P, are adopted. Similarly, two diodes with low

forward voltage drop, namely, DSSK60-02A, are chosen.

As in the aforementioned specifications, the voltage

conversion ratio is 1/16, as calculated by (24). Next,

considering the steady-state inductor currents in (35), the

rated output current is calculated to be 16 A. Moreover,

15% of the full-load inductor current, i.e., 2.4 A, can be

chosen as the peak-to-peak ripple current. Therefore, the

inductor operating in the CCM is

(36)

According to the magnetic powder core data sheet provided

by CSC, we choose a to roid powder core whose part

number is CM467060. Using magnetic design formulas

from the datasheet, the design ensures that the in inductor

operates in the CCM when the load is greater than 60 W. In

fact, a 250-μH inductor is chosen in the implementation.

The interleaved structure can effectively increase the

switching frequency and reduce the output current ripples as

well as the size of the energy storage inductors. Fig. 7

shows the two-phase inductor current waveforms of the

simulation and experimental results. Both simulated

inductor current ripples are about 2.3 A, while the

experimental ones are about 2.32 A. Since output current I

in is equal to IL1 plus IL2, it is obvious that, with two-phase

interleaving control, both output current ripples and

conduction losses can be reduced.

(a)

(b)

Fig.7. (a) Waveform of current ic0 (b) Waveforms of

inductor currents iL1 & iL2.

The simulation and experimental waveforms of the input

voltage and output voltage are shown in Fig. 8. The

measured input voltage is 400 V, and the output voltage is

25 V.

(a)

(b)

Fig.8. Simulation waveforms (a) input and (b)output

voltage.




(a)

(b)

Fig.9. Simulation results of (a) input capacitor and

(b)blockingcapacitor voltages.

Fig.10. Simulation results of voltage stressesVD1 and

VD2.

(a)

(b)

Fig.11(a) Simulation results of the voltage stresses of

Vs1a, and Vs1b. (b) Simulation results of the voltage

stresses of Vs2a, and Vs2b.

To check the validity of the capacitor voltage stress, the

waveforms of the input capacitors and blocking capacitors

are recorded as shown in Fig. 9. From Fig. 9, one can see

that, with the proposed converter, the voltage stresses of the

input capacitors and blocking capacitors are indeed equal to

one half and one fourth of the input voltage, respectively.

Similarly, to check the correctness of (25), experiments are

made, and the results are shown in Fig. 10. From Fig. 10,

one can observe that the voltage stress of the diodes is equal

to one fourth of the input voltage. The active switch voltage

waveforms of the simulation and experimental results are

shown in Fig. 11, which indicates that the maximum

voltages cross the switches VS1a, VS2a, and VS2b are equal to

200 V, which is indeed equal to one-half of the input

voltage. The maximum voltage that crosses the switch. A

precise power meter (YOKOGAWA-WT3000) was used to

measure the efficiency of the proposed converter. Fig. 12

shows the measured efficiency curve of the proposed high

step-down converter.

The measured full-load efficiency is 93.36%, and the

maximum efficiency is 94.4%. It can be seen that, from Fig.

12,with the increase of the output load, the conversion

efficiency decreases due to a larger current, which will

result in relatively larger conduction losses and switching

losses. Fig. 13 shows the corresponding loss analysis of the

proposed converter at full load as an illustration. By

analyzing the power loss distribution, it can be concluded

that the major losses come from the active switches, the

diodes, and the output inductors. From Fig. 13, it can also

be seen that the conduction loss of diodes is obviously

larger than other component losses. In order to further

increase the converter efficiency, one can adopt the

synchronous rectifier technology; namely, replace two

diodes with two MOSFETs. The corresponding measured

efficiency curve is shown in Fig. 14. From Fig. 14, it can be

seen that the measured full-load efficiency of the proposed

converter with synchronous rectifier is 95.4%, and the

maximum efficiency is nearly 96.7%.




Fig.12. Measured efficiency of the proposed converter.

Fig.13. Loss analysis of the proposed converter at full

load.

Fig.14. Measured efficiency of the proposed converter

with synchronous rectifier technology.

V. CONCLUSION

In the existing project we have designed and operated a

novel converter topology for interleaved high step-down

conversion ratio dc–dc converter with low switch voltage

stress. The propositioned converter consists of two input

capacitors and two blocking capacitors. Input capacitors are

series-charged by the input voltage and parallel discharged

by a new two-phase interleaved buck converter for

conveying a much higher step-down conversion ratio

without adopting an extreme short duty cycle. The blocking

capacitors are used to store energy in it. The propositioned

converter topology procures the low switch voltage stress as

a result. To reduce both switching and conduction losses

which will allow one to choose lower voltage rating

MOSFETs. The converter features automatic uniform

current sharing characteristic of the interleaved phases

without adding extra circuitry or complex control methods

due to the charge balance of the blocking capacitor. The

overall efficiency is subsequently enriched. A 400-V input

voltage, 25-V output voltage, and 400-W output MATLAB

Simulink model is to verify the performance.

VI. APPENDIX A

According to the simulation and experiment, the current

waveforms of the switches, diodes, inductors, and capacitors

are adopted to calculate the approximate loss of each

component at full load, and the results are listed as (A1)–

(A7) for reference. Also, to simplify the calculation, the

converter losses and the voltage and current waveforms are

approximated with piecewise linear segment. The

corresponding expressions of losses are shown as follows.

1) Active switch conduction losses

I2S 1a(rms) ×RDS1a(on) + I2S 1b(rms) ×RDS1b(on)

+ I2S 2a(rms) ×RDS2a(on) + I2S 2b(rms) ×RDS2b(on)

= [DI2O/16 + D(−1 + D)2v2O/12f2L2 ×

RDS1a(on)+RDS1b(on)+RDS2a(on)+RDS2b(on)

_.

(A1)

VII. APPENDIX B

According to the specifications, the voltage stresses of

actives witches and diodes are provided, as listed in Table

IV. According to the specifications, proper components are

chosen, and the corresponding parameters are given in Table

V. The loss analysis of the conventional IBC [17] and

proposed converter is shown in Table VI.

TABLE IV: Comparison of the Steady-State

Characteristics




TABLE V: Various Component Parameters

TABLE VI: Loss Analysis Results

VIII. REFERENCES

[1] D. D.-C. Lu and V. G. Agelidis, ―Photovoltaic-battery-

powered dc bussystem for common portable electronic

devices,‖ IEEE Trans. PowerElectron., vol. 24, no. 3, pp.

849–855, Mar. 2009.

[2] K. Sun, L. Zhang, Y. Xing, and J. M. Guerrero, ―A

distributed controlstrategy based on dc bus signaling for

modular photovoltaic generationsystems with battery energy

storage,‖ IEEE Trans. Ind. Electron., vol. 26,no. 10, pp.

3032–3045, Oct. 2010.

[3] H. R. E. Larico and I. Barbi, ―Three-phase push–pull dc–

dc converter:Analysis, design, experimentation,‖ IEEE

Trans. Ind. Electron., vol. 59,no. 12, pp. 4629–4636, Dec.

2012.

[4] M. Pahlevaninezhad, J. Drobnik, P. K. Jain, and A.

Bakhshai, ―A loadadaptive control approach for a zero-

voltage-switching dc/dc converterused for electric vehicles,‖

IEEE Trans. Ind. Electron., vol. 59, no. 2,pp. 920–933, Feb.

2012.

[5] R. L. Lin, C. C. Hsu, and S. K. Changchien, ―Interleaved

four-phasebuck-based current source with isolated energy-

recovery scheme for electrical

discharge machine,‖ IEEE Trans. Power Electron., vol. 24,

no. 7,pp. 2249–2258, Jul. 2009.

[6] C. Garcia, P. Zumel, A. D. Castro, and J. A. Cobos,

―Automotive dc–dcbidirectional converter made with many

interleaved buck stages,‖ IEEETrans. Power Electron., vol.

21, no. 3, pp. 578–586, May 2006.

[7] Y. C. Chuang, ―High-efficiency ZCS buck converter for

rechargeablebatteries,‖ IEEE Trans. Ind. Electron., vol. 57,

no. 7, pp. 2463–2472,Jul. 2010.

[8] C. S.Moo, Y. J. Chen, H. L. Cheng, and Y. C. Hsieh,

―Twin-buck converter

with zero-voltage-transition,‖ IEEE Trans. Ind. Electron.,

vol. 58, no. 6,pp. 2366–2371, Jun. 2011.

[9] X. Du and H. M. Tai, ―Double-frequency buck

converter,‖ IEEE Trans.Ind. Electron., vol. 56, no. 54, pp.

1690–1698, May 2009.

[10] J. A. S. Morales, J. Leyva-Ramos, E. E. G. Carbajal,

and M. G. Ortiz-Lopez, ―Average current-mode control

scheme for a quadratic buck converter

with a single switch,‖ IEEE Trans. Power Electron., vol. 23,

no. 1,pp. 485–490, Jan. 2008.

[11] J. P. Rodrigues, S. A. Mussa,M. L. Heldwein, and A. J.

Perin, ―Three levelZVS active clamping PWM for the dc–dc

buck converter,‖ IEEE Trans.Power Electron., vol. 24, no.

10, pp. 2249–2258, Oct. 2009.

[12] X. Ruan, B. Li, Q. Chen, S. C. Tan, and C. K. Tse,

―Fundamental considerationsof three-level dc–dc

converters: Topologies, analysis, control,‖IEEE Trans.

Circuit Syst., vol. 55, no. 11, pp. 3733–3743, Dec. 2008.

[13] Y. M. Chen, S. Y. Teseng, C. T. Tsai, and T. F. Wu,

―Interleaved buckconverters with a single-capacitor turn-off

snubber,‖ IEEE Trans. Aerosp.Electron. Syst., vol. 40, no.

3, pp. 954–967, Jul. 2004.

[14] C. T. Tsai and C. L. Shen, ―Interleaved soft-switching

coupled-buckconverter with active-clamp circuits,‖ in Proc.

IEEE Int. Conf. PowerElectron. Drive Syst., 2009, pp.

1113–1118.

[15] K. Yao, Y. Qiu, M. Xu, and F. C. Lee, ―A novel

winding-coupled buckconverter for high-frequency, high-

step-down dc–dc conversion,‖ IEEETrans. Power Electron.,

vol. 20, no. 5, pp. 1017–1023, Sep. 2005.

[16] K. Yao, M. Ye,M. Xu, and F. C. Lee, ―Tapped-inductor

buck converter forhigh-step-down dc–dc conversion,‖ IEEE

Trans. Power Electron., vol. 20,no. 4, pp. 775–780, Jul.

2005.

[17] I.-O. Lee, S.-Y.Cho, and G.-W. Moon, ―Interleaved

buck converter havinglow switching losses and improved

step-down conversion ratio,‖ IEEETrans. Power Electron.,

vol. 27, no. 8, pp. 3664–3675, Aug. 2012.

[18] P. Xu, J. Wei, and F. C. Lee, ―Multiphase coupled-

buck converter—Anovel high efficient 12 V voltage

regulator module,‖ IEEE Trans. PowerElectron., vol. 18, no.

1, pp. 74–82, Jan. 2003.

[19] H. Mao, L. Yao, C. Wang, and I. Batarseh, ―Analysis

of inductor currentsharing in non-isolated and isolated

multiphase dc–dc converters,‖ IEEETrans. Ind. Electron.,

vol. 54, no. 6, pp. 3379–3388, Dec. 2007.

[20] L. Sung-Sae, ―Step-down converter with efficient ZVS

operation withload variation,‖ IEEE Trans. Ind. Electron.,

vol. 61, no. 1, pp. 591–597,Jan. 2014.




Author’s Profile:

K.S.Sambaiah, received B.Tech degree

Form (Electrical& Electronics Engineering)

in Priyadarshini Institute of Technology,

Tirupathi, in 2012. M.Tech (Power

Electronics) from KEC, Kuppam and

JNTUA, his research areas Include switched

mode regulators and high step-down conversion ratio dc-dc

converters.

Dr. Venugopal. N has obtained his PhD

from Dr. MGR University, Chennai. He

obtained both B.E. and M.E. Degree from

Bangalore University respectively. He has

18 years of teaching experience. His

research area is Digital Image Processing

& Video separation. He is currently

working as an HOD of EEE Department & Director of R &

D in Kuppam Engineering College, Kuppam, and Chittoor

Andhra Pradesh. His research area of interest includes

Power electronics, power systems, renewable energy

sources and Embedded Systems.

a novel converter topology for high step-down conversion ...a novel converter topology for high...

Documents