a novel converter topology and mixed-signal controller for ......operation. power management systems...
TRANSCRIPT
A Novel Converter Topology and Mixed-Signal Controllerfor Pulse Powered Applications
by
Ivan Radovic
A thesis submitted in conformity with the requirementsfor the degree of Masters of Applied Science
Graduate Department of Electrical and Computer EngineeringUniversity of Toronto
c© Copyright 2019 by Ivan Radovic
Abstract
A Novel Converter Topology and Mixed-Signal Controller for Pulse Powered
Applications
Ivan Radovic
Masters of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2019
The work presented in this thesis introduces a novel converter topology and associated
controller for pulsed power systems. The presented work offers a flexible solution to the
challenges of pulsed power charging by managing long pulse duration and high pulsing
frequency while avoiding the limitations of linear solutions. The proposed converter is
flexible, allows universal conversion ratios, high frequency operation and its viability
is verified through an application specific design. The operating modes and control
methods of the proposed topology for operation as a pulsed power supply are analyzed.
Also presented is an application specific implementation for use in pulsed battery charging
systems. The prototype can operate as both a constant and pulsed power supply, achieve
a maximum pulsing frequency of 50 kHz while providing output currents up to 30A, while
also offering over voltage protection and battery maintenance modes. The practical
challenges and limitations of the solutions are discussed.
ii
Acknowledgements
First and foremost, I would like to thank my supervisor, Prof. Aleksandar
Prodic, for giving me this wonderful opportunity. Your passion and enthusiasm for
the field of power electronics served as a great instigator for action and motivated me to
further my studies in this field and remain excited throughout. I am eternally grateful for
the wisdom, both academic and non-academic that you have imparted to me throughout
my journey. Your honesty, support, and encouragement have been phenomenal during
my time here.
Furthermore, I would like to thank Tim McRae for being a fantastic men-
tor throughout my journey. His guidance and insightful advice helped me many times
throughout my studies. To my lab mates, Basil, Gianluca, Ksenija, Jasmine, Michael and
Sam. Thank you all for providing me with a welcoming and supportive work environ-
ment, your willingness to share your knowledge and your time helped me through some of
my most stressful times. To my close friends, Kyle, Iris, Nikita, Pranali, Scott, Thomas,
Tristan, and Valerian. Thank you for your enduring support and comfort through the
highs and the lows of my academic journey and ensuring I never went too long without
a smile on my face.
Finally, I would like to thank and dedicate my work to my family; my parents
Sanja and Blazimir as well as my sister Natasa. Without your love and continued support
there would be no way I am where I am today.
iii
Contents
1 Introduction 1
1.1 Introduction and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Prior Art 7
2.1 LiDAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pulsed Current Battery Charging . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Medical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Proposed Solution 14
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Control for Operating as a Pulsating Power Supply . . . . . . . . . . . . 21
3.3.1 Pre-charge State . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
iv
3.3.2 Current Maintenance State . . . . . . . . . . . . . . . . . . . . . . 23
3.3.3 Current Pulsing State . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Pulsating Power Supplies for Battery Charging 27
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Application of Interest . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Proposed Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 Three Level Switched Capacitor Ladder . . . . . . . . . . . . . . . . . . . 33
4.4.1 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.2 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 Specific Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5.1 Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . 44
4.5.2 Reverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5 Practical Implementation 48
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2.1 Three Level Switched Capacitor Ladder . . . . . . . . . . . . . . 50
5.2.2 Universal Symmetric Converter (USC) . . . . . . . . . . . . . . . 52
v
5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6 Conclusion 63
6.0.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Bibliography 64
vi
List of Tables
3.1 Operating Modes of the Universal Symmetric Converter . . . . . . . . . . 16
3.2 Switch Current Ratings for the USC . . . . . . . . . . . . . . . . . . . . 18
3.3 Switch Blocking Voltages of the USC . . . . . . . . . . . . . . . . . . . . 19
3.4 Voltage and Switch Requirements for inverting and non-inverting buck-
boosting from V1 to V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 USB PD Power profile options . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Optimization design parameter sweeping ranges . . . . . . . . . . . . . . 37
4.3 Optimized design selected for 30 A output current . . . . . . . . . . . . . 42
5.1 Components selected for design implementation - USC . . . . . . . . . . 50
5.2 Converter operating conditions . . . . . . . . . . . . . . . . . . . . . . . 51
vii
List of Figures
1.1 Simplified schematic of a standard linear regulator [8] . . . . . . . . . . . 2
1.2 iPhone X PCB area teardown.
https://www.ifixit.com/Teardown/iPhone+X+Teardown/98975 . . . . . 4
1.3 Area breakdown of the iPhone X motherboard PCB . . . . . . . . . . . . 5
2.1 Pulsed power supply for LiDAR systems . . . . . . . . . . . . . . . . . . 8
2.2 Battery adaptive pulsing state diagram [3] . . . . . . . . . . . . . . . . . 9
2.3 Implementation of adaptive pulse charging algorithm [3] . . . . . . . . . 10
2.4 Duty and frequency perturbations for adaptive pulsing algorithm [3] . . . 11
2.5 Pulsed power supply for medical applications . . . . . . . . . . . . . . . . 12
3.1 Universal Symmetric Converter with ideal four quadrant switches . . . . 15
3.2 Switch current direction and voltage polarity assumptions . . . . . . . . 16
3.3 Basic operating modes of the USC . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Using the design tables to arrive at different implementable solutions . . 20
3.5 Controller structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
viii
3.6 Mode Structure of Controller FSM . . . . . . . . . . . . . . . . . . . . . 22
3.7 Pre-charge state switching sequence and equivalent circuits . . . . . . . . 23
3.8 Current maintenance state switching sequence and equivalent circuits . . 24
3.9 Current pulsing state switching sequence and equivalent circuits . . . . . 25
4.1 Diagram of lithium cell construction [7] . . . . . . . . . . . . . . . . . . . 29
4.2 CC-CV Charging procedure . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 Proposed topology for pulsed battery charging . . . . . . . . . . . . . . . 32
4.4 Three Level Switched Capacitor Ladder Topology . . . . . . . . . . . . . 33
4.5 Switching states of the 3L-SCL . . . . . . . . . . . . . . . . . . . . . . . 35
4.6 Design curves of stacked switched capacitor ladders from two to six levels 38
4.6 Design curves of stacked switched capacitor ladders from two to six . . . 39
4.6 Design curves of stacked switched capacitor ladders from two to six . . . 40
4.7 Design set comparisons at fixed ripple values . . . . . . . . . . . . . . . . 41
4.8 Three Level Series Parallel Capacitor Converter . . . . . . . . . . . . . . 43
4.9 Comparing the solutions sets of three level stacked switched capacitor
ladders and series-parallel capacitor ladder . . . . . . . . . . . . . . . . . 44
4.10 Revised FSM Controller for pulsed battery charging . . . . . . . . . . . . 45
4.11 Battery discharge switching configuration . . . . . . . . . . . . . . . . . . 46
5.1 Fabricated PCB for design realization . . . . . . . . . . . . . . . . . . . . 49
ix
5.2 Efficiency plots for the 3L-SCL . . . . . . . . . . . . . . . . . . . . . . . 52
5.3 Implemented topology and controller . . . . . . . . . . . . . . . . . . . . 53
5.4 Open Loop buck mode operation and efficiency . . . . . . . . . . . . . . 54
5.5 Converter pre-charge and current maintenance states . . . . . . . . . . . 55
5.6 Lithium battery AC impedance . . . . . . . . . . . . . . . . . . . . . . . 57
5.7 Converter pulsing operation . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.8 Converter over voltage and reverse current operation . . . . . . . . . . . 60
5.9 25 A Current Pulse to 25 A discharge; Ch 1: valley detection, Ch 3: IL,
Ch 4: Iout, D0−7 gating signals . . . . . . . . . . . . . . . . . . . . . . . . 61
x
Chapter 1
Introduction
1.1 Introduction and Motivation
Power management systems are an essential part of any electronic system, with analog
and digital systems almost ubiquitously requiring regulated power supplies for proper
operation. Power management systems are built from power supplies that can be viewed
as having two distinct parts; the converter and the associated control system. The
converter is a circuit that is responsible for converting voltage or current from the input
level, such as a battery or power outlet, to the level required by the load, such as a
CPU processor, Light Emitting Diode (LED) or audio amplifier. The controller circuit
regulates converter operation to achieve the desired output voltage or current. The type
of power management system to be used in an application depends on the requirements
of the load. Conventional power management systems, such as point of load (PoL)
supplies in cellphones, provide a constant regulated voltage and current to the output.
Increasingly, power management systems that provide pulsating, square wave currents
or voltages are finding use in wide range of applications including medical devices such
as implantable stimulators, Light Detection and Ranging (LiDAR) systems, and AC
battery charging with consideration for employment in mobile cellphones [32, 30, 3, 15].
1
Whether conventional or pulsating, designers of both types of power supplies are striving
to make smaller and more compact solutions. Doing so allows for the introduction of
more functional blocks at the device’s system level.
Figure 1.1: Simplified schematic of a standard linear regulator [8]
Despite the growing number of applications for pulsed current power supplies,
linear regulators are still being used instead of switch mode power supplies (SMPS) in
a number of applications [15]. A simplified schematic of a standard linear regulator can
be seen in Figure 1.1. The pass device (Q1) has its current controlled by the switch Q2
and the voltage error amplifier. The amplifier senses the output voltage and compares
it to the reference, adjusting the output current by regulating Q2 and hence the current
of Q1 accordingly. Linear regulators can be modified to produce square wave currents.
By placing a switch in series between the linear regulator and the load, the current
can be chopped, limited only be the transition time of the switch and the parasitic
inductance of the circuit. However, linear regulators are quite inefficient as a power loss
2
of IL ∗ Vdrop (where Vdrop is the difference between Vin and Vout) will inevitably occur
across the pass device. This means that the power loss grows linearly with the power
output of the regulator. Furthermore, since much power is being dissipated across a
single device (or a collection of devices in a small area), linear regulators typically suffer
from heat dissipation issues as the power they are regulating increases. To accommodate
this increased heat dissipation, large heat sinks are needed. As a result, linear regulators
are often too bulky for practical use in commercial systems. Due to these issues, linear
regulators are not an effective choice as power supplies for higher power levels, or in
applications that requiring small volume. SMPS offer a more efficient and power dense
solution for power regulation. While SMPS are more power dense than linear regulators,
they may still be too big in some applications that require further innovation to meet
size constraints.
While SMPS are preferable to linear regulators in most applications, they suffer
from their own limitations. Two notable drawbacks are the increased design complexity
and larger than desired volume. SMPS require more complex control systems that pro-
vide their own set of challenges, such as how to produce fast current pulses for pulsed
power supplies. Implementation of these control systems and the use of bulky passive
components constitute the two main bottlenecks in low power electronics systems. The
issue of control is tackled by researchers and practicing in a variety of ways. The size
reduction of SMPS systems is primarily achieved through the volume reduction of passive
components. In many instances passive components (i.e. inductors and capacitors) are
the main bottlenecks of further miniaturization of power management systems. Take for
example Figure 1.2 which shows the bottom view of the iPhone X’s motherboard. The
passive components can be seen shaded in light blue, while the power management ICs
are circled in orange and pink. Of the roughly 32% of board area occupied by the power
management system, 23% is occupied by passives alone. Thus prioritizing the reduction
of passive component volume offers the potential for greater miniaturization while poten-
tially opening up board real estate for new functional blocks. Although this example is
application specific, reduction of power system passive component volume is ubiquitously
3
advantageous as other applications may use this space for additional protection circuitry
or simply for a more portable and lighter final product.
Figure 1.2: iPhone X PCB area teardown.https://www.ifixit.com/Teardown/iPhone+X+Teardown/98975
Considering a first order approximation, the volume of passive components is
proportional to the energy storage of the element. For capacitors this energy is approxi-
mated as WC = 1/2 ∗ C ∗ V 2 and for inductors it is WL = 1/2 ∗ L ∗ I2peak. Furthermore,
it can be shows that the inductance L is proportional to the voltage swing across the
inductor and inversely proportional to the frequency of the desired current ripple [6].
While increasing the switching frequency is a simple solution, it is often non-optimal
since it also increases switching losses. As a result, reducing the voltage swing across
the inductor terminals arises as the preferred strategy for inductor size reduction. This
strategy relies on the introduction of novel converter topologies and control algorithms
to limit the voltage swing across the inductor. Thus, a novel converter topology which
aims to reduce voltage swing across its inductor offers a superior alternative to existing
linear solutions for pulsed current delivery, while simultaneously addressing the issue of
passive component volume bottlenecking the miniaturization of SMPS solutions.
4
Figure 1.3: Area breakdown of the iPhone X motherboard PCB
1.2 Thesis Objective
The objective of this thesis is to introduce a flexible novel converter topology and asso-
ciated control system for operation as a pulsating power supply. As a design example, a
hybrid converter featuring the novel topology is presented for use in bipolar lithium-ion
battery charging applications. A procedure for how the topology can be adapted to other
applications will also be included. The functionality of the control circuitry for operation
as a pulsating power supply will be outlined. Challenges and issues in designing pulsating
power supplies for this application are addressed. Additionally, control capabilities are
introduced to cover the application specific needs of the converter. The feasibility and
effectiveness of the proposed topology and control methods have been verified through a
discrete prototype, using a FPGA based digital controller and a 3.6V nominal lithium-ion
battery as the load.
5
1.3 Thesis Outline
Chapter 2 reviews state-of-the-art solutions. Pulsating power supplies for various appli-
cations and their trade-offs are reviewed.
Chapter 3 introduces the novel topology. The converter’s modes of operation
and operating conditions are described in detail. A simple and systematic procedure is
devised for adapting the proposed topology to a variety of potential applications. The
controller developed to regulate the converter as a pulsating power supply is discussed.
The aforementioned design procedure is then used to tailor the introduced topology to
the application of bipolar pulsating battery charging.
Chapter 4 provides a description of a hybrid converter employing the novel
topology from chapter 3 as a power management system for AC lithium-ion battery
charging. The design challenges and additional application specific system requirements
are discussed. Design procedure and optimization of the hybrid converter is discussed
along with modifications to the originally presented control system.
Chapter 5 reviews the practical implementation of the hybrid converter system
introduced in Chapter 4. Experimental results confirming ability and performance of the
developed pulsating power supply are demonstrated.
Chapter 6 presents conclusions and discusses potential future work.
6
Chapter 2
Prior Art
As mentioned in the previous section, pulsing power supplies have found use in many
applications including LiDAR systems, fast charging and medical devices. In this chapter,
prior state of the art for different applications is reviewed, with an emphasis on fast
charging of Lithium-ion batteries.
2.1 LiDAR
One application of pulsed power supplies which is quickly gaining popularity is LiDAR.
LiDAR, short for Light Detection and Ranging is a popular surveying method used fre-
quently in geodesy, geography, seismology, and increasingly for the control and navigation
of autonomous vehicles [4]. LiDAR systems consist of a few key components one of which
is the laser diode used to generate the laser to perform the surface detection and rang-
ing functionalities. Since most LiDAR applications are tied to geographical mappings,
LiDAR systems often find themselves on Unmanned Aerial Vehicles (UAVs). Due to the
limited carrying capacity of the UAV, the laser diode and its power supply should be
lightweight, small volumetrically and highly efficient [12, 27, 2, 1]. Laser diodes require
periodic high power pulses to achieve sufficient detection sensitivity and resolution.
7
Figure 2.1: Pulsed power supply for LiDAR systems
The work in [17] presents an example of a solution to such a problem, which
can be seen in Figure 2.1. The topology consists of two coupled coils, a thyristor, a TTL
(Transistor-Transistor Logic) pulse signal, a resistor, and a capacitor. The TTL signal
operates as a binary signal with some voltage bandwidth; signals below 0.8 V are seen
as a zero or ground while signals above 2.8 V as seen as supply voltage Vdd or 5 V. The
converter operates off of a +28 V DC power supply provided by the UAV. The output
voltage at the laser diode D1 is set at 300 V, which can be tuned by adjusting the turns
ratio of the transformer. The basic operation of the converter is as follows: before the
TTL signal arrives, C1 is charged through R1 and L1 to +28 V. During this time the
thyristor Q1 is off and the output voltage of the circuit is 0 V. Once the TTL signal goes
high, C1 begins discharging through thyristor Q1. The reflected voltage applied across
coil L1 introduces a low resistance into the circuit, resulting in a large voltage across L2.
The output voltage is the inverted sum of the voltages across L1 and L2, coupled to the
output through the R2 and C2. A turns ratio of approximately 10 to 1 between L2 and
L1 is used to achieve an output voltage of 300 V. Capacitor C3 is used to prevent high
voltage spikes from damaging the power supply.
The discussed topology has the ability to pulse at voltages between 100 V and
8
300 V, with currents up to 120 A, with pulse duration between 50-200 µs and pulse
frequency of 50 Hz. It is a favorable solution for a number of reasons including its
simplicity, availability of components and ability to meet the requirements of the UAV
platform. While well suited for those applications, the design possesses some inherent
disadvantages. While the output voltage is adjustable, the adjustment can only take
place in discrete steps which depends on the input voltage. Furthermore, the duration
of the pulses is rather short and the pulsing frequency very low. These disadvantages
strongly limit the potential employment of this topology to other applications.
Figure 2.2: Battery adaptive pulsing state diagram [3]
2.2 Pulsed Current Battery Charging
Another application in which pulsed power supplies have gained increasing popularity
in recent years is the field of battery charging. While batteries have traditionally been
charged using constant currents, recent publications such as [30, 3, 15] have shown that
pulsed current charging of batteries can be more efficient and faster than conventional
constant current methods. The works presented in [3] and [15] construct systems that
9
Figure 2.3: Implementation of adaptive pulse charging algorithm [3]
attempt to determine the optimal pulsing duty ratio for battery pulsing. A simple state
diagram for the operation detailed in [15] is shown in Figure 2.2. The practical implemen-
tation of the algorithm is shown in Figure 2.3 with the logic of the charging period shown
in Figure 2.4. At the start of every cycle, the battery voltage is checked to verify if the
charging process is complete. If not, the power supply enters the charging procedure. In
this procedure, the duty ratio and frequency of the pulsing is iteratively perturbed until
the optimal charging factor is determined. Multiple perturbations are often used until
an optimal duty ratio and frequency are determined, which ultimately lead to superior
charging times and efficiencies.
The experimental setup consists of a linear voltage regulator connected to a
lithium ion battery through an isolator switch. The setup also includes sensing circuitry,
to determine the average pulse current and the battery voltage, as well as a controller
to regulate the connection between the regulator and battery. The advantages of this
implementation are relative simplicity and availability of components, while being able to
10
perform the pulsating algorithm proposed in [3]. The drawback, however, is that linear
regulators are inherently lossy as discussed in Chapter 1. This means that the pulsing
current of such a solution is limited to 100s of mA. Therefore, for higher currents, linear
regulators become unfeasible.
Figure 2.4: Duty and frequency perturbations for adaptive pulsing algorithm [3]
11
Figure 2.5: Pulsed power supply for medical applications
2.3 Medical Applications
A third domain in which pulsed power supplies have found use are medical applications.
The paper given in [17] proposes a power supply to produce high-intensity magnetic
and electric fields for the medical uses of electric stimulators. Such stimulators can find
multiple applications, with the treatment of renal calculus disease (kidney stones) being
the application explored in the paper. In this instance, magnetic/electric stimulation of
the kidney can aid with peristalsis, helping to move food along the digestive tract and
facilitate the passing of kidney stones. The topology proposed in [17] can be seen in
Figure 2.5. The capacitor C is realized by a capacitor bank of two parallel connected 200
uF/22 kV capacitors with their charging system controlled through a fiber-optic link.
The capacitor bank is separated from the pulsing coils via a pneumatically controlled
switch. The parallel connected diode and ballast resistor Rballast stack is used to control
the shape of the current pulse and prevent the possibility of reverse charging of the bank.
Two identical spiral coils are mounted side by side and carrying currents in opposed
12
directions produce the magnetic field. The current through the parallel resistor Lcoil
produces a magnetic field which then induces a magnetic field in the second, remote coil.
This method allowed for the creation of electric fields of up to 400 V/m at distances of
50 mm from 15kV shots from the capacitor bank. The increased strength of the electric
field at the distance of 50 mm opens the door for other medical applications beyond the
treating of renal calculus disease mentioned earlier.
As can be seen, pulsed power supplies are employed in a variety of applications.
The solutions vary both in their complexity and in the power of the output pulses pro-
duced. A commonality amongst all the presented solutions is that they are application
specific designs. One would find it difficult to employ these solutions in any application
but the ones they were specifically designed for. Furthermore, solutions such as the linear
circuits used to employ pulsed battery charging [15] are inhibitive due to the previously
mentioned shortcomings. In the following section, a novel topology and controller will
be introduced which can potentially be used in various pulsed power applications. A
specific implementation tailored for efficient pulsed battery charging will follow.
13
Chapter 3
Proposed Solution
3.1 Introduction
The solution proposed in this work is the Universal Symmetric Converter (USC) shown
in Figure 3.1. Here, we shall assume that SW1 to SW6 are all ideal four quadrant
switches. The name was chosen to reflect the structure and flexibility of the topology.
The converter’s symmetry is centered around the inductor; looking over a vertical or
horizontal line passing through the inductor we can see the same circuit on both sides.
The universal term is given to denote that the converter is capable of achieving step down,
step-up, or step up/down conversion ratios, with inverting and non-inverting polarities
for the latter. Starting from this structure and desired conversion ratio, we can perform
an analysis of the switch blocking voltages and conduction currents to determine which
switches need to be four quadrant and those which we can be reduced to two quadrant
switches. The key features and design decisions for the employment of the USC as a
pulsating power supply are shown in the following subsections. Section 3.2 discusses
the USC’s ability to be operated with various DC-DC conversion ratios. An analysis
is performed on the switch blocking voltage and current conduction requirements for
each mode of operation. From here, a design table is constructed to aid the creation of
14
application specific converter topologies based on the requisite modes of operation and the
associated switch requirements. Section 3.3 details the control architecture implemented
to operate the USC as a pulsating power supply. The operation of the finite state machine
(FSM) controller are explained in more detail. Section 3.4 summarizes the chapter and
the key points of the proposed solution.
Figure 3.1: Universal Symmetric Converter with ideal four quadrant switches
15
3.2 Principle of Operation
The particular operating conditions of the USC are dependent on the desired conversion
ratio. As mentioned in section 3.1, the USC has the capability of producing any con-
version ratio. Assuming a converter model employing ideal four quadrant switches, the
USC can perform these conversions in a bidirectional manner. The switching sequences
provide these conversion ratios are listed in Table 3.2 and corresponding circuit states in
3.3.
Conversion Mode Conversion Ratio 0 < t < DTs DTs < t < TsForward Buck D from V1 to V2 Q1, Q6 Conducting Q2, Q6 ConductingForward Boost D’ from V1 to V2 Q1, Q5 Conducting Q1, Q6 Conducting
Forward Buck-Boost -D/D’ from V1 to V2 Q1, Q5 Conducting Q2, Q6 ConductingForward NIBB D/D’ from V1 to V2 Q1, Q5 Conducting Q3, Q5 ConductingReverse Buck D from V2 to V1 Q3, Q4 Conducting Q2, Q4 ConductingReverse Boost D’ from V2 to V1 Q3, Q5 Conducting Q3, Q4 Conducting
Reverse Buck-Boost -D/D’ from V2 to V1 Q3, Q5 Conducting Q1, Q5 ConductingReverse NIBB D/D’ from V2 to V1 Q3, Q5 Conducting Q2, Q4 Conducting
Table 3.1: Operating Modes of the Universal Symmetric Converter
Figure 3.2: Switch current direction and voltage polarity assumptions
16
(a) Buck operation, phase 1 (b) Buck operation, phase 2
(c) Boost operation, phase 1 (d) Boost operation, phase 2
(e) NIBB operation, phase 1 (f) NIBB operation, phase 2
(g) Buck-boost operation, phase 1 (h) Buck-boost operation, phase 2
Figure 3.3: Basic operating modes of the USC
17
The table and states show that for any desired conversion ratio a switching
sequence exists. They also show that by using six four quadrant switches it would be
possible to create a truly universal converter. However, the requirement of employing four
quadrant switches would necessitate a compromise. While the implementation of four
quadrant switches allows for 8 modes of operation, it would result in a loss of efficiency
and an increase in cost. Assuming the common implementation of the four quadrant
switch as two back to back MOSFETs, the component count would be doubled with
respect to the diagram shown in Figure 3.1. Efficiency losses would manifest in the form
of increased resistance in the conduction path and Coss losses from switching the added
MOSFETs. However, target applications will rarely if ever require the need for all the
modes. To arrive at a more efficient model we can analyze the requisite blocking voltages
and conduction currents of each switch. Then, by selecting the functionality necessary for
our application we can narrow down which switches can be two, three, or four quadrant.
In doing so, we can derive an implementation of the USC specific to our application but
with the additional flexibility inherent in the symmetric topology.
Mode ofOperation
IQ1 IQ2 IQ3 IQ4 IQ5 IQ6
ForwardBuck
IL −IL / / / IL
ForwardBoost
IL / / / IL IL
ForwardBuck-Boost
IL / −IL / IL /
ForwardNIBB
IL −IL / / IL IL
ReverseBuck
/ −IL −IL −IL / /
ReverseBoost
/ / −IL −IL IL /
ReverseBuck-Boost
IL / −IL / IL /
ReverseNIBB
/ −IL −IL −IL IL /
Table 3.2: Switch Current Ratings for the USC
18
Mode ofOperation
VQ1 VQ2 VQ3 VQ4 VQ5 VQ6
ForwardBuck
V1 V1 V1 − V2 or−V2
V1 − V2 V2 /
ForwardBoost
/ V1 V1 − V2 V1 − V2 orV1
V2 −V2
ForwardBuck-Boost
V1 − V2 V1 or V2 V1 − V2 V1 / −V2
ForwardNIBB
V1 V1 V1 − V2 or−V2
V1 − V2 orV1
V2 −V2
ReverseBuck
V1 − V2 orV1
V2 −V2 / V1 V1 − V2
ReverseBoost
V1 − V2 V2 / V1 V1 −V2
ReverseBuck-Boost
V1 − V2 V1 − V2 orV2
V1 − V2 V1 / −V21
ReverseNIBB
V1 − V2 orV1
V2 −V2 V1 V1 V1 − V2 or−V2
Table 3.3: Switch Blocking Voltages of the USC
In this analysis we will assume that power transfer from V1 to V2 is the forward
operation of the converter and that power transfer from V2 to V1 is reverse operation.
Applying these conventions and analyzing the USC’s switching sequences, we arrive at
the switch current and voltages listed in Tables 3.2 and 3.3.
Having performed this analysis, we now have the guidelines for designing ap-
plication specific implementations of the USC. For example, if we were designing for an
application that requires inverting and non-inverting buck-boosting from V1 to V2 the
necessary conducting currents and blocking voltages are as shown in Table 3.4.
Parameter Q1 Q2 Q3 Q4 Q5 Q6
Voltage V1 orV1 − V2
V1 orV1 − V2
−V2 orV1 − V2
V1 orV1 − V2
V2 −V2
Current IL −IL −IL / IL IL
Table 3.4: Voltage and Switch Requirements for inverting and non-inverting buck-boosting from V1 to V2
Table 3.4 also gives guidelines for selecting types of switches. Knowing that
19
MOSFETs, which are used for most modern switch realizations in low to mid power
applications, are two quadrant switches capable of bidirectional current conduction and
blocking a positive voltage. The converter for our target application may be implemented
as seen in Figure 3.4. Table 3.2 shows that for the targeted conversion ratios, SW4 does
not conduct current. This allows us a choice in our design. If component count and area
are of utmost importance, SW4 can be removed from the topology to achieve a more
compact final product. If the target application requires specifically tailored control
methods, the designer may choose to retain SW4 to exploit the flexibility offered by a
symmetric topology. This procedure can be repeated for any combination of operational
requirements, creating a subset of converters from the USC that can be individually
tailored to their application of interest.
Figure 3.4: Using the design tables to arrive at different implementable solutions
20
Figure 3.5: Controller structure
3.3 Control for Operating as a Pulsating Power Sup-
ply
The controller for operating the USC as a pulsating power supply is shown in Figure
3.6. The controller effectively turns the USC into a controlled current source where the
reference can be set by the designer. This behavior is achieved through digital control
employing a finite state machine (FSM) shown in Figure 3.6. The pre-charge state is
the default and handles converter start-up. The current maintenance state ensures the
inductor current tracks a set reference. The current pulsing state creates square wave
pulsing current.
21
Figure 3.6: Mode Structure of Controller FSM
3.3.1 Pre-charge State
The pre-charging state is the converter’s default start-up state. In this state, the inductor
is directly connected to the input through switches Q1 and Q5. This causes the inductor
current to increase at a rate of (Vg/L) for the duration of the pre-charge. The primary
motivation for employing this pre-charge state is that it brings the inductor current to
the desired level before creating pulses. Hypothetically, this allows the converter to
achieve perfectly square current pulses. In practice, output current slew rate of the USC
is limited by the ability of Q6 to source current to the output. Therefore we can achieve
higher slew rates than are typically possible for a given VL and inductance value, which
in turn allows us to pulse the output current at a higher frequency then would otherwise
be possible. The switching state and gating signals for the pre-charge state can be seen
in Figure 3.7. The USC remains in this configuration until a predefined peak current is
reached. At this point the FSM transitions to the current maintenance state.
22
(a) Pre-charge phase 1 equivalent circuit (b) Pre-charge state switching sequence
(c) Pre-charge state relevant signal wave-forms
Figure 3.7: Pre-charge state switching sequence and equivalent circuits
3.3.2 Current Maintenance State
The current maintenance state employs fixed on time (ton) valley mode control to enable
the USC to track an established current reference. After the peak current has been
detected in the pre-charge state, the inductor current is allowed to discharge through
switches Q2 and Q5. The inductor discharges in this fashion until the inductor current
drops below a valley or minimum reference current. Once this occurs, switch Q2 is turned
off and the switch Q1 is turned on for some pre-established time ton. After time ton has
elapsed, switch Q1 is once again shut off in favor of Q2 and the process repeats. An
advantage of employing fixed on time valley mode control is it allows us some control
over the inductor current ripple. This flexibility can be useful in applying this topology
to ripple sensitive applications or extracting greater efficiency in ripple insensitive ones.
23
The switching states and gating signals for the current maintenance state can be seen
in Figure 3.8. The converter remains in the current maintenance state until it receives
an indication that the output load should be pulsed. At this point, it enters the current
pulsing state.
(a) Current maintenance phase 1 equivalentcircuit
(b) Current maintenance phase 1 switchingsequence
(c) Current maintenance phase 2 equivalentcircuit
(d) Current maintenance relevant signalwaveforms
Figure 3.8: Current maintenance state switching sequence and equivalent circuits
3.3.3 Current Pulsing State
The current pulsing state is entered when the controller receives a request for the out-
put to be pulsed with current. In this state, the controller employs the same current
maintenance logic detailed in section 3.3.2 with the addition of periodically sourcing the
output with current. When the output is not being sourced with the current, the switch-
24
(a) Current pulsing phase 1 equivalent cir-cuit
(b) Current pulsing switching sequence
(c) Current pulsing phase 2 equivalent cir-cuit
(d) Current pulsing relevant signal wave-forms
Figure 3.9: Current pulsing state switching sequence and equivalent circuits
ing behavior mimics that outlined in section 3.3.2. When the output is being pulsed
with current, the role of Q5 is performed by Q6. In the first time interval Q2 and Q6
are conducting such that the inductor current is decreasing at a rate of (Vo/L). Once
the inductor current drops below the established reference Q2 stops conducting while Q1
connects the input and output through the inductor. Since the slope of the inductor
current is only (Vg − Vo)/L for this interval, and its duration is still fixed at the same
ton as before, we expect the converter to operate with a higher frequency and smaller
ripple in the current pulsing state. The switching states and gating signals for the current
pulsing state can be seen in figures 3.9a and 3.9b. For general use, the current pulsing
25
state effectively regulates the USC to operate as a pulsating power supply. In section 4,
additional application specific control methods will be detailed.
3.4 Conclusion
A novel converter topology, the USC, was introduced for pulsating power supplies. The
flexibility of the USC is highlighted by demonstrating its ability to produce multiple
conversion ratios in in either direction. A design guide was developed to show how the
USC can be tailored and physically implemented for specific applications depending on
the voltage regulation required. An example was provided for the case of a converter
requiring both inverting and non-inverting buck-boost functionality. The structure of
the FSM used to operate the USC as a pulsing power supply was explained in detail.
This structure includes a pre-charge state to establish the desired current, a current
maintenance state to sustain and regulate the inductor current between pulses, and a
pulsing state that delivers current to the output in a square wave when triggered.
26
Chapter 4
Pulsating Power Supplies for
Battery Charging
4.1 Introduction
With the meteoric rise of consumer electronics over the past decade, applications from
power tools to electric powered vehicles have adopted the battery as their power source of
choice. Specifically, lithium batteries have gained great popularity due to their appealing
features including high energy and power density, long life time, low self-discharge and
flexible geometry [15]. Lithium batteries are not limited to being used as supplies how-
ever; they are also used to improve the power quality of energy harvested from renewable
sources and as storage units of electrical energy in micro grid power management systems
[16].
Devices that operate off lithium batteries must inevitably be recharged at some
point. Regarding the charging process and their utilization, batteries are usually charac-
terized with three time based metrics: effective on-time, effective off-time and lifespan.
Effective on-time is the duration through which they can power a device without having
to be recharged. The effective off-time is the time required to restore the battery to
27
full charge. Finally, lifespan is the amount of time for which the battery will retain a
significant amount of its charge upon recharge. In the electric vehicle industry, battery
packs are usually replaced when they reach 70% capacity [14]. The lifespan of a battery
also be thought of as the number of complete charge and discharge cycles (from 0% to
100% charge) until the battery capacity is reduced to an established benchmark. For ex-
ample, if after 300 charges the battery can only hold 70% of its nominal charge capacity,
its lifecycle would be 300 charges. Charge cycles are usually used as a measurement of
lifespan, since they are independent of how frequently a given device would be used.
The goal of both researchers and industry alike is to increase the ratio of effective
on-time to effective off-time while maintaining or extending lifespan. This is an extremely
important goal, as one of the main drawbacks preventing a wider adoption of electric
vehicles is the comparatively long ‘refuel’ time of electric vehicles [5]. Improving the
effective on-time to off-time ratio can be achieved by decreasing the time required to
recharge the battery. While increasing the charging speed is the ultimate goal, it should
not cause a significant decrease in the battery’s lifespan. The methodology for preserving
battery lifespan requires some insight into the construction of lithium batteries and the
materials used.
Lithium-ion (Li-ion) and Lithium ion polymer (Li-Poly) are the most commonly
used lithium battery types in electronic devices and electric energy storage systems. The
anode and cathode electrodes of a lithium cell is made of a carbonaceous material and
lithium based metal oxide, respectively. As shown in 4.1 these electrodes are separated
by a semipermeable separator, which can only be traversed by lithium ions. The two
electrodes and separator are soaked in a lithium salt based electrolyte [22]. Graphite is
the most popular material used for the anode while the cathode is typically constructed
from one of three materials; a layered oxide, polyanion or a spinel. Common compounds
used for these materials include lithium cobalt oxide, lithium iron phosphate and lithium
manganese oxide respectively. Of these materials, cobalt is rarely mined individually and
most cobalt is produced as a byproduct of nickel mining. Should the demand for battery
production significantly increase due to irresponsible charging methods, the necessary
28
Figure 4.1: Diagram of lithium cell construction [7]
mining operations to supply the cobalt would inevitably have adverse environmental
impacts. Additionally, manganese has been shown to negatively affect the carbon storage
of coniferous trees [9]. Thus two of the key materials used in Li-ion battery production
hold potential adverse climate change effects. Hence, preserving the lifespan of existing
battery chemistries, until a more sustainable combination is found, through effective and
non-degrading charging methods, is of great importance.
Over the years as lithium batteries gained popularity, a variety of charging meth-
ods have been developed. The conventional solution employed by most Li-ion chargers
is constant current-constant voltage (CC-CV) charging [18, 11] depicted with diagram of
Figure 4.2. Other charging methods such as Constant Trickle Current (CTC) and Con-
stant Current (CC) have been previously tested but found to have inadequate charging
performance [19]. A multi stage variant of CC-CV is another widely spread fast charge
method [31, 20, 24]. Recently, pulse charging of Li-ion batteries [15] has arisen as a new
and promising charging strategy. In addition to its fast and efficient charge performance,
29
Figure 4.2: CC-CV Charging procedure
pulse charging offers the additional benefits of maximal battery utilization, low heating,
low degradation of battery materials and longer battery lifespan [10]. Furthermore, it has
been shown that pulse charging of the battery can improve charge speed [15, 3] over the
conventional CC-CV charging solutions. Furthermore, introducing negative pulses into
the charging procedure allows for greater currents to be used during charging [30]. To
make the most of these discoveries, a converter delivering pulsed power while also being
able to periodically discharge the battery is required. In the remainder of this thesis, an
application specific solution to this problem will be presented. Section 4.2 discusses the
specific target application and the associated design requirements and objectives. Section
4.3 outlines the proposed solution, based on previously described universal topology and
describes both the power stage and its controller. Section 4.4 analyzes the operation and
optimization of the topology in more depth. Section 4.5 explains the implementation
of additional controller functionality in more depth. Finally, Section 4.6 concludes on
this chapter by summarizing the design procedure and the proposed solution’s functional
abilities.
30
4.2 Application of Interest
The application targeted by the solution proposed in this thesis is bipolar pulsed battery
charging from a USB power delivery (USB PD) connection. Specifically, we are consid-
ering the input voltage as potentially ranging from 12V to 20V and the input current as
being limited to 5 A [25]. Since devices powered by USB tend to be small, we wish to
minimize the converter volume as much as possible while maintaining efficiency compa-
rable to existing solutions. To address the shortcomings of prior solutions discussed in
Chapter 2, we wish to design a system capable of operating with high pulsing frequencies
(10s of kHz), extended pulse duration (ideally indefinite), and output currents up to 30
A. Recent discoveries by the company G-Batteries showed that high current pulsing with
high slew rates can achieve faster charge times. This is due to the fact that pulsing with
high current allows us to achieve a higher average charge current than the battery can
sustain when receiving DC current. The algorithm additionally requires as high slew rate
as possible to avoid battery degradation, and makes use of reverse pulsing to mitigate the
ionization of the battery terminals. The load being supplied is assumed to be a Li-ion
battery with a nominal voltage between 3.5V and 3.7V, and whose capacity is on the
order of 1000s of mAh.
Mode of Operation Nominal Voltage Maximum Current NotesUSB PD Configurable up to
20 VConfigurable up to
5 ADirectional control
and power levelmanagement
Table 4.1: USB PD Power profile options
31
Figure 4.3: Proposed topology for pulsed battery charging
4.3 Proposed Solution
In order to meet the design constraints of the challenge outlined in Section 4.1, an
application specific topology and controller are developed. A hybrid, two stage topology
is proposed and shown in Figure 4.3. It consists of a three level switched capacitor ladder
converter (3L-SCL) followed by the USC described in Chapter 3. The justification for a
hybrid design will provided in later sections, when the design process is discussed. The
3L-SCL is used as the first stage to provide efficient 3-to-1 step down conversion. From
this intermediate voltage, the USC is used as a current shaping converter, regulating
the current and pulsing the output load as chosen by the designer. Application specific
control modes have been added to the original controller FSM presented in Chapter 3,
with detailed explanations of their operation outlined later in this chapter.
32
Figure 4.4: Three Level Switched Capacitor Ladder Topology
4.4 Three Level Switched Capacitor Ladder
As previously noted, one of the current bottlenecks to power management system minia-
turization is the volume of passive components. As discussed, two of the main strategies
for addressing this issue consisted of reducing the inductor size by increasing the switch-
ing frequency [6] or reducing the voltage swing seen at the inductor terminals [6]. The
use of the three level switched capacitor ladder (3L-SCL) allows us to reduce the inductor
volume via the latter method. The 3L-SCL effectively acts as a DC transformer provid-
ing a fixed, efficient 3-to-1 step down conversion ratio from the USB PD input to the
33
input of the USC converter. In doing so, the 3L-SCL ensures that the inductor will never
see a voltage swing greater than Vg/3 allowing for a smaller inductor size than would be
possible with the USC topology alone. Additionally, reducing the difference between the
USC input voltage and the output voltage allows us greater precision when assigning the
USC’s duty ratio. This may allow us to better track the battery voltage as it progresses
through different states of charge. On the other side, the use of the 3L-SCL and hence a
hybrid converter solution increases the component count. This decision can be justified
by the following considerations. First, power management ICs provide simple integration
of a large number of semiconductor components and are are shown to consume much less
space than the passive components surrounding them. Consequentially, passive compo-
nent size reduction often outpaces the space required to add more switches, resulting in
net area saved. Furthermore, capacitors have been shown to have greater energy density
than inductors [13, 21], so they occupy less space to process the same amount of power.
4.4.1 Principle of Operation
A schematic of the front end converter can be seen in Figure 4.4. As mentioned in
the previous section, the 3-level switched capacitor ladder serves as a high efficiency 3-
to-1 step down converter. The converter consists of three capacitors stacked atop one
another and connected across the input source. The voltage across these capacitors
is regulated by the two flying capacitors Cfly,1 and Cfly,2, which shuffle and equally
distribute charge between capacitors C1,C2, and C3. The equal distribution of charge
between these capacitors results in the 3-to-1 conversion ratio of the 3L-SCL. This charge
distribution is a result of operating the 3L-SCL with a fixed duty ratio of 50% or D =
0.5. Since the role of the 3L-SCL is to provide a high efficiency step down stage, it is
operated in open loop, the most efficient operating point.
34
(a) 3L-SCL, first switching state (b) 3L-SCL, second switching state
Figure 4.5: Switching states of the 3L-SCL
4.4.2 Design Procedure
The following subsections discuss key steps in the design that lead to the selection of the
3L-SCL. It includes a comparison between different numbers of levels of switched capac-
itor ladder (SCL) converters, a comparison against a series-parallel switched capacitor
converters, and the optimization procedure used for component selection.
4.4.2.1 Level Selection and Optimization
The SCL converter topology can be extended to any number of levels. The process of
choosing the number of levels depends on the application. As mentioned before, the SCL
is at its most efficient operating with D = 0.5 and a conversion ratio of N-to-1 where N is
the level of the SCL. Similarly, the number of switches and capacitors required to realize
35
a SCL are proportional to N. The number of switches needed is 2N and the number
of capacitors is 2N-1. Thus, we are trading off greater step-down ratios for increased
component count. From our operating point requirements, we decided to compare SCLs
with N ranging from two to six. For N greater than six, the component count becomes
prohibitively large. As a result, we are effectively losing part of the advantage gained by
employing a front end SCL in the first place.
In comparing our potential designs, we consider three criteria; the power pro-
cessing efficiency, the area needed to realize it and the suitability for the given application.
For the first two, we built a mathematical model, to compare designs with different val-
ues of N. The groundwork for such a mathematical comparison has already been lain.
Recently, the application of convex optimization to find the optimal operating point of a
converter has been demonstrated in [26]. Furthermore, this concept has been extended
to SC converters in [28]. The SC variation of this optimization requires the designer
to determine the charge, resistor and capacitor coefficients for a desired topology. The
charge coefficient is the amount of charge that passes through a given resistor (switch
on-resistance) relative to the charge that is sent to the output of the circuit. This analysis
method was developed by Dr. Seeman in his doctoral thesis and a detailed description
can be found therein [23]. The resistor coefficient is a value relating the loop resistance
during a given switching cycle to the circuit capacitor values and switching frequency.
Finally, the capacitor coefficients are ratios of individual capacitors in the circuit to the
output capacitor. In our analysis, the capacitor at the bottom of the ladder was consid-
ered the output capacitor, as this is where the input to the USC is connected. A simple
example analysis showing how these coefficients are calculated for a two level SCL are
presented in Appendix A. The full table of charge, resistor, and capacitor coefficients for
SCLs from N equal to two to six is also given in Appendix A.
As presented in [28], a switched capacitor circuit can be fully described by three
values; the switching frequency, the output capacitance, and the output current ripple.
Since the capacitor coefficients are known, we can derive the optimal value of other capac-
itors in the circuit from the output capacitor value. Once this is done, we can use these
36
Parameter Rangefsw 50 kHz - 5 MHzCout 50 nF - 200µF
∆Vout 25 mV - 250 mVIout 10 A
Table 4.2: Optimization design parameter sweeping ranges
capacitor values and the switching frequency to determine the optimal on-resistance of
all switches used to realize the circuit. Furthermore, we can use this resistance value to
determine the optimal Coss (output capacitance) of our switches as well. This procedure
gives guidelines for selecting components for desired performance. Finally, the optimiza-
tion aims to solve trade off problem between power processing efficiency and minimizing
area. It assigns a weight to both of these objectives from 0 to 1 at the start of each
iteration and attempts to find an optimal solution. It iterates until it has provided a
solution set where both extremes have been considered; minimizing loss with no interest
in area and minimizing area with no consideration for efficiency. This is possible due to
SC circuit optimization being a convex optimization problem, ensuring there is a global
minimum (or best) solution). The optimization requires framing the loss equations as
posynomials to allow the convex optimization solver to solve the geometric programming
problem. These set of solutions create what are known as a Pareto curves. We can gen-
erate multiple Pareto curves to generate Pareto graphs by holding one of the parameters
(switching frequency, output capacitance or output voltage ripple) and varying the oth-
ers. In this case we chose to hold output voltage ripple constant for each iteration of the
optimizer. So each Pareto curve corresponds to a specific output voltage ripple, where
the frequency and output capacitance are varied to try and minimize the aforementioned
loss functions. The range of switching frequency, output capacitance and output voltage
ripple considered by this optimization are shown in Table 4.4.2. Performing this analysis
on SCL converters for N equal to two to six. Results are shown in Figure 4.6.
Each curve represents a solution for a fixed output voltage ripple ranging from
25 mV to 250 mV in 25 mV steps. It has been shown that for all values of N, solutions
37
(a) 2 Level Switched Capacitor Ladder
(b) 3 Level Switched Capacitor Ladder
Figure 4.6: Design curves of stacked switched capacitor ladders from two to six levels
38
(c) 4 Level Switched Capacitor Ladder
(d) 5 Level Switched Capacitor Ladder
Figure 4.6: Design curves of stacked switched capacitor ladders from two to six
39
(e) 6 Level Switched Capacitor Ladder
Figure 4.6: Design curves of stacked switched capacitor ladders from two to six
40
(a) 75 mV Ripple Comparison
(b) 175 mV Ripple Comparison
Figure 4.7: Design set comparisons at fixed ripple values
41
limiting the output voltage ripple to 25 mV or 50 mV are too large and inefficient to be
considered viable solutions. Furthermore, we notice that, with the exception of the six
level case, after a certain point relaxing the constraint on the output voltage ripple does
not lead to a more efficient solution. Additionally, increasing the size of the converter at
this point leads to minimal or no efficiency improvement. To simplify, we selected one
or two voltage ripple values that look promising and compare designs at these specific
ripple values across different values of N. Figure 4.7 shows this comparison for fixed
values of 75 mV and 175 mV ripple. We can see that in both cases the two level and
three level solutions are superior in terms of both efficiency and area. Between these two
choices, the three level solution is shown to be realizable with lower area and comparable
efficiency. Once we also consider the benefits associated with having a larger step down
from the SCL input to the USC input, including reduced inductor voltage swing and
increased resolution in adjusting the duty ratio, the three level SCL appears to be the
ideal candidate for our front end step down converter. Repeating these optimizations
for an output current of 30 A, we arrive at the optimized circuit parameters shown in
Table 4.3. Note that these optimized values are from a continuous solution set and thus
the components we are actually able to source for a prototype will vary slightly from the
values listed in this table.
Parameter Valuefsw 1.4396 MHzC1 50 µFC2 150 µFC3 100 µFCfly,1 100 µFCfly,2 200 µFQ1 4.3 mΩ, 2.2 nFQ2 1.6 mΩ, 6.04 nF
Q3, Q5 0.867 mΩ, 11 nFQ4, Q6 1.3 mΩ, 7.38 nF
Table 4.3: Optimized design selected for 30 A output current
42
Figure 4.8: Three Level Series Parallel Capacitor Converter
4.4.2.2 Comparison with Series-Parallel Capacitive Ladder
Having selected the three level as the most promising solution SCL, we also compared
it with an alternate topology. The Series-Parallel switched capacitor (SPSC) converter
shown in Figure 4.8. offers an alternative to the SCL. The SPSC requires N capacitors
and 3N – 2 switches for a N-to-1 conversion ratio. We conducted the same charge, resistor
and capacitor analysis on the SPSC. Analysis results can be found in Appendix A. Figure
4.9 shows a comparison of the SCL and SPSC topologies with 10 A output current and
100 mV output voltage ripple. It can be seen that the SCL outperforms the SPSC across
the board, achieving higher efficiency for the same area, or conversely providing a denser
design at the same efficiency. Thus, we opted for the SCL.
43
Figure 4.9: Comparing the solutions sets of three level stacked switched capacitor laddersand series-parallel capacitor ladder
4.5 Specific Controller Features
In addition to regulating output voltage, the targeted application requires over voltage
protection and pulsed battery discharge. The first, over voltage protection, is critical
due to its necessity to meet safety regulations. The second, pulsed battery discharge, as
discussed before allows implementation of pulsed current charging that extend battery
lifespan.
4.5.1 Over Voltage Protection
Over voltage protection is a necessity in any battery charging applications, as the over-
voltage may result in the battery exploding [29]. To deal with this issue, a new state was
introduced into the controller FSM shown in Chapter 3. This state, named the critical
voltage response state, rapidly decreases the output current once the output voltage
exceeds a critical threshold. A revised FSM structure including over voltage protection
and reverse current pulsing can be seen in Figure 4.10. Transitioning to the critical
voltage response state is only necessary from the current pulsing state, as operation in
44
Figure 4.10: Revised FSM Controller for pulsed battery charging
different states do not risk over-charging the battery. After tapering the output current,
the converter re-enters the pre-charge mode. The controller then proceeds into the current
maintenance state when the desired current is reached and awaits the next pulsing signal.
4.5.2 Reverse Current
Allowing the battery to discharge with a reverse current during pulsed charging has
been shown to improve charge time by increasing the maximum and average current the
battery can safely accept [30]. To achieve this, we can provide the battery a discharge
path immediately following the pulsing of the output or periodically throughout the
charging procedure. Here we can exploit the symmetry of the USC. After the pulse has
45
Figure 4.11: Battery discharge switching configuration
ended, Q9, Q10 and Q12 are briefly used to discharge the battery by connecting it to
ground through the inductor. A diagram of the equivalent circuit can be seen in Figure
4.11. By adjusting the duration of this switching configuration we can tailor the current
discharge to the desired level. Following battery discharge, the converter returns to the
current maintenance state, adjusting the inductor current as necessary and awaiting the
next pulsing signal.
46
4.6 Conclusion
A novel solution allowing the implementation of various pulse charging algorithms is
introduced. It employs a topology consisting of a 3LSCL and USC as well as a com-
plementary controller. Topology selection and optimization process is discussed. The
control logic of the over voltage protection and battery discharge modes are discussed.
The integration of these control functionalities into the existing control architecture is
explained and the revised structure is presented as the final system controller.
47
Chapter 5
Practical Implementation
5.1 Introduction
Based on previous analysis, an experimental prototype was designed and fabricated. A
diagram of the physical implementation of the complete system can be seen in Figure
5.1. The components selected to realize the 3L-SCL and the USC are listed in Table 5.1.
Note that the devices selected to realize Q1 to Q6 were chosen such that their Ron and
Coss values were as close as possible to the optimized values derived in Section 4.4. The
operating conditions of the full converter system are shown in Table 5.2. In the following
section, experimental results for the individual stages are presented.
Three Level Switched Capacitor LadderParameter ComponentC1−3,f ly1,2 C3216X7S1A226M160AC
Gate Driver LTC4440Q1 FDMS7672ASQ2 FDMS8558SDC
Q3, Q5 BSC009NE2LS5Q4, Q6 BSC010NE2LSATMA1
48
Figure 5.1: Fabricated PCB for design realization
49
Universal Symmetric ConverterParameter ComponentQ7−14 CSD16411Q3L XEL5050681ME
Gate Driver LTC4440Analog-to-Digital Converter AD9220Digital-to-Analog Converter AD9760
FPGA Altera Cyclone II
Table 5.1: Components selected for design implementation - USC
5.2 Experimental Results
5.2.1 Three Level Switched Capacitor Ladder
As noted in Section 4.4, the 3L-SCL was designed for fixed 3-to-1 step down ratio from the
USB-PD input to the USC input. Individual testing of the 3L-SCL stage was performed,
to verify the accuracy of our optimization algorithm. With D fixed at 0.5, three operating
variables were tuned to attain maximum efficiency; the input voltage, the switching
deadtime and the switching frequency. Table 5.2 displays the range over which each
of the values was swept ahd the results are shown in Figure 5.2a-5.2c. We see that
as the input voltage increases, the converter efficiency tends to increase for the same
output current. This behavior matches our expectation; as the input voltage rises for a
given output current, the converter requires a smaller input current. As a result, there
are fewer conduction losses associated with charge being transferred between capacitors.
Thus for best efficiency we should operate the converter with the maximum available
input voltage. For USB PD this is a 20 V input voltage.
Sweeping the switching frequency across the specified range in 100 kHz intervals,
we find that the highest efficiency operating point resides between 300 kHz and 400 kHz.
We see that the frequency drops consistently before and after this frequency range, leading
to the conclusion that this is the optimal operating point. Note that in our design for
the 3L-SCL presented in Section 4.4. The optimized switching frequency was determined
50
Three Level Switched Capacitor LadderParameter Value
fsw 100 kHz - 1 MHzVin 12 V - 20 V
tdeadtime 60 ns - 100 nsVout 3.7 VDuty 50%
Universal Symmetric Converter (Open Loop)Parameter Value
Vin 20 Vfsw 1 MHz - 2 MHzVout 3.7 V
tdeadtime 10 - 100 ns
Universal Symmetric Converter (Closed Loop)Iout 0 - 30 Afpulse Up to 50 kHzvout 3.6 V
Battery LG INR18650HG2
Table 5.2: Converter operating conditions
to be 1.4396 MHz. The significant difference between the simulated optimal switching
frequency and the actual suggests that our model has a tendency to underestimate the
switching losses in the converter. This is most likely due to parasitics introduced by PCB
and discrete implementation. Finally, a sweep of the converter deadtime shows us that
the best performance is achieved with a deadtime of approximately 80 ns. As we increase
the deadtime, the amount of trickle charge lost to capacitor leakage current increases,
resulting in a loss of efficiency. However, reducing the deadtime too much results in
increased losses due to shoot-through currents. This adverse effect was observed as the
deadtime was dropped to 40 ns, resulting in significantly lower efficiency. After the
initial prototype, a second iteration was made. Efficiency testing was repeated on the
revised prototype with the operating conditions matching the optimal values found by
the previous prototype. The revised results can be seen in Figure 5.2d. As can be seen,
the 3L-SCL acts as a power dense, high efficiency 3-to-1 step down converter for output
currents up to about 9 A. Thus, performance of 3L-SCL as a 3-to-1 as a high efficiency
DC transformer is verified.
51
(a) Converter Efficiency vs. Vin (b) Converter Efficiency vs. fsw
(c) Converter Efficiency vs. tdeadtime (d) Converter Efficiency vs. Iout
Figure 5.2: Efficiency plots for the 3L-SCL
5.2.2 Universal Symmetric Converter (USC)
The block diagram of the USC and its controller can be seen in Figure 5.3. Before
implementing the digital controller, the open loop operation of the USC was confirmed.
Figure 5.4b shows the operation of the USC as a standard buck converter, with the
operating conditions listed in Table 5.2. A graph showing the efficiency results for the
buck mode can be seen in Figure 5.4a. Having confirmed that the USC can operate
in open loop as expected, we can verify the functionality of the proposed controller.
Flexibility of the USC architecture and digital controller allows parameters such as output
current pulse length and magnitude to be varied over a wide range. In some works, such
as in [15], the controller incorporates dedicated logic to determine when it should be
sending pulses to the battery by estimating its equivalent impedance and state of charge
52
Figure 5.3: Implemented topology and controller
(SoC). Note that we do not attempt to replicate this behavior but rather create a system
that can supply the desired current pulses.
5.2.2.1 Pre-charge State
The first step in this controller is the pre-charge state, which ramps up USC’s inductor
to desired current value. The current reference is set by a 10-bit value sent to a Digital-
to-Analog Converter (DAC). The inductor current is sensed via a small array of parallel
sense resistors placed in the conduction path immediately following the inductor. This
sensed voltage is filtered so that the DC value is extracted and compared to the voltage
53
(a) USC Open Loop efficiency in buck mode opera-tion
(b) CCM buck operation of the USC; Ch4: Iout
Figure 5.4: Open Loop buck mode operation and efficiency
produced by the DAC via comparator. The designed controller employs peak detection
for realization of the pre-charge state. Figure 5.5a. Shows the operation of the USC in
the pre-charge state. The state transition is labeled with the digital signals D0 to D2
going from 001 to 010.
5.2.2.2 Current Maintenance State
The current maintenance mode was implemented using constant on time (ton) valley
mode control. In this control method, valley detection is used to ensure the inductor
current does not drop below a selected reference value. For the detection, a DAC and
an additional comparator are used. When the valley comparator detects a valley, the
converter switching state is altered such that the inductor is being charged for a fixed
time interval denoted as ton after which the inductor is once again left to dissipate en-
ergy. Constant ton valley mode control is a variable frequency control method, with the
frequency being determined by the inductor voltage during each of the switching states
and their durations. One of the benefits of constant ton valley mode control is that the
ton parameter provides us with control of the output current ripple. Since the switching
sequences used to deliver current to the output are the same as that of a buck con-
54
(a) Pre-charge state; D0−2 show the state transition,Ch2 shows IL and D4 shows the peak detect signal
(b) Current maintenance; Ch1: valley detect signal(active low), Ch3: IL, D0−4 gating signals
(c) Current maintenance, zoomed in; Ch1: valleydetect signal (active low), Ch3: IL, D0−4 gating sig-nals
(d) Current maintenance, zoomed in; Ch1: valleydetect signal (active low), Ch3: IL, D0−4 gating sig-nals
(e) Current maintenance equivalent circuit phase 1 (f) Current maintenance equivalent circuit phase 2
Figure 5.5: Converter pre-charge and current maintenance states
55
verter, the output current ripple is the same as the inductor current ripple which we are
regulating.
The degree of control afforded by this technique depends on the specifics of
the implementation. In our case, ton can be adjusted in 3.33 ns increments affording
us relatively stringent control of the output current ripple. Current maintenance mode
can be seen in Figures 5.5b-5.5d. Testing higher currents presented another practical
challenge for the chosen implementation. As previously discussed, the ton parameter
is used to set the current ripple and consequently influences the switching frequency.
The swapping between switching states relies on the flipping of the comparator signal.
However, when the reference and sensed values are very close, the superposition of an
interfering noise signal can result in the comparator signal toggling rapidly back and
forth. Since this may cause instability in the pulsing state, we implement a short blanking
period after the detection of a current valley to prevent the comparator from triggering
multiple times in rapid succession. This stabilizes the current regulation while creating
a functional relationship between ton and the comparator blanking time tblank. Since the
inductor is only ever charging for a duration of ton during a switching cycle, we must
ensure that tblank never exceeds ton, otherwise the inductor current will decrease cycle to
cycle due to inductor volt second imbalance. A practical way to think of this is that the
need for a blanking period after valley detection effectively puts a cap on how small we
can make the current ripple. This relationship makes it such that ton and tblank should
be adjusted simultaneously when deciding the operating conditions of the circuit.
5.2.2.3 Current Pulsing State
The pulsing, critical voltage response and reverse current modes of operation are all
triggered by external signals. For the purpose of our implementation, these signals were
generated through the FPGA of Figure 5.3. The pulsing state is simply activated by a one
bit signal that denotes that the inductor current should be sent to the output. Therefore
the inductor current dictates the output current waveform. To verify the capabilities of
56
Figure 5.6: Lithium battery AC impedance
the prototype, the system was tested with varying output currents, pulsing frequency,
and pulse duration. Of a particular interest was the level of slew rate the output current
pulse can achieve as this will dictate the maximum pulsing frequency. The slew rate
is limited by the resonant tank at the output of the converter formed by the battery’s
and PCB’s parasitics. A model of the battery’s equivalent AC impedance showing this
resonant tank can be seen in Figure 5.6. Figures 5.7a to 5.7d show the pulsing mode
being tested with varying current amplitudes and pulsing frequencies. The slew rate of
the output current is shown to increase with the amplitude of the output current pulse.
Thus we achieve the highest output current slew rate for output current pulses of 30 A.
The rising current slew rate is found to be approximately 12 A/µs whereas the falling
slew rate is roughly 18.4 A/µs.
As mentioned in subsection 4.2, it is important to achieve high slew rate and
high frequency. The pulsing frequency was gradually increased while maintaining a square
wave appearance. The pulses maintain a primarily square wave appearance until about
50 kHz. At this point, we can see that the slew rate is no longer sufficient to achieve
the desired square waveshape. If we wish to evaluate the absolute maximum pulsing
frequency, we can consider the case where the output pulse is merely a triangular wave.
In this case, the maximum pulsing frequency can be calculated by using three factors: the
57
rising slew rate, the falling slew rate and the reverse pulse duration. Testing has revealed
that the ringing causing negative current seen in Figure 5.7a and 5.7b is unavoidable for
pulsed charging methods. This ringing is caused by the resonant tank at the output of
the converter, created by the parasitic inductance and capacitance originating from the
battery and the PCB traces. From Figure 5.7b and 5.7d we can see that the duration of
the reverse current pulse is independent of the pulsing frequency. The duration is seen
to be approximately 4µs. With this piece of information we can determine the maximum
pulsing frequency as:
fmax = (IpulseSRup
+IreverseSRdown
+ treversepulse)−1
Which results in a theoretical maximum switching frequency of approximately
113.1 kHz. To the best of our knowledge, this frequency is an order of magnitude higher
than previously proposed solutions. Recall that due to the inductor current already
storing the energy necessary to provide the desired output current, the slew rate is
determined by the speed of transistors Q13 and Q14 and the circuit parasitics. Thus,
the limitation in our prototype is set by the turn on time of these transistors and our
PCB layout.
5.2.2.4 Over Voltage Protection
The importance of voltage protection was described in Section 4.4, the critical voltage
response of the controller can be seen in Figure 5.8a. Voltage is sensed at the converter
output and is filtered for comparison. The sensed voltage is converted to a 12-bit value
by an analog-to-digital converter (ADC) and is compared to a reference selected by the
designer. Exceeding this value results in a rapid decrease in the output current until it
reaches 0 A. For this specific design, it was desired to have controlled slew rate during this
mode as well. After the pulse signal ends, the converter re-enters the pre-charge mode to
re-establish the desired inductor current. The current is ramped down by reducing the
58
(a) Low current pulse; Ch1: valley detect signal,Ch3: IL, Ch4: Iout, D0−4 gating signals
(b) Max current pulse; Ch2: valley detect signal,Ch3: IL, Ch4: Iout, D0−4 gating signals
(c) Low frequency pulsing (100 Hz); Ch1: valley de-tect signal, Ch4: Iout, D0−4 gating signals
(d) Max frequency pulsing (50 kHz); Ch2: valley de-tect signal, Ch3: IL, Ch4: Iout, D0−4 gating signals
(e) USC Pulsing equivalent circuit state 1 (f) USC Pulsing equivalent circuit state 2
Figure 5.7: Converter pulsing operation
59
(a) Critical voltage response; Ch2: IL, D0−3 statetransition, D4 something
(b) Reverse current discharge; Ch3: IL, Ch4: Iout;100 mV/A, D0−7 gating signals
Figure 5.8: Converter over voltage and reverse current operation
10-bit current reference with each clock cycle. This allows us to reduce the current very
quickly. In Figure 5.8a. we can see the current being reduced from 5 A to 0 A within 50
µs. The speed of this current reduction can be adjusted by tuning how often the current
reference is reduced. The slew rate of the inductor current is −Vo/L for the duration
of the current dissipation, thus the output current cannot decrease any faster than this.
It should be noted that it is possible to put yet another level of over voltage protection
with immediate shut down of the current.
5.2.2.5 Reverse Current
The reverse current mode of operation allows the converter to periodically discharge the
battery with a high current, the benefits of which were discussed in prior sections. Due
to the reverse current caused by the resonant network at the output of the converter,
the explicit discharging of the battery may not be necessary with every pulsing cycle.
However, the implementation of a separate discharge mode allows us to discharge with a
much larger current, which can be vital to achieving the desired depolarization effect of
the battery [30]. In Figure 5.8b, we see the battery being discharged through the inductor,
60
capitalizing on the maintained inductor current to create a large, short discharge. Note
that as the current probe is set to detect 100 mV/A the reverse current pulse shown in
Figure 5.8b has a magnitude of approximately 30 A.
Figure 5.9: 25 A Current Pulse to 25 A discharge; Ch 1: valley detection, Ch 3: IL, Ch4: Iout, D0−7 gating signals
The influence of the resonant tank is visible again in the small positive current
that manifests after the discharge period has concluded. If required one could employ a
controlled discharge period directly after a positive pulse. The benefit here would be the
increased slew rate realized during the pulse falling edge to achieve a more square like
reverse current pulse. An example of such a transition can be seen in Figure 5.9 where
the current changes from a roughly +25 A pulse to -25 A (discharge). In the independent
discharge mode we facilitated the discharge by simply connecting the battery to ground
through the inductor. While this allows for the fastest discharge, it will also cause the
inductor current to increase over the duration of the discharge as the inductor voltage
61
is positive throughout the duration. This is not a large concern in the independent dis-
charge mode as the discharge pulses are occurring outside a pulsing sequence. However,
if we chain the two pulsing functionalities the stability of the inductor current becomes
important. Having the inductor current increase during the discharge phase would cause
instability in the output current pulse values if the converter is operating at maximum
frequency, with pulses occurring in immediate succession. To this end, we use the combi-
nation of switching between Q12 and Q11 in 5.3 to maintain the inductor current during
discharge pulses. The gating signals of these switches are labeled as D5 and D6 in Figure
5.9. By allowing the implementation of both discharge methods, the system allows the
user to employ the more appropriate one for the given application.
5.3 Conclusion
A prototype of the proposed solution was fabricated and the feasibility of the controller
verified. Practical limitations of the converter with respect to current amplitude, pulsing
frequency, and pulse duration have been explored for the chosen implementation. Limits
associated with the practical implementation of the converter including the lower limit on
the enforceable current ripple and the maximum realizable current slew rate are explained
and discussed. Flexibility of the design including the ability to tune the output current
ripple and the speed of current reduction for the critical voltage response are highlighted.
The proposed solution is shown to offer greater flexibility while achieving higher slew
rates, greater pulsing frequencies and greater efficiency at the tested power levels than
current solutions.
62
Chapter 6
Conclusion
This thesis introduces a novel flexible topology and an associated controller to operate it
as a pulsating power supply. Compared to the state of the art solutions, it offers greater
flexibility, higher pulsing frequency, greater current slew rate and improved efficiency.
The operation of the USC is described in detail, including its flexibility in producing
multiple different conversion ratios. A design guide is given for realizing the USC with
implementable switches based on the functionality required. An example is provided,
showing how the given guidelines can create more flexible or denser solutions than those
that are currently available. In particular the methodology was used to design a novel,
SMPS solution for pulsed battery charging from a USB C input source. A two stage
solution featuring the USC as a current shaping converter with a refined controller is
examined. A three level switched capacitor ladder was used for stepping down the input.
The selection method for the first stage is explained, including optimization procedures
to compare various designs and select components for most efficient performance. The
revised control structure of the USC was explained. A discrete prototype was built
confirming the feasibility of the proposed solution. Implementation limitations of the
prototype were discussed. The prototype demonstrated the USC’s feasibility as a solution
for pulsed current battery charging using a SMPS, allowing for pulsing with varying
frequencies, durations and amplitudes. Overall, the presented converter figures to be a
63
more efficient solution for pulse charging applications that are currently employing linear
solutions.
6.0.1 Future Work
Implementation adjustments can be made to compare the benefits of different control
methods for current regulation. The constant ton valley mode control could be replaced
with a constant toff peak mode control to provide additional over-current protection.
Similarly, peak-valley mode control could be implemented to see if greater control of the
current ripple could be achieved and whether the increased control complexity would be
worthwhile. For the USC topology itself, more research could be done to investigate the
benefits and flexibility offered by the symmetry of the topology and in which applications
it may prove advantageous over conventional solutions. Finally, the possibility of creating
an integrated solution for the USC may provide a dense and efficient option for a universal
converter capable of realizing the four fundamental conversion ratios.
64
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