bdd-based topology optimization for low-power dtig finfet...

Research ArticleBDD-Based Topology Optimization for Low-Power DTIGFinFET Circuits

Haiyan Ni Jianping Hu Xuqiang Zhang and Haotian Zhu

Faculty of Information Science and Technology Ningbo University Ningbo 315211 China

Correspondence should be addressed to Haiyan Ni nihaiyannbueducn

Received 1 February 2019 Accepted 12 June 2019 Published 18 July 2019

Academic Editor Gerard Ghibaudo

Copyright copy 2019 Haiyan Ni et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation The proposed method isoptimized for dual-threshold independent-gate (DTIG) FinFET circuits The algorithm of the BDD-based topology optimizationis stated in detail Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fedto mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates Some MCNC benchmarkcircuits are tested under the proposed synthesismethod by comparing with ABCDC toolsThe simulations show that the proposedsynthesis method can obtain performance improvement for DTIG FinFET circuits

1 Introduction

As a 3D transistor FinFET is more efficient than the tradi-tional devices because it can suppress short channel effect(SCE) and drain induced barrier lowering (DIBL) [1ndash6]FinFET can operate in common-gate (CG) mode whosetwo gates are tied together naturally and can be used like atraditional single-gate device with improved performancesor in independent-gate (IG) mode whose two gates can beused as two separated single-gate devices in parallel or serieson special conditions [2]

Todayrsquos VLSI is usually designed by ldquostandard cellrdquomethod [7] Among the design flow synthesis is an importantprocess which transforms the high level design to low levelnetlists form composed by standard cells Currently standardcell libraries are basically built on the basis of CMOS or CGFinFETdevicesThe synthesis tools such as commercial toolslike Synopsys Design Compiler (DC) public-domain toolslike ABC [8] and synthesis algorithms like factorization-based methods usually utilizing these single-gate standardcell libraries to optimize the circuit topology Howeveraccording to our research DTIG FinFET-based circuits haveexcellent performances and can be used in modern VLSIcircuits [9ndash11] So it has an emerging need to develop acomprehensive method based on DTIG FinFETs

As a powerful representation of logic function binarydecision diagram (BDD) is widely used in computer scienceto solve graph algorithms and matrix-operation even arti-ficial intelligence problems It also can be applied in VLSIdesign to construct the topology of the circuits and detectand optimize the circuits [12ndash14] The efficiency of the BDDis always determined by the variable order of the functionsSince the variable ordering problem is a NP-complete [15 16]there are many approximation heuristic methods have beenfound to efficiently solve this problem [12 17ndash19]

The paper described a circuit topology optimizationmethod based on BDD technology to compose the DTIG FinFET circuits by using the predefined DTIG FinFETbasic logic cells It is organized as follows In Section 2 weintroduce the predefined DTIG FinFET logic gates brieflyand in Section 3 we state some theorems and an algorithmof feature modules extraction in BDD graph The mappingalgorithm is also included in Section 3 And in Section 4we realize the algorithms and verify the effectiveness ofthe method by testing the MCNC benchmarks Finally weconclude in Section 5

2 DTIG FinFET Cell Library

Compared with single-gate devices such as CMOS or CGFinFET DTIG FinFET can design more flexible circuits by

HindawiActive and Passive Electronic ComponentsVolume 2019 Article ID 8292653 9 pageshttpsdoiorg10115520198292653

2 Active and Passive Electronic Components

Table 1 Performance comparison of some example cells

Cells TCount Delay (ps) Power (120583W)CG IG CG IG CG IG

NAND 4 2 56 51 118 55NOR 4 2 55 47 118 30NAND3 6 4 92 97 85 49AOI 6 4 77 73 156 59OAI 6 4 66 64 168 95XOR 10 8 40 34 543 317

A

A

B

B

B

A

A

B

A B A B

L-Vtℎ

H-Vtℎ

(a) NAND

A

A

B

BA+B

A

A B

BA+B

L-Vtℎ

H-Vtℎ

(b) NOR

Figure 1 The basic logic cells realized by the CG FinFETs and DTIG FinFETs respectively (a) NAND (b) NOR

using of the low-threshold (low-Vth) and high-threshold(high-Vth) devices [2 3 9 11 20] We have built a mini DTIGFinFET logic cells library for further using and as shown inFigure 1 are two examples and their CG comparisons TheDTIG FinFET logic cells have more compact structures thanthe CG FinFET logic cells and thus they would have moreadvantages in transistor count delay and power dissipationthan CG FinFET cells as examples shown in Table 1 All gatesin the library which are composed by low-Vth transistorsand high-Vth ones with parameters extracted from TCADsimulations have been verified by Hspice with the BSIMIMGmodel from UC Berkeley [21]

3 The Algorithms of Synthesis DTIGLogic Circuits

Firstly we give some definitions about BDD and featurestructure Next we give some theorems related to BDDsubgraph extraction and prove them Finally we describethe implementations of BDD-based extraction algorithm andmapping algorithm

31 Definitions Binary decision diagrams (BDD) is proposedby Akers [22] as a method to representation of logic functionThe methods based on BDD have been widely used in therepresentation and design of VLSI [23] For the convenienceof further discussion we introduce several definitions relatedto BDD and its subgraph extraction firstly

Definition 1 (binary decision diagram (BDD)) BDDhas beendefined in [22 24] detailed here we briefly describe someconcepts A BDD as an example shown in Figure 2(a) is arooted directed acyclic graph which is used to represent aBoolean function as

119891 = V1V4 + V1V3 + V1V4V5 + V2V3 (1)

The BDD graph can be represented in formal language asG = ⟨VE⟩ where V and E are the node set and edgeset respectively V contains two types of nodes named asnonterminal nodes (circular form in the figure) and terminalnodes (block form in the figure) Every nonterminal nodelabelled with an input variable V119894 isin 119866 ((i = 1 2 n) hastwo children low (V119894) isin 119881 and high (V119894) isin 119881 and two relativeedges else (V119894) isin 119864 and then (V119894) isin 119864 connecting to thetwo children respectively Here in this paper the else (V119894) andthen (V119894) edges are denoted as dotted line and solid line inthe figures respectively A terminal node V119894 isin 119881 has not anychild and outgoing edges and is only labelled with a value(V119894) isin 0 1

When a BDD is used to compute a logic function119891(V1 V2 Vn) we recursively compute the function fromthe root node (here assuming that it is V119894) to the terminal node0 or 1

119891 (V119894) = V119894119891 (119897119900119908 (V119894)) + V119894119891 (ℎ119894119892ℎ (V119894)) (2)

where V119894 is the complementary logic of V119894 Because theproduction of 0 and any logic is 0 we can omit the paths fromroot to 0-terminal and reserve the computations from root to1-terminal

The BDD mentioned in this paper actually refers toreduced ordered binary decision diagram (ROBDD) [25ndash27]which is a type of variant BDD with input variables speciallyordered and simplified structure with distinct nodes Thereare many algorithms to get the ROBDD from BDD byefficiently ordering the variables and removing the redundantvariables in literatures [15ndash19]

Definition 2 (feature structure) A feature structure is aspecial subgraph in a BDD 119866119904 = 119866119894 sube 119866 (119894 = 1 2 3 )

Active and Passive Electronic Components 3

(a)0 1

(b) (c) (d) (e) (f)

extractedv1

(g)

Mapped

(h)

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Mapped

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(i)

01 f

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33

3 11

3 3

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22

2

2

Figure 2 (a) A BDD example representing the Boolean logic equation (1) (b)ndash(f) its extracted BDD subgraphs (g) MUX realization directlyfrom (a) (h) the AOI and OAI cells mapped by the extracted BDD subgraphs (e) and (f) (i) the optimized result

which can be mapped to a DTIG FinFET basic logic gatesuch as ANDNAND ORNOR AOI XOR and MUX Here119866119894 is a subgraph in 119866 rooted by V119894 with its children and thedescendants

From Figure 2(a) we can extract some BDD subgraphas shown in Figures 2(b)ndash2(f) Among them subgraphs inFigures 2(c)ndash2(e) can be realized with theDTIG FinFET logicgates that are AOI OAI AND and NOR respectivelyThere-fore all these structures are feature structures For exampleFigure 2(b) is an extracted subgraph fromFigure 2(a) that canbe realized by an AOI cell and Figure 2(c) can be realized byan OAI as shown in Figure 2(h) The structure in Figure 2(f)cannot bemapped to any logic cell therefore it is not a featurestructure

On the other hand for a nonterminal node in BDD wecan always realize by a MUX cell directly [22 28] So we canmap the BDD shown in (1) to aMUX-based netlist directly asshown in Figure 2(g)

32 eorems of Extraction Algorithm

Theorem 3 For a nonterminal node V119894 of a BDD we assumethat its two children are V119909 with node function 119891(V119909) andV119910 with node function 119891(V119910) If a nonterminal node V119895 withfunction 119891(V119895) and one of its two outgoing edges are connectingto V119894 and another edge connecting to V119909 or V119910 the nodesgroup (V119894 V119895 V119909 V119910) can construct as a feature structure ofANDNANDORNOR

Proof Assuming that V119909 = ℎ119894119892ℎ(V119894) = 119897119900119908(V119895) V119910 = 119897119900119908(V119894)and V119894 = ℎ119894119892ℎ(V119895) as shown Figure 3(a)

According to Definition 1 there is a function shown in (3)and the derivations (4) and (5) from Figure 3(a)

119891 (V119895) = V119895119891 (V119909) + V119895 (V119894119891 (V119909) + V119894119891 (V119910))= 119891 (V119909) (V119894 + V119895) + 119891 (V119910) V119894V119895

(3)

= 119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895 (4)

= 119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895 (5)

From (4) and (5) we can map the BDD subgraph to oneof four feature structures of NAND AND OR and NOR asshown in Figures 3(b)ndash3(e)

Similarly the other cases satisfying the condition ofTheorem 3 will get similar results and also can be proveneasily

Theorem4 For a node group (V119894 V119909 V119910 V119895) satisfying the con-dition of eorem 3 assuming that there exists a nonterminalnode V119896 with function 119891(V119896) and V119909 is a common child of V119895and V119894 and V119910 is just a child of V119894 when one outgoing edge of V119896connects to node V119895 and the other edge connects to node V119909 thenthe nodes V119894 V119909 V119910 V119895 V119896 and their relative edges construct afeature structure of three-input ANDNANDORNOR logic

Otherwise when one outgoing edge of V119896 connects to nodeV119895 and the other edge connects to node V119894 or V119910 the nodes V119894 V119909V119910 V119895 V119896 and their relative edges construct a feature structureof three-input AOIOAI logic

Proof Firstly we consider the first case as shown in Fig-ure 4(a)


(b) (c)

(d) (e)

01

01

01

01(a)

f(x)

f(x)

f(x)

f(x)

f(x)

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j

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f(y)f(y)

f(y)

f(y)

f(y)f(j)

f(j)

f(j)f(j)

f(j)i

i

ii

ji

Figure 3 One case ofTheorem 3 and relative feature structures (a) One case of BDD subgraph (b) NAND structure (c) AND structure (d)OR structure and (e) NOR structure

(b)

01

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(c)

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x

k k

y

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i

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i

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ii

f(y)

f(y)f(y)

f(y)f(y)

f(j)

f(j)

f(j)f(j)

f(j)

f(k)

Figure 4 One case of Theorem 4 and relative feature structures (a) one case of BDD subgraph (b) AND3 (c) NAND3 (c) OR3 and (d)NOR3

Assuming that V119909 = high(V119894) = low(V119895) = low(V119896) and V119910= low(V119894) according to (2) in Definition 1 there is (6) and itsderivations as follows

119891 (V119896) = V119896V119909 + V119896119891 (V119895)= V119896119891 (V119909) + V119896 (119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895)= 119891 (V119909) (V119896 + V119894 + V119895) + 119891 (V119910) (V119896V119894V119895)

(6)

= 119891 (V119909) (V119896V119894V119895) + 119891 (V119910) (V119896V119894V119895) (7)

= 119891 (V119909) (V119896 + V119894 + V119895) + 119891 (V119910) (V119896 + V119894 + V119895) (8)

From (7) and (8) we can get the results as shown inFigures 4(b)ndash4(e)

Now we consider another case in Theorem 4 assumingthat V119895 = ℎ119894119892ℎ(V119896) V119894 = 119897119900119908(V119896) V119909 = ℎ119894119892ℎ(V119894) = 119897119900119908(V119895) =119897119900119908(V119896) and V119910 = 119897119900119908(V119894) according to (2) in Definition 1there is (9) and its derivations as follows

119891 (V119896) = V119896119891 (V119895) + V119896 (V119894119891 (V119909) + V119894119891 (V119910))= V119896 (119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895)+ V119896 (V119894119891 (V119909) + V119894119891 (V119910))= 119891 (V119909) (V119894 + V119896V119895) + 119891 (V119910) (V119894 (V119896 + V119895))

(9)

= 119891 (V119909) (V119894 + V119896V119895) + 119891 (V119910) (V119894 + V119896V119895) (10)

= 119891 (V119909) (V119894 (V119896 + V119895)) + 119891 (V119910) (V119894 (V119896 + V119895)) (11)

From (10) and (11) we can get the results of Theorem 4

Theorem 5 For two nodes V119894 V119895 in a BDD graph assume thatV119894 is the low child and the high child of V119895 at the same time if thelow child V119894 has two outgoing edges then and else connecting toV119909 and V119910 respectively while the high child V119894 has two outgoingedges then and else connecting to V119910 and V119909 respectively esubgraph including V119895 V119894 V119909 V119910 can be construct as a featurestructure of XORXNOR logic

Proof FromTheorem 5 we can show it in Figure 5According to (2) in Definition 1 we have

119891 (V119895) = V119895 (V119894119891 (V119909) + V119894119891 (V119910))+ V119895 (V119894119891 (V119909) + V119894119891 (V119910))= 119891 (V119909) (V119895V119894 + V119895V119894) + 119891 (V119910) (V119895V119894 + V119895V119894)

(12)

= 119891 (V119909) (V119895 ⊙ V119894) + 119891 (V119910) (V119895 oplus V119894) (13)

From (13) the subgraph can be constructed asXORXNOR logic as shown in Figures 5(b) and 5(c)

33 BDD-Based Node Extraction Algorithm According tothe definitions and the theorems above mentioned we havedeveloped a feature structure extraction algorithm for a givenBDDwhich contains four subroutines to finish the extractionprocedure The subroutine 1 outputs the reduced orderingform of the BDD graph from an input logic function fThe extracted BDD subgraphs of the feature structures willbe obtained through the processes from subroutines 2 to 4


Algorithm of Subroutine 1Input 119891 = 119891(V1 V2 V119894 V119895 V119899)Output G[] node set of BDD form

1 G[] larr997888 bdd init(119891)2 sum srclarr997888 bdd nodecount(G[])3 for i = 1 to n do4 for j = i to n do5 bdd swapvar(V119894 V119895)6 sum exlarr997888 bdd nodecount(G[])7 if sum ex le sum src then8 sum srclarr997888 sum ex9 else sum ex gt sum src 10 bdd swapvar(V119894 V119895)11 end if12 end for13 end for

Algorithm 1 The algorithm of subroutine 1 in the BDD-based extraction algorithm

(a) (c)(b)

01

01

f(x)

f(x)f(x)

x y

jjj

iiii

f(y)f(y)

f(y)

f(j)

f(k)f(k)

Figure 5 The case inTheorem 5 (a) BDD subgraph (b) XOR and (c) XNOR

successively In each subroutine some parts of the BDD aremarked as the different feature structures The order of thealgorithm flow is carefully arranged As shown in Table 1in the proposed DTIG FinFET cell library NANDNORcells can reduce the number of transistors more than thesingle-gate gates AOIOAINAND3NOR3 cells the secondand XOR cells the least The extraction order of the featurestructure is in this order to get the most improvement Whenthe whole algorithm procedure is finished we will obtain theoptimized BDD and the feature structures which can be fedto the mapping algorithm to further process

In the algorithm of the subroutine 1 as shown in Algo-rithm 1 we generate an initial reduced ordered BDD fromthe input logic function by using a sorting algorithm likethe traditional bubble sort algorithm When subroutine 1 isfinished an optimal ordered BDD form will be obtained

The subroutine 2 as shown in Algorithm 2 searches fora father V119895 of each node V119894 in the optimal ordered BDD fromsubroutine 1

We mark V119895 as a father of V119894 and V119909 V119910 as two childrenof V119894 If the node group (V119894 V119895 V119909 V119910) meets the conditionof Theorem 3 ie both V119894 and V119909 (or V119910) are the children ofV119895 and we extract the subgraph containing the nodes V119895 V119894V119909 V119910 and their relative edges and then mark the subgraph asa feature structure of ORNOR (119891119874119877minus119873119874119877) or ANDNAND(119891119860119873119863minus119873119860119873119863) When this subroutine is finished all featurestructures of ORNOR or ANDNAND are extracted andstored in the sets Gso and Gsa respectively

The algorithm of the subroutine 3 as shown in Algorithm3 searches for a node group (V119894 V119895 V119896 V119909 V119910) whichmeets thecondition of Theorem 4 First we check each subgraph in theresult set Gsa from subroutine 2 and the origin BDD graphset119866 from subroutine 1 if a node V119896 exists in119866which satisfiesthe cases ofTheorem 4 we extract a new subgraph containingthe node V119896 and the corresponding subgraph in the set Gsaand their edges and we mark the new subgraph as a newfeature structure of AND3NAND3 or AOI Then we storethis feature structure into the set Gsa3 for AND3NAND3or set Gsaoi for AOI respectively Finally the correspondingsubgraph in the setGsa should be deleted because it has beencovered by the new generated feature structure

According to Theorem 5 algorithm of the subroutine 4as shown in Algorithm 4 searches for the special groups ofnodes in the optimal ordered BDD from subroutine 1 andthen constructs them as new feature structures If the nodesof a group satisfy the conditions of Theorem 5 (a) a node(denoted as V119896) is the same father of the other two nodes(denoted as V119894 and V119895) of the same variable (b) there exist twonodes that are the same children of V119894 and V119895 and (c) 119897119900119908(V119895)= ℎ119894119892ℎ(V119894) and 119897119900119908(V119894) = ℎ119894119892ℎ(V119895) then we extract the groupand their edges as a feature structure of XOR logic and thenstore it into set Gsxor

When these subroutines are all finished the proposedextraction algorithm generates the optimal ordered BDDform of a given logic function and obtains all the featurestructures in the BDD


Algorithm of subroutine2Input G[] node set from subroutine 1Output Gsa[] set of ANDNAND2 sub-graphOutput Gso[] set of ORNOR sub-graph

1 for each vi in G[] do2 (V119909 V119910) larr997888 children(vi)3 for each vj in G[] do4 if low(V119895) = V119894 then5 If high(vj) = vx OR high(vj) = vy then6 fOR-NOR larr997888 fOR-NORmark(V119894 V119894 V119909 V119910E(V119895 V119894 V119909 V119910))7 Gso[k] larr997888 fOR-NOR8 end if9 else if high(V119895) = V119894 then10 if low(V119895) = vx OR low(V119895) = V119910 then11 fAND-NAND larr997888mark(V119894 V119894 V119909 V119910E(V119895 V119894 V119909 V119910))12 Gsa[] larr997888 fAND-NAND13 end if14 end if15 end for16 end for


Algorithm of Subroutine3Input Gsa set of ANDNAND2 sub-graph from subroutine2Input G[] node set of BDD from subroutine 1Output Gsaoi[] set of AOIOAI sub-graphOutput Gsand3[] set of ANDNAND31 sub-graph

1 for each gs in Gsa do2 vj larr997888root(gs)3 for each vk in BDD do4 if low(vk)=vj OR high(vk)=vj then5 if vk satisfyTheorem 4 case 1 then6 fANDNAND31 larr997888 mark(V119894 V119895 V119896 V119909 V119910E(V119894 V119895 V119896 V119909 V119910))10 Gsa3[] larr997888 fANDNAND3111 else if vk satifyTheorem 4 case2 then12 fAOIOAI larr997888 mark(V119894 V119895 V119896 V119909 V119910E(V119894 V119895 V119896 V119909 V119910))13 Gsaoi[] larr997888 fAOIOAI14 end if15 end if16 end for17 end for


34 e Mapping Algorithm The extraction algorithmsdescribed above only aims at simplifying Boolean functionsIn the next logic synthesis steps we need to replace thelogic gates with physical cells in the cell library by usinga mapping algorithm We propose the feature structuremapping algorithm with four steps In step 1 after readingthe BDD and its subgraphs from the extraction algorithm weexclude the redundant or covered subgraphs Then in step2 we map the source BDD to a circuit composed of MUXscompletely and map the feature structures to the IG FinFETlogic gates In step 3 we give the final optimized circuit by

replacing some MUXs subcircuits with logic cells Step 1 tostep 3 are shown as examples in Figures 2(a)ndash2(h) and theresult is as shown in Figure 2(i)

4 Algorithm Implementation

The synthesis algorithms including extraction and mappingare both implemented in MATLAB platform and for com-parison of the circuit optimization effectiveness the ABC andDC synthesis tools are also applied to the same circuits For afair comparison all methods use the same DTIG FinFET cell


Algorithm of Subroutine 41 Input G[] node set of source BDD from subroutine 12 Output Gsxor[] set of XORNXOR sub-graph3 for each vk in G[] do4 for each vi in G[] do5 for each vj in G[] do6 if low(vk) = vi AND high(vk) = vj OR

high(vk) = vi AND low(vk) = vj then7 if value(vj) = value(vi) then8 if low(vi) = high(vj) AND high(vi) = low(vj) then9 (vxvy)larr997888 children(vivj)10 fXORNXOR larr997888 mark(V119894 V119895 V119896 V119909 V119910E(V119894 V119895 V119896 V119909 V119910))11 Gsxor[]larr997888fXORNXOR12 end if13 end if14 end if15 end for16 end for17 end for


librarywe built in Section 2 Finally all the circuits fromABCDC and the proposed method are simulated by using Hspicewith the BSIMIMG model from UC Berkeley [21] Figure 6presents the simulation results of the MCNC benchmarkcircuits

As shown in Figure 6(a) for almost all tested circuits thecount of transistors in the circuit optimized by this work isthe least among the comparisons Therefore in most casesthe proposed method can get the most effective area sincethe area occupation is determined by the number of thetransistors

The average power dissipation can be expressed by

119875119886V = 119873119875119886V1 = 119873(119901119897119900119908119875119897119900119908 + 119901ℎ119894119892ℎ119875ℎ119894119892ℎ) (14)

where 119875119886V is the average power of a circuitN is the transistorcount in a circuit Pav1 is the average power of one transistorPlow and Phigh are the average power of one low-Vth andhigh-Vth IG FinFET respectively and plow and phigh are thepossibility of low-Vth and high-Vth IG FinFET in a circuitrespectively

From (14) if the possibility of transistors in kinds ofcircuits is close to each other the average power of a circuitis determined by the count of transistor in a circuit FromFigure 6(b) we can see the trend of the power dissipationis close to the transistor count trend shown in Figure 6 andstill almost all the circuits synthesized by this work have theleast power dissipation and the fact fits the prediction of (14)very well The delay analysis is more complicated than powerdissipation The maximum delay of a circuit depends on thecritical path The more transistors on the critical path arethe greater delay should be For a DTIG FinFET circuit thehigh-threshold device has more delay because it has low on-current which further reduces the switch speed and increasesthe delay So as shown in Figure 6(c) we find that the circuit

synthesized by this work has no obvious advantage in termsof delay

The power delay product (PDP) can evaluate a circuitmore comprehensively because it considers both delay andpower consumption As seen from Figure 6(d) comparedwith ABC and DC all of the circuits synthesized by this workhave obvious advantage of PDP

5 Conclusion

In this paper we have presented a BDD-based synthesismethod to optimize DTIG FinFET circuits We search theBDD graph of an input logic to find feature structures andmap them to DTIG FinFET basic logic gates The algorithmsare implemented in MATLAB and compared with ABC andDC by simulation of the MCNC benchmark circuits Theresult shows that the proposed method can significantlyimprove the performances of DTIG FinFET circuits in areaoccupation power consumption and PDP

Data Availability

All data used to support the study had been included in thepaper and can be accessed freely

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

This research is based upon work supported by NationalNatural Science Foundation of China under Grant No


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Figure 6 Comparison between the simulation results of ABC DC and this work

61671259 and Zhejiang Provincial Natural Science Founda-tion (No LY19F010005)The study is funded byNational Nat-ural Science Foundation of China [61671259] and ZhejiangProvincial Natural Science Foundation [LY19F010005]

References

[1] C Shin ldquoState-of-the-art silicon device miniaturization tech-nology and its challengesrdquo IEICE Electronics Express vol 11 no10 Article ID 20142005 2014

[2] P Mishra A Muttreja and N K Jha ldquoFinFETcircuit designrdquoNanoelectronic Circuit Design pp 23ndash54 2011

[3] M Rostami and K Mohanram ldquoDual-Vth independent-gateFinFETs for low power logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol30 no 3 pp 337ndash349 2011

[4] S Chaudhuri and N K Jha ldquoFinFET logic circuit optimizationwith different FinFET styles Lower power possible at highersupply voltagerdquo in Proceedings of the International Conference

on Vlsi Design and 2014 International Conference on EmbeddedSystems pp 476ndash482 2014

[5] S Tawfik and V Kursun ldquoMulti-Threshold Voltage FinFETSequential Circuitsrdquo IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems vol 19 no 1 pp 151ndash156 2011

[6] M Imani S Patil and T S Rosing ldquoHierarchical design ofrobust and low data dependent FinFET based SRAM arrayrdquoin Proceedings of the IEEEACM International Symposium onNanoscale Architectures pp 63ndash68 2015

[7] T Wang X Cui K Liao et al ldquoLow power high performanceFinFET standard cells based onmixed back biasing technologyrdquoIEICETransactions onElectronics vol E99C no 8 pp 974ndash9832016

[8] R Brayton and A Mishchenko ldquoABC An academic industrial-strength verification toolrdquo in Proceedings of the Computer AidedVerification International Conference vol 6174 pp 24ndash40Edinburgh Uk CAV 2010

[9] X Zhang J Hu and X Luo ldquoOptimization of dual-thresholdindependent-gate FinFETs for compact low power logic cir-cuitsrdquo in Proceedings of the 16th IEEE International Conference


on Nanotechnology - IEEE NANO 2016 pp 529ndash532 SendaiJapan August 2016

[10] H Yang J Hu and H Zhu ldquoNovel SRAM cells using dual-threshold independent-gate FinFETsrdquo in Proceedings of the 17thIEEE International Conference on Nanotechnology NANO 2017pp 358-359 Pittsburgh Pa USA July 2017

[11] H Ni J Hu H Yang and H Zhu ldquoComprehensive optimiza-tion of dual threshold independent-gate FinFET and SRAMcellsrdquo Active and Passive Electronic Components vol 2018Article ID 4512924 10 pages 2018

[12] W Lenders and C Baier ldquoGenetic algorithms for the variableordering problem of binary decision diagramsrdquo in Proceedingsof the International Conference on Foundations of GeneticAlgorithms pp 1ndash20 2005

[13] U S Costa A M Moreira D Dharbe C Universitrio and LNova ldquoAdvances in bdd reduction using parallel genetic algo-rithmsrdquo in Proceedings of the IEEE 10th International Workshopon Logic amp Synthesis (IWLS2001) pp 84ndash89 2001

[14] P Porwik K Wrobel and P Zaczkowski ldquoSome practicalremarks about Binary Decision Diagram size reductionrdquo IEICEElectronics Express vol 3 no 3 pp 51ndash57 2006

[15] S Tani K Hamaguchi and S Yajima ldquoThe complexity of theoptimal variable ordering problems of shared binary decisiondiagramsrdquo in Proceedings of the in Algorithms amp ComputationInternational Symposium ISAAC 93 Hong Kong December1993

[16] B Bollig and I Wegener ldquoImproving the variable ordering ofOBDDs is NP-completerdquo IEEE Transactions on Computers vol45 no 9 pp 993ndash1002

[17] H Fujii G Ootomo and C Hori ldquoInterleaving based vari-able ordering methods for ordered binary decision diagramsrdquoin Proceedings of the IEEEACM International Conference onComputer-aided Design 1993

[18] O Brudaru C Rotaru and I Furdu ldquoStatic segregative geneticalgorithm for optimizing variable ordering of ROBDDsrdquo inProceedings of the International Symposium on Symbolic ampNumeric Algorithms for Scientific Computing 2011

[19] M Takapoo and M B Ghaznavi-Ghoushchi ldquoIDGBDD Thenovel use of ID3 to improve genetic algorithm in BDDreorderingrdquo in Proceedings of the International Conference onElectrical Engineeringelectronics Computer Telecommunicationsamp Information Technology 2010

[20] H Zhu J Hu H Yang Y Xiong and T Yang ldquoA topologyoptimization method for low-power logic circuits with dual-threshold independent-gate FinFETsrdquo in Proceedings of the27th International Symposium on Power and Timing ModelingOptimization and Simulation PATMOS 2017 pp 1ndash6 GreeceSeptember 2017

[21] N Paydavosi S Venugopalan Y S Chauhan et alldquoBSIMmdashSPICE models enable FinFET and UTB IC designsrdquoIEEE Access vol 1 pp 201ndash215 2013

[22] S B Akers ldquoBinary decision diagramsrdquo IEEE Transactions onComputers vol 27 no 6 pp 509ndash516 1978

[23] S ichi Minato ldquoTechniques of BDDZDD brief history andrecent activityrdquo IEICE Transaction on Information and Systemsvol E96D no 7 pp 1419ndash1429 2013

[24] R Drechsler and D Sieling ldquoBinary decision diagrams intheory and practicerdquo International Journal on So13ware Tools forTechnology Transfer vol 3 no 2 pp 112ndash136 2001

[25] R E Bryant ldquoGraph-based algorithms for boolean functionmanipulationrdquo IEEE Transactions on Computers vol C-35 no8 pp 677ndash691 1986

[26] M Raseen P Chandana Prasad and A Assi ldquoAn efficientestimation of the ROBDDrsquos complexityrdquo Integration the VLSIJournal vol 39 no 3 pp 211ndash228 2006

[27] K S Brace R L Rudell and R E Bryant ldquoEfficient implemen-tation of a BDD packagerdquo in Proceedings of the 27th ACMIEEEDesign Automation Conference pp 40ndash45 June 1990

[28] J M Rabaey A P Chandrakasan and B Nikolic DigitalIntegrated Circuit-ADesign Perspective Prentice-Hall Inc 2003

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

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VLSI Design



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Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018


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wwwhindawicom Volume 2018

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Submit your manuscripts atwwwhindawicom


Table 1 Performance comparison of some example cells

Cells TCount Delay (ps) Power (120583W)CG IG CG IG CG IG

NAND 4 2 56 51 118 55NOR 4 2 55 47 118 30NAND3 6 4 92 97 85 49AOI 6 4 77 73 156 59OAI 6 4 66 64 168 95XOR 10 8 40 34 543 317

A

A

B

B

B

A

A

B

A B A B

L-Vtℎ

H-Vtℎ

(a) NAND

A

A

B

BA+B

A

A B

BA+B

L-Vtℎ

H-Vtℎ

(b) NOR

Figure 1 The basic logic cells realized by the CG FinFETs and DTIG FinFETs respectively (a) NAND (b) NOR

using of the low-threshold (low-Vth) and high-threshold(high-Vth) devices [2 3 9 11 20] We have built a mini DTIGFinFET logic cells library for further using and as shown inFigure 1 are two examples and their CG comparisons TheDTIG FinFET logic cells have more compact structures thanthe CG FinFET logic cells and thus they would have moreadvantages in transistor count delay and power dissipationthan CG FinFET cells as examples shown in Table 1 All gatesin the library which are composed by low-Vth transistorsand high-Vth ones with parameters extracted from TCADsimulations have been verified by Hspice with the BSIMIMGmodel from UC Berkeley [21]

3 The Algorithms of Synthesis DTIGLogic Circuits

Firstly we give some definitions about BDD and featurestructure Next we give some theorems related to BDDsubgraph extraction and prove them Finally we describethe implementations of BDD-based extraction algorithm andmapping algorithm

31 Definitions Binary decision diagrams (BDD) is proposedby Akers [22] as a method to representation of logic functionThe methods based on BDD have been widely used in therepresentation and design of VLSI [23] For the convenienceof further discussion we introduce several definitions relatedto BDD and its subgraph extraction firstly

Definition 1 (binary decision diagram (BDD)) BDDhas beendefined in [22 24] detailed here we briefly describe someconcepts A BDD as an example shown in Figure 2(a) is arooted directed acyclic graph which is used to represent aBoolean function as

119891 = V1V4 + V1V3 + V1V4V5 + V2V3 (1)

The BDD graph can be represented in formal language asG = ⟨VE⟩ where V and E are the node set and edgeset respectively V contains two types of nodes named asnonterminal nodes (circular form in the figure) and terminalnodes (block form in the figure) Every nonterminal nodelabelled with an input variable V119894 isin 119866 ((i = 1 2 n) hastwo children low (V119894) isin 119881 and high (V119894) isin 119881 and two relativeedges else (V119894) isin 119864 and then (V119894) isin 119864 connecting to thetwo children respectively Here in this paper the else (V119894) andthen (V119894) edges are denoted as dotted line and solid line inthe figures respectively A terminal node V119894 isin 119881 has not anychild and outgoing edges and is only labelled with a value(V119894) isin 0 1

When a BDD is used to compute a logic function119891(V1 V2 Vn) we recursively compute the function fromthe root node (here assuming that it is V119894) to the terminal node0 or 1

119891 (V119894) = V119894119891 (119897119900119908 (V119894)) + V119894119891 (ℎ119894119892ℎ (V119894)) (2)

where V119894 is the complementary logic of V119894 Because theproduction of 0 and any logic is 0 we can omit the paths fromroot to 0-terminal and reserve the computations from root to1-terminal

The BDD mentioned in this paper actually refers toreduced ordered binary decision diagram (ROBDD) [25ndash27]which is a type of variant BDD with input variables speciallyordered and simplified structure with distinct nodes Thereare many algorithms to get the ROBDD from BDD byefficiently ordering the variables and removing the redundantvariables in literatures [15ndash19]

Definition 2 (feature structure) A feature structure is aspecial subgraph in a BDD 119866119904 = 119866119894 sube 119866 (119894 = 1 2 3 )


(a)0 1

(b) (c) (d) (e) (f)

extractedv1

(g)

Mapped

(h)

f

Mapped

v2

v3

v4 v5

v4

v3

(i)

01 f

f 2

f 1replace

01

10

01 1

0

10

0

v3

0 1

v2

2

f1

f2

f

f2

v2v3

f1

v4

v3

0 1 0 1

v4

v3

v2

v5

v4

0 1 0 1

v4

v3

v5

0 v4

v3

4

4

4

4

4

33

3 11

3 3

3

5

5

5

4

22

2

2









119891 (V119895) = V119895119891 (V119909) + V119895 (V119894119891 (V119909) + V119894119891 (V119910))= 119891 (V119909) (V119894 + V119895) + 119891 (V119910) V119894V119895

(3)

= 119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895 (4)

= 119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895 (5)







(b) (c)

(d) (e)

01

01

01

01(a)

f(x)

f(x)

f(x)

f(x)

f(x)

x y

j

j j

j

f(y)f(y)

f(y)

f(y)

f(y)f(j)

f(j)

f(j)f(j)

f(j)i

i

ii

ji


(b)

01

01

01

01

(c)

(d) (e)(a)

f(x)

f(x)f(x)

f(x)f(x)

x

k k

y

j

ji

kj

i

kj

i

kj

ii

f(y)

f(y)f(y)

f(y)f(y)

f(j)

f(j)

f(j)f(j)

f(j)

f(k)




(6)

= 119891 (V119909) (V119896V119894V119895) + 119891 (V119910) (V119896V119894V119895) (7)

= 119891 (V119909) (V119896 + V119894 + V119895) + 119891 (V119910) (V119896 + V119894 + V119895) (8)




(9)

= 119891 (V119909) (V119894 + V119896V119895) + 119891 (V119910) (V119894 + V119896V119895) (10)

= 119891 (V119909) (V119894 (V119896 + V119895)) + 119891 (V119910) (V119894 (V119896 + V119895)) (11)





(12)

= 119891 (V119909) (V119895 ⊙ V119894) + 119891 (V119910) (V119895 oplus V119894) (13)







(a) (c)(b)

01

01

f(x)

f(x)f(x)

x y

jjj

iiii

f(y)f(y)

f(y)

f(j)

f(k)f(k)



























119875119886V = 119873119875119886V1 = 119873(119901119897119900119908119875119897119900119908 + 119901ℎ119894119892ℎ119875ℎ119894119892ℎ) (14)





5 Conclusion


Data Availability




Acknowledgments



MCNC circuits

0

20

40

60

80

100

120

140

ABC

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

DCThis work

Tran

sisto

r Cou

nt

(a)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

0

100

200

300

400

500

600

ABCDCThis work

MCNC circuits

Aver

age P

ower

(W

)

(b)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

Del

ay (p

s)

MCNC circuits

0

40

80

120

160

200

ABCDCThis work

(c)

PDP(

fJ)

MCNC circuits

0

20

40

60

80

100

ABCDCThis work

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

(d)



References


































RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



(a)0 1

(b) (c) (d) (e) (f)

extractedv1

(g)

Mapped

(h)

f

Mapped

v2

v3

v4 v5

v4

v3

(i)

01 f

f 2

f 1replace

01

10

01 1

0

10

0

v3

0 1

v2

2

f1

f2

f

f2

v2v3

f1

v4

v3

0 1 0 1

v4

v3

v2

v5

v4

0 1 0 1

v4

v3

v5

0 v4

v3

4

4

4

4

4

33

3 11

3 3

3

5

5

5

4

22

2

2









119891 (V119895) = V119895119891 (V119909) + V119895 (V119894119891 (V119909) + V119894119891 (V119910))= 119891 (V119909) (V119894 + V119895) + 119891 (V119910) V119894V119895

(3)

= 119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895 (4)

= 119891 (V119909) V119894V119895 + 119891 (V119910) V119894V119895 (5)







(b) (c)

(d) (e)

01

01

01

01(a)

f(x)

f(x)

f(x)

f(x)

f(x)

x y

j

j j

j

f(y)f(y)

f(y)

f(y)

f(y)f(j)

f(j)

f(j)f(j)

f(j)i

i

ii

ji


(b)

01

01

01

01

(c)

(d) (e)(a)

f(x)

f(x)f(x)

f(x)f(x)

x

k k

y

j

ji

kj

i

kj

i

kj

ii

f(y)

f(y)f(y)

f(y)f(y)

f(j)

f(j)

f(j)f(j)

f(j)

f(k)




(6)

= 119891 (V119909) (V119896V119894V119895) + 119891 (V119910) (V119896V119894V119895) (7)

= 119891 (V119909) (V119896 + V119894 + V119895) + 119891 (V119910) (V119896 + V119894 + V119895) (8)




(9)

= 119891 (V119909) (V119894 + V119896V119895) + 119891 (V119910) (V119894 + V119896V119895) (10)

= 119891 (V119909) (V119894 (V119896 + V119895)) + 119891 (V119910) (V119894 (V119896 + V119895)) (11)





(12)

= 119891 (V119909) (V119895 ⊙ V119894) + 119891 (V119910) (V119895 oplus V119894) (13)







(a) (c)(b)

01

01

f(x)

f(x)f(x)

x y

jjj

iiii

f(y)f(y)

f(y)

f(j)

f(k)f(k)



























119875119886V = 119873119875119886V1 = 119873(119901119897119900119908119875119897119900119908 + 119901ℎ119894119892ℎ119875ℎ119894119892ℎ) (14)





5 Conclusion


Data Availability




Acknowledgments



MCNC circuits

0

20

40

60

80

100

120

140

ABC

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

DCThis work

Tran

sisto

r Cou

nt

(a)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

0

100

200

300

400

500

600

ABCDCThis work

MCNC circuits

Aver

age P

ower

(W

)

(b)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

Del

ay (p

s)

MCNC circuits

0

40

80

120

160

200

ABCDCThis work

(c)

PDP(

fJ)

MCNC circuits

0

20

40

60

80

100

ABCDCThis work

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

(d)



References


































RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



(b) (c)

(d) (e)

01

01

01

01(a)

f(x)

f(x)

f(x)

f(x)

f(x)

x y

j

j j

j

f(y)f(y)

f(y)

f(y)

f(y)f(j)

f(j)

f(j)f(j)

f(j)i

i

ii

ji


(b)

01

01

01

01

(c)

(d) (e)(a)

f(x)

f(x)f(x)

f(x)f(x)

x

k k

y

j

ji

kj

i

kj

i

kj

ii

f(y)

f(y)f(y)

f(y)f(y)

f(j)

f(j)

f(j)f(j)

f(j)

f(k)




(6)

= 119891 (V119909) (V119896V119894V119895) + 119891 (V119910) (V119896V119894V119895) (7)

= 119891 (V119909) (V119896 + V119894 + V119895) + 119891 (V119910) (V119896 + V119894 + V119895) (8)




(9)

= 119891 (V119909) (V119894 + V119896V119895) + 119891 (V119910) (V119894 + V119896V119895) (10)

= 119891 (V119909) (V119894 (V119896 + V119895)) + 119891 (V119910) (V119894 (V119896 + V119895)) (11)





(12)

= 119891 (V119909) (V119895 ⊙ V119894) + 119891 (V119910) (V119895 oplus V119894) (13)







(a) (c)(b)

01

01

f(x)

f(x)f(x)

x y

jjj

iiii

f(y)f(y)

f(y)

f(j)

f(k)f(k)



























119875119886V = 119873119875119886V1 = 119873(119901119897119900119908119875119897119900119908 + 119901ℎ119894119892ℎ119875ℎ119894119892ℎ) (14)





5 Conclusion


Data Availability




Acknowledgments



MCNC circuits

0

20

40

60

80

100

120

140

ABC

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

DCThis work

Tran

sisto

r Cou

nt

(a)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

0

100

200

300

400

500

600

ABCDCThis work

MCNC circuits

Aver

age P

ower

(W

)

(b)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

Del

ay (p

s)

MCNC circuits

0

40

80

120

160

200

ABCDCThis work

(c)

PDP(

fJ)

MCNC circuits

0

20

40

60

80

100

ABCDCThis work

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

(d)



References


































RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia






(a) (c)(b)

01

01

f(x)

f(x)f(x)

x y

jjj

iiii

f(y)f(y)

f(y)

f(j)

f(k)f(k)



























119875119886V = 119873119875119886V1 = 119873(119901119897119900119908119875119897119900119908 + 119901ℎ119894119892ℎ119875ℎ119894119892ℎ) (14)





5 Conclusion


Data Availability




Acknowledgments



MCNC circuits

0

20

40

60

80

100

120

140

ABC

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

DCThis work

Tran

sisto

r Cou

nt

(a)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

0

100

200

300

400

500

600

ABCDCThis work

MCNC circuits

Aver

age P

ower

(W

)

(b)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

Del

ay (p

s)

MCNC circuits

0

40

80

120

160

200

ABCDCThis work

(c)

PDP(

fJ)

MCNC circuits

0

20

40

60

80

100

ABCDCThis work

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

(d)



References


































RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




















119875119886V = 119873119875119886V1 = 119873(119901119897119900119908119875119897119900119908 + 119901ℎ119894119892ℎ119875ℎ119894119892ℎ) (14)





5 Conclusion


Data Availability




Acknowledgments



MCNC circuits

0

20

40

60

80

100

120

140

ABC

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

DCThis work

Tran

sisto

r Cou

nt

(a)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

0

100

200

300

400

500

600

ABCDCThis work

MCNC circuits

Aver

age P

ower

(W

)

(b)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

Del

ay (p

s)

MCNC circuits

0

40

80

120

160

200

ABCDCThis work

(c)

PDP(

fJ)

MCNC circuits

0

20

40

60

80

100

ABCDCThis work

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

(d)



References


































RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia



MCNC circuits

0

20

40

60

80

100

120

140

ABC

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

DCThis work

Tran

sisto

r Cou

nt

(a)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

0

100

200

300

400

500

600

ABCDCThis work

MCNC circuits

Aver

age P

ower

(W

)

(b)

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

Del

ay (p

s)

MCNC circuits

0

40

80

120

160

200

ABCDCThis work

(c)

PDP(

fJ)

MCNC circuits

0

20

40

60

80

100

ABCDCThis work

b1

con1

dc1dekodermajo

rity

newcw

prd53 wim xo

r5z4m

l

cm82c17

(d)



References


































RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia

























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia


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