https://doi.org/10.1007/s10836-019-05828-6

A Binary Decision Diagram Approach to On-line Testingof Asynchronous Circuits with Dynamic and Static C-elements

Pradeep Kumar Biswal1 · Santosh Biswas2

Received: 14 May 2019 / Accepted: 10 September 2019© Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractThe fast growing in complexity of digital VLSI circuits with the advance of deep sub-micron scaling causes occurrence offaults during normal operation of the circuits. These faults cannot be detected by off-line test or Built-In-Self-Test (BIST)techniques. Further, a number of critical faults may require detection at the functional mode during run-time. On-line Testing(OLT) provides a solution to both the problems, and can be implemented using appropriate Design-for-Testability (DFT)techniques. Nowadays, use of asynchronous circuits in semiconductor industry has rapidly increased because of no clockskew problem, low power consumption, average case performances and high degree of modularity. It has been found inthe literature of OLT of VLSI circuits that the number of OLT schemes proposed for asynchronous circuits is very fewcompared to synchronous circuits. The main drawbacks of the existing OLT schemes for asynchronous circuits are protocoldependency, high area overhead and scalability. In this work, we have proposed a partial replication based OLT scheme forasynchronous circuits with dynamic and static C-elements using Binary Decision Diagram (BDD). The proposed schemeworks for all circuits irrespective of their design protocols and achieves high fault coverage and comparatively low areaoverhead. It has been observed that the area overhead is further reduced with increase in values of FD-transitions (FaultDetecting transitions) exclusion. Furthermore, the use of BDD enables the scheme to handle fairly large circuits.

Keywords On-line testing (OLT) · Asynchronous circuit · Binary decision diagram (BDD) · Area overhead (AO) ·Fault coverage (FC) · Signal transition graph (STG)

1 Introduction

The complexity of digital VLSI circuits in recent years hasincreased in a very impressive manner. The sophisticationof VLSI technology has reached a point where an effortis made to put a large number of devices on a single chipby by shrinking feature sizes−decreasing the dimensionsof the transistors and length of the interconnection wires.As the fabrication technology moves to lower sub-micron

Responsible Editor: R. A. Parekhji

� Pradeep Kumar Biswalbiswalpradeep28@gmail.com

Santosh Biswassantoshbiswas402@yahoo.com

1 Department of Computer Science and Engineering,IIIT Bhagalpur, Bihar, India

2 Department of Electrical Engineering and Computer Science,IIT Bhilai, Bihar, India

processes and engineers continuously increase the designcomplexity, testing encounters greater challenges [12].Testing of digital VLSI circuits can be classified intotwo important classes; off-line testing and On-line Testing(OLT). The off-line testing strategies (Automatic TestEquipment (ATE) based testing and Built-In-Self-Test(BIST) [3, 14]) cannot detect faults that develop on-the-flyduring operation of the circuit. It has been observed that theprobability of occurrence of such faults in the present dayVLSI circuits designed using deep sub-micron technology ishigh [18, 22]. Therefore, OLT is becoming an indispensablepart of testing [9, 21]. OLT can be defined as the procedureto enable integrated circuits to verify the correctness oftheir functionality during normal operation by checkingwhether the response of the circuit conforms to its desireddynamic behavior. In OLT, it requires an on-chip DesignFor Testability (DFT) circuity to test the Circuit Under Test(CUT) for all the input patterns that would appear duringnormal operation of the CUT [6, 7, 21, 24].

Since last two decades, a number of OLT techniques havebeen proposed for digital circuits, which can be broadly

/ Published online: 7 November 2019

Journal of Electronic Testing (2019) 35:715–727

classified as−signature monitoring in Finite State Machines(FSMs) [13, 27], self-checking design [16, 21], on-lineBIST [1, 2, 30] and partial replication [4, 5, 8, 9, 15].Signature monitoring techniques for OLT basically workby studying the state sequences of the circuit FSM model(called signature) during its operation. Signatures areanalyzed concurrently with the execution of the circuitand target to detect faults that lead to the paths havingtransitions which do not exist in the FSM specification[13, 27]. To make the runtime signature of the fault-free circuit FSM different from the one with the fault, asignature invariant property is forced during FSM synthesis.To obtain an FSM with signature invariant property, the stateassignment procedure may have to be modified to takeinto account the constraints related to such an invariant.Thus, this technique requires some special properties inthe circuit structure, which leads to a change in theoriginal structure of the circuit. So, signature monitoringis treated as an intrusive OLT technique. Further, the stateexplosion problem in FSM models makes the application ofthis scheme limited to circuits having typically about onehundred states.

The technique of self checking design involves encodingof the circuit outputs using some error detecting codeand then checking the corresponding property of codeinvariance (e.g., parity, m-out-of-n code, berger-codes, etc.)[16, 21]. This technique confirms that the erroneous outputsgenerated due to occurrence of any fault in the circuitwill not be misinterpreted as correct outputs. For an on-line tester, a non-code word output is the indication ofoccurrence of fault in the CUT. The main drawback of thistechnique is that it requires a number of design and synthesisconstraints to control the scope of fault propagation. Thus,it requires re-synthesis and re-design, which modify theoriginal structure of the circuit. Therefore, self-checkingdesign is also an intrusive OLT technique.

Design of circuits with additional on-chip logic, whichcan be used to test the circuit before it powers on, is calledoff-line Built-In-Self-Test (BIST). Off-line BIST resourcescan be used for OLT during the idle times of the variouscircuit modules [1, 2, 30]. The advantage is resource sharingfor both on-line and off-line BIST. However, the efficiencyof on-line BIST mainly depends on the amount of idle timesavailable in the circuit modules. The present day circuitstarget to achieve pipelining and parallelism, which reducethe idle times of their modules (i.e, high utilization of theirmodules). So, on-line BIST cannot be considered as anefficient technique for OLT.

In the case of partial replication technique, a minimizedversion of the Circuit Under Test (CUT) is designed andOLT is performed by cross-checking for similarity of outputresponses of the CUT and the replicated circuit. In [15],a complete set of test vectors is generated using any

Automatic Test Pattern Generation (ATPG) algorithm on thenext state logic of the CUT, considering the current state bitsalso as primary inputs. Then a subset of the test vectors aretaken and synthesized into a prediction logic that generatesthe expected next state of the CUT when any input-presentstate combination matches with a test vector (of the subsetused in the prediction logic design). The prediction logicoutputs are compared with state flip-flop outputs of the CUTand in case of a mismatch, a fault indicator bit is set. Theinput-present state combinations which are not consideredin the subset of test vectors are don’t cares and this results inthe prediction logic circuit having lower area as compared tothe CUT. The partial replication technique is widely used inOLT because of the advantages such as simplicity in design,non-intrusiveness (minimal changes in original structure ofthe CUT), provides flexibility in terms of trade-offs betweenarea and power overheads of the on-line tester versus faultcoverage and detection latency, etc. [5, 7, 15, 17]. In thiswork, we aim at designing a partial replication based OLTscheme for asynchronous circuits.

Recently, VLSI community has grown interest inasynchronous circuits because they have no clock skewproblem, have potentially lower power consumption, canbe designed for average case performances rather thanthe worst case performances, and have higher degree ofmodularity. Testing of asynchronous circuits as comparedto synchronous circuits is considered difficult due to theabsence of the global clock [19]. Also, OLT of such circuitsis one of the challenging tasks. It has been found that mostof the OLT schemes are designed for synchronous circuitscompared to asynchronous circuits. There are few worksthat have been proposed on OLT of asynchronous circuits[4, 8, 25, 26, 29]. Now we elaborate these works one afteranother.

OLT of asynchronous circuit discussed in [29] by Verdelet al. is based on simple double redundancy method, wheretwo copies of the same circuit run in parallel and theon-line tester checks if they generate the same outputresponses. The main drawback of this scheme is that ithas more than 100% area and power overheads. Further,both being the same circuit, they are susceptible to similarnature of failures. The OLT schemes for asynchronouscircuits presented in papers [25, 26] work by checking ifthe output of the circuit satisfies a predefined protocol.The protocol is maintained in such a way that there is nolate occurrence or premature transitions. The on-line testercircuit (called checker) is designed using Mutual Exclusion(Mutex) elements, David Cells (DC), C-elements [20] andlogic gates. Basically, the checker operates in two modes;normal test mode and self-test mode. In normal test mode,the checker detects if there is any contravene in the protocolbeing executed by the Circuit Under Test (CUT). In self-testmode, the checker detects if there are any faults occurring

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within it. The main drawback of these schemes is that thearea overhead is much higher than that of the CUT, evencompared to the redundancy based methods. This is becausethe on-line tester is designed using Mutex elements andarea overhead of the Mutex elements is quite high. Furtherthese schemes only check the protocol, thus there is noguarantee for fault coverage and detection latency. The OLTschemes reported in papers [4, 8] are non-intrusive in natureand have low area overhead, however they are not scalablebecause of state explosion problem in discrete event systemmodel. From the above discussion, we aim at developinga Binary Decision Diagram (BDD) based OLT scheme forasynchronous circuits with static and dynamic C-elements,which is protocol independent, scalable and incurs low areaoverhead.

The rest of the paper is organized as follows. Circuitmodeling under normal and faulty conditions and genera-tion of fault detecting transitions are illustrated in Section 2.We discuss the procedure of generation of fault detect-ing transitions using BDD in Section 3. Design of on-linetester circuit from fault detecting transitions is explained inSection 4. We present experimental results regarding faultcoverage, area overhead and FD-transitions exclusion inSection 5 and conclude in Section 6.

2 Circuit Modeling Under Normal and FaultyConditions and Generation of FaultDetecting Transitions

In this section, we start with modeling of asynchronouscircuit using Signal Transition Graphs (STGs) under normaland faulty conditions, then convert these STGs into StateGraphs (SGs) and generate Fault Detecting transitions

(FD-transitions) from the state graphs. The STG (a variantof petri net model) is widely used to model asynchronouscircuits because it interprets transitions as input-outputsignal transitions and describes behavior of the circuit byestablishing casual relations among the signal transitions.

2.1 STG Representation of Asynchronous Circuit

This subsection represents the behavior of asynchronouscircuits using STG. In order to discuss our proposedscheme, an example of asynchronous circuit shown in Fig. 1is considered as the CUT. The circuit consists of 2, C-elements and some logic gate. C-elements are used as theprimitive components for building asynchronous circuitsand providing the basis for asynchronous communication.There are two types of C-elements; static and dynamic. Bothof the implementations have different advantages. The staticC-elements guarantee that data can be stored inside it forunbounded periods, whereas dynamic C-elements have lowarea, delay and power consumption [8, 28]. In this work,we have chosen asynchronous circuits with both static anddynamic C-elements for on-line testing. The C-element C1in the CUT shown in the Fig. 1 is a static C-element andthe C-element C2 is a dynamic C-element. When both theinputs of C-element are low (high) then it’s output is low(high), otherwise it keeps it’s previous logic value. Thus, theBoolean expression of C-element is C = XY +XC′ +YC′,where X and Y are two inputs, C and C′ are next andold state values, respectively. Transistor level diagram ofstatic and dynamic C-elements are shown in Fig. 2a and b,respectively.

The Signal Transition Graph (STG) represents thebehavior of the CUT (Fig. 1), as shown in Fig. 3. Thereare two types of transitions on each signal in STG; rising

Fig. 1 Example of anasynchronous circuit (i.e. CUT)

C1

C2

a

X

Y

X

Y

c

d

b

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Fig. 2 Transistors of C-elements

transition (indicated by +) and falling transition (indicatedby −). The dark circles along the edges are called tokens.Presence of token enables the signal transition to fire. Whenthere are tokens at all the input edges of a signal transitionthen it is enabled to fire. For example, when both the signalsa and c become low (denoted by transitions a− and c−,respectively), then only transition d− can fire. After firingof d−, a token is placed on each of its outgoing edges, thusenabling transition a+ to fire.

2.2 Fault Model in Asynchronous Circuits

Faults in the digital circuits occur due to wearing out,aging of the components, etc., and these type of faultsare called physical faults. Testing of physical faults isextremely complex because of limited access to the internalcomponents of the circuit and difficulty to measure them.Also their number is prohibitively high to be tested inreasonable time. So logical faults are devised, which are

Fig. 3 STG representation of CUT (Fig. 1)

convenient representation of effect of physical faults onthe operation of the circuit. In the present work on OLTof asynchronous circuits, we have assumed single stuck-at fault model. We have applied stuck-on and stuck-offfaults for each transistor of both the static and dynamic C-elements and stuck-at faults at different lines of the CircuitUnder Test (CUT), one at time.

Consider stuck-on fault at transistor p1 of dynamic C-element C2 in the CUT (shown in Fig. 1). The inputs ofC2 are a and c, and output of C2 is d . Stuck-on fault attransistor p1 (Say F1) waits transistor p2 to be enabled togenerate the output (referring to the transistor level diagramof C-element C2 shown in Fig. 2b). When p2 turns on thena path to Vdd is established via p1 and p2. Now transistorn3 turns on, transistor p3 turns off and output becomes low.Thus, the effect of F1 is that output of C2 becomes low(i.e., d−) when p2 turns on (i.e., a−). That means d− canfire just after firing of a− and does not wait for firing ofc−. However, in normal case d− can fire only after firingof a− and c− (referring to the STG representation of CUTshown in Figure 3). Thus, this fault results premature firingof d−. The STG representation of the CUT under F1 isshown in Fig. 4. We denote “1” on the edge of c− indicatingthat d− can fire as soon as a− fires, without waiting forfiring of c−.

Consider stuck-on fault at transistor n1 (say F2) of staticC-element C1 in the CUT shown in Fig. 1. The transistorlevel diagram of static C-element is shown in Fig. 2a. Thisfault (stuck-on fault at transistor n1) enforces the CUT towait for n2 to be enabled. When n2 turns on, then a path toground is established via transistors n1 and n2, which turnson transistor p4, turns off transistor n4 and makes outputof C1 high. Therefore, the effect of F2 is that the outputof C1 becomes high (i.e., c+) when n2 turns on. As n2 isconnected to input X (of C-element C1), which is logical

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a+

d+

a−

d−

b−

c+

b+

c−1

Fig. 4 STG representation of CUT under F1

ORing of transitions b− and d−. Hence transition c+ canfire after firing of b− or d− and does not wait for firing ofa+. It may be noted that under normal condition, for c+ tofire, it mandates to fire a+ with b− or d−. This prematurefiring of the transition c+ is indicated in the STG by adding“1” to a+, which is shown in Fig. 5.

Let there be a stuck-off fault at transistor n2 (say F3)of static C-element C1 in the CUT shown in Fig. 1. Asn2 is off, there will be no path established to ground. So,transistor p4 never turns on and output of C1 never becomeshigh. In other words, we shall never have the c+ transition.This is represented in the STG by adding 0 on the outputedges of c+, which is shown in Fig. 6. In similar way,we have applied faults in the asynchronous circuits withstatic and dynamic C-elements and studied their effects.The effect of each fault is represented using separate STGs.Next we convert the STGs representing CUT under normaland faulty conditions into separate State Graphs (SGs)and discuss the procedure of generation of Fault Detectingtransitions (FD-transitions).

a+

d+

a−

d−

b−

c+

b+

c−

1

Fig. 5 STG representation of CUT under F2

a+

d+

a−

d−

b−

c+

b+

c−

00

Fig. 6 STG representation of CUT under F3

2.3 Converting STG Into State GraphModeland Generation of FD-Transitions

A State Graph (SG) G is defined as G = 〈V, X, �, X0〉,where V = {v0, v1, ..., vn}1 is a finite set of Boolean vari-ables, i.e., the domain of the variables is {0, 1}, X is a finiteset of states, � is a finite set of transitions and X0 ⊆ X isthe set of initial states. A state X is a mapping of each vari-able to one of its domain elements. A transition τ ∈ � froma state Xi to another state Xj is an ordered pair 〈Xi, Xj 〉,where Xi and Xj are present state and next state

of τ , respectively.The stuck-on and stuck-off faults in the transistors of

the C-elements of the circuit are captured by dividingthe SG into sub-models and each sub-model is used todescribe the system under normal or faulty conditions. Tomake differentiation among the sub-models, each state X isassigned a fault label by a status variable S with it’s domainbeing equal to {N ∪ F1 ∪ F2 ∪ .... ∪ Fp}, where N is thenormal status, Fi, 1 ≤ i ≤ p, is the ith fault status and p

is the number of possible faults. It must be noted that thestatus variables are dummy variables and are unmeasurable.These are only used for fault modeling of the circuit. If thestatus variables are measurable then fault detection problemis trivial. Now, we introduce some terminologies which arerelated to the SG model G and would be required for faultmodeling of the circuit.

Definition 1 Normal G-state: A G-state X is normal ifX(S) = N . The set of all normal states is denoted as XN .

Definition 2 Fi-G-state: A G-state X′ is fault state, orsynonymously, an Fi-state, if X′(S) = Fi . The set of allFi-states is denoted as XFi

.

1In case of modeling asynchronous circuit using SG, the values of statevariables are values of the input/output signals. In this work, we usethe terms signal and variable interchangeably.

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Definition 3 Normal-G-transition: A G-transition〈Xi, Xj 〉 is called a normal G-transition if Xi, Xj ∈ XN .

Definition 4 Fi-G-transition: A G-transition 〈X′i , X

′j 〉

is called an Fi-G-transition if X′i , X

′j ∈ XFi

.

Definition 5 Equivalent states: Two states Xi and Xj

are said to be equivalent, denoted as XiEXj , if Xi |V =Xj |V and Xi(S) = Xj(S).

In other words two states are said to be equivalent ifthey have same values for state variables and differentvalue for status variable.

A transition 〈Xi, X′i〉, where Xi(S) = X′

i (S), is calledan sk-transition (start of fault Fk), indicating the firstoccurrence of fault Fk in the circuit. The occurrence ofan sk-transition only changes the status variable (i.e., S)from N to Fk and all other variables remains unchanged.Since the status variables are unmeasurable, thus sk-transition are unmeasurable. Also, faults are assumed to bepermanent.

Definition 6 Equivalent transitions: Two transitionsτ1 = 〈Xi, Xj 〉 and τ2 = 〈X′

i , X′j 〉 are equivalent,

denoted as τ1Eτ2, if XiEX′i , XjEX′

j and they mustassociate with same signal change.

Now, we discuss the procedure of generation of FD-transitions from SG model. As usual state based OLTstrategy, we first represent the asynchronous circuit undernormal and faulty conditions using separate STGs, thenconvert them into corresponding SG sub-models. The wholeprocedure can be explained in detail by taking the exampleof CUT shown in Fig. 1 and stuck on fault at transistor p1of C-element C2 (i.e., F1).

Since the CUT has 4 input and output signals (a, b, c

and d), so the corresponding SG model has 4 state variables(i.e., v0 = a, v1 = b, v2 = c and v3 = d) and each variableassumes values from the set {0, 1}. Figure 7 shows the SGmodel for the CUT under normal and faulty (F1) conditions.It consists of two SG sub-models; normal and faulty. Theset of states in normal SG sub-model (i.e., XN ) consists of14 states, starting from X0 to X13 and X0 is the initial state.Similarly, the faulty SG sub-model (i.e., XF1 ) consists of 16states, starting from X′

0 to X′15 and X′

0 is the initial state. Thestates X0 and X′

0 are equivalent states (X0EX′0) because

X0|V = X′0|V = 1010. Similarly, X1EX′

1, X2EX′2, and

so on. The transitions 〈X0, X1〉 and 〈X′0, X

′1〉 are equivalent

transitions (〈X0, X1〉E〈X′0, X

′1〉) because X0EX′

0 , X1EX′1

and they are associated with same signal change d+.Similarly, 〈X0, X2〉E〈X′

0, X′2〉, 〈X1, X3〉E〈X′

1, X′3〉, and so

on. The unmeasurable s1-transitions indicate occurrence offault F1 on the fly during normal operation of the CUT,which can be found in Fig. 7.

The normal SG sub-model shown in Fig. 7 is constructedfrom the STG representation of CUT under normalcondition. It shows the state mappings and transitions,e.g., the state (〈a, b, c, d〉) mappings of X0 and X1 are〈1, 0, 1, 0〉 and 〈1, 0, 1, 1〉, respectively. The transition fromX0 (present state) to X1 (next state) changes d from 0 to1, which is indicated by transition d+. In similar way, thewhole normal SG sub-model is constructed using the normalSTG (Fig. 3). Likewise, the faulty SG sub-model for faultF1 is constructed from the faulty STG (Fig. 4), which isshown in Fig. 7. If we compare the normal and faulty SGsub-models, it can be found that there are two transitions(〈X′

4, X′14〉 and 〈X′

5, X′15〉) in the faulty SG sub-model

which are different from that of normal SG sub-model.These transitions appear due to occurrence of fault F1 in theCUT. This indicates premature firing of d−. We call these

1111

1010

1011

0011

1110

0111

1101

0101

0100

1100

1001

0001

0000

1000

d+

a−

b+

b+

b+

d+

d+c−

c−

a−

b−

b−

b−

b−

d−

a+

a−

d−

a+ c+

1010

1011

0011

1110

0111

1101

0101

0100

1100

1001

0001

0000

1000

d+

a−

b+

b+

b+

d+

d+c−

c−

a−

b−

b−

b−

b−

d−

a+

a−

d−

a+ c+

1111

0010 0110

d−

X0

X1

X2

X3

X5

X6

X7

X9

X11

X8

X10

X12

X13

X’0

X’1

X’4

X’2

X’3

X’5

X’6

X’7

X’9

X’11

X’8

X’10

X’12

X’13

X’14

X’15

1

s1

Normal SG sub−model Faulty SG sub−model

s

d−

Fig. 7 SG model for the CUT (of Fig. 1) under normal and faulty (F1) conditions

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transitions as Fault Detecting transitions (FD-transitions).In other words, if there is a transition in faulty SG sub-modelfor which there is no corresponding equivalent transitionin the normal SG sub-model, then that transition is calledan FD-transition. Thus, we can define FD-transition asfollows.

Definition 7 FD-transition: An Fi-G-transition offaulty SG sub-model τ ′ = 〈X′

i , X′j 〉 is an FD-transition,

if there is no G-transition τ = 〈Xi, Xj 〉 in the normalSG sub-model such that τ ′Eτ .

The FD-transitions for all targeted faults in the CUT aregenerated and on-line tester circuit is designed using suchtransitions. In OLT, the on-line tester circuit runs parallelwith the CUT and detects occurrence of fault when the CUTtraverses through any FD-transition. In this work, we havecomputed equivalent FD-transitions and reduced the num-ber of FD-transitions to be considered in the tester design,which reduces its area overhead. We have first definedthis equivalence and then explained using an example.

Definition 8 Equivalent FD-transitions: Two FD-transitions τ ′

1 = 〈X′i , X

′j 〉 and τ ′

2 = 〈X′k, X

′l〉 are said to

be equivalent if the following conditions are satisfied:

– They must have same signal change (rising orfalling). If v1 and v2 are the signal change by FD-transitions τ ′

1 and τ ′2, then v1 is same as v2.

– Let V ′1 ⊆ V (for τ ′

1 = 〈X′i , X

′j 〉) be the set of

signals whose values at X′i are different compared to

state(s) Xp, where Xp ∈ XN (any state under normalcondition), from which v1 is the signal change.Similarly, the set V ′

2 ⊆ V is calculated for FD-transition τ ′

2 = 〈X′k, X

′l〉. Then V ′

1 ∩ V ′2 = ∅. That

means, there exists at least one signal whose valueis same in initial state of both the FD-transitionsand that is different compared to the initial state ofthe corresponding equivalent transition under normalcondition.

For example, consider stuck-on fault at transistor n1 (F2)of static C-element C1 in the CUT shown in Figure 1. Theeffect of F2 is premature firing of transition c+, i.e., c+ canfire after firing of b− or d− and does not wait for firingof a+. The FD-transitions to detect F2 are 〈0001, 0011〉and 〈0100, 0110〉, whereas corresponding normal transitionis 〈1000, 1010〉. These two FD-transitions are equivalentbecause they have same signal change (i.e., c+) and twosignals have same values at the initial states (i.e., a = 0 andc = 0).

This process of generating FD-transitions from the SGframework becomes complex for large circuits because the

a

d

1

0

0 1

1 0

Fig. 8 Normal OBDD

number of states in the SG grows exponentially with thevariables/ signals of the circuit. Further, comparing eachtransition under normal and faulty SG sub-models in orderto generate FD-transitions is a time taking task. In orderto solve these problems we have devised a procedure whichis capable of generating FD-transitions directly from thecircuit description using Ordered Binary Decision Diagrams(OBDDs) [10, 11], without need of the explicit state graphmodel.

3 Generation of FD-Transitions using OBDD

In this section, we demonstrate the procedure of generationof FD-transitions using OBDD by considering the runningexample of CUT and fault F1 (stuck-on fault at transistor p1of C-element of C2), following that the detailed procedureis discussed.

a

c c

d

1 0

0 1

1 0

0 1

1 0

Fig. 9 Faulty OBDD

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a

c c

d d

01

1 0

01

1

00

1

1

0

Fig. 10 XORed OBDD

The effect of fault F1 is premature firing of transition d−.The STG representation of CUT under F1 is shown in Fig. 4,where d− is fired as soon as a− fires, without waitingfor c−. In other words, we can say that under this faultc− is always true, (i.e., c = 0 always) and whenever a−occurs in the circuit then d− occurs. Since d is the outputof C2, thus the Boolean expression for d under normalcondition is ac+cd ′ +ad ′ (say, dN ). Similarly, the Booleanexpression for d under F1 is ad ′ (say dF1 ), which is obtainedby substituting c = 0 in dN . The OBDD representationsof dN and dF1 are shown in Figs. 8 and 9, respectively.XORed OBDD corresponding to dN ⊕ dF1 is depicted inFig. 10, which is obtained by XORing the normal and faultyOBDDs shown in Figs. 8 and 9, respectively. The set of nextstates under F1 which are different compared to the normalcondition is obtained by applying “satisfy-all-1” operationon the XORed OBDD. In case of F1, the such set of nextstates is {〈a = 0, b = 0, c = 1, d = 0〉, 〈a = 0, b = 1, c =1, d = 0〉, 〈a = 1, b = 0, c = 1, d = 1〉, 〈a = 1, b =1, c = 1, d = 1〉}. Since the effect of fault F1 is prematurefiring of d−, so the value of d in the next states must beequal to 0. Therefore, we have considered the next stateswhere d = 0. Now the set of next state becomes as {〈a =0, b = 0, c = 1, d = 0〉, 〈a = 0, b = 1, c = 1, d = 0〉}.

Corresponding to the next state 〈a = 0, b = 0, c = 1, d =0〉, the present state is 〈a = 0, b = 0, c = 1, d = 1〉 andthe FD-transition is 〈0011, 0010〉. Similarly, correspondingto the next state 〈a = 0, b = 1, c = 1, d = 0〉, the FD-transition is 〈0111, 0110〉. Same FD-transitions were foundin the case of SG model, which is depicted in Fig. 7.

Now we discuss the general procedure for generation ofFD-transitions for a given fault (say Fi) using OBDD. Ini-tially, the effect of the fault Fi is found from the STG modelof the fault. Let signal vk be one of the affected signals forthe fault Fi which fires prematurely. The following steps areused to generate FD-transitions to detect the premature fireof vk due to the fault Fi .

Fig. 11 State graph for on-linetester to detect FD1

c−

c+

d− S+

d−d+c− c+

010 110 100 101

001000

x0 x1x2 x3

x4x5

J Electron Test (2019) 35:715–727722

Fig. 12 State graph for on-linetester to detect equivalentFD-transitions 〈0001, 0011〉and 〈0100, 0110〉 100 000 010 011

110 111

c+c−

c+ S+

a− a+

x0 x1x2

x3

x4x5

a−

a+

4 Design of On-Line Tester Circuit usingFD-Transitions

In OLT, the On-line tester circuit is designed using theFD-transitions generated for the targeted faults and isexecuted parallelly with the CUT. The on-line tester detectsoccurrence of fault by checking whenever the CUT traversesthrough any FD-transitions. In case of design of on-linetester circuit for synchronous circuit, the on-line tester mustbe a synchronous circuit and that is easily designed from theFD-transitions using general Finite State Machine (FSM)synthesis philosophy. Since the CUT is an asynchronouscircuit, so the on-line tester must be designed as anasynchronous circuit for OLT.

Now we illustrate the design of on-line tester circuitusing the FD-transition 〈0011, 0010〉 (say FD1). We havedesigned the tester circuit using CAD tool Petrify [23]. Incase of FD1, the signal d is changed from 1 to 0 (i.e., d−)when a = 0 and c = 1, whereas in normal case d− fires(i.e., d is changed from 1 to 0) when a = 0 and c = 0(transitions 〈X7, X9〉 and 〈X10, X12〉 in normal SG sub-model shown in Fig. 7). In order to detect whether FD1 hasoccurred, the on-line tester taps lines c and d of the CUTand determines whether d− has fired with c = 1; if so, astatus output line becomes high. It can be noted that the linea is not required to be tapped because the value of a remainssame under normal and faulty cases (i.e., a = 0).

Figure 11 demonstrates on-line tester in the form ofstate graph model to detect FD1. The state encoding(〈c, d, S〉) of initial state x0 is 010, where first two bitsare complement of c = 1 and d = 0, and third bitrepresents status output (S) which is 0 until FD1 is detected.Once c+ occurs in the CUT, the on-line tester moves tostate x1. In x1, if d− fires (i.e., d− fires when c = 1)then FD-transition (i.e., FD1) has occurred in the CUTand hence fault is detected. This is accomplished by theon-line tester by moving to state x2 having encoding〈100〉. Following that, the tester moves to state x3 bymaking status output (S) high, indicating that fault has

occurred in the CUT. In x1, if c− fires then the on-linetester moves to state x0. The tester moves to state x5 fromstate x0 and back from x5 to state x0 by the transitions d−and d+, respectively. Similarly, the tester moves to state x4

from state x3 and back from state x4 to x3 by the transitionsc− and c+, respectively. We have added states x4 and x5 inthe state graph in order to satisfy the proprieties of CompleteState Encoding (CSE) and no liveness issues, which aremandatory in asynchronous circuit design.

Similarly, state graph for on-line tester to detectequivalent FD-transitions 〈0001, 0011〉 (say, FD2) and〈0100, 0110〉 (say FD3) is shown in Fig. 12. In case of FD2

and FD3, the signal c is changed from 0 to 1 (i.e., c+) whenb = 0 or d = 0, whereas in normal condition c+ fires whena = 1 with b = 0 or d = 0. Since FD2 and FD3 areequivalent, so there is no need to design separate sate graphsfor on-line tester to detect them. The on-line tester taps linesa and c of the CUT and determines whether c+ has firedwith a = 0.

The CAD tool Petrify [23] is used for synthesis of on-line tester circuit. It takes state graph description of on-linetester as input and produces a set of equations as output,

Fig. 13 State graph description of on-line tester

J Electron Test (2019) 35:715–727 723

Fig. 14 Set of equations foron-line tester

from which the on-line tester circuit is designed. Figure 13shows the snapshot of state graph description of on-linetester that is given as input to the Petrify and the snapshot ofset of equations produced (as output) from Petrify is shownin Fig. 14. The schematic of on-line tester circuit that isdesigned from the set of equations is shown in Fig. 15. Inthe same manner, all the state graphs for the FD-transitionshave been synthesized into different circuits. Then, thefinal on-line tester circuit for the CUT is designed byORing the outputs of these circuits. The output of the testercircuit becomes high when at least one individual outputbecomes high, hence detects the occurrence of fault inthe CUT.

5 Experimental Results

We have taken different asynchronous benchmark circuitswith static and dynamic C-elements to show the efficiencyof the proposed scheme. In this work, we have studiedthree important parameters in OLT; Fault Coverage (FC),Area Overhead (AO) and FD-transitions Exclusion (FDE).A fault is said to be covered if at least one FD-transition ofthat fault is considered in on-line tester design. We definefault coverage, area overhead as follows.

Fault Coverage (FC) = ((Total number of faultscovered)/(Total number of faults in CUT)) × 100%

Area Overhead (AO) = (Area of on-line tester)/(Area ofthe CUT)

FD-transitions Exclusion (FDE): Suppose X be the totalnumber of FD-transitions of fault Fi and Y (<= X) be thenumber of FD-transitions that are considered in the on-line

tester design. Then FD-transitions exclusion (FDE) for Fi

is (X/Y)-1.That means if we consider all FD-transitions of each fault

in design of on-line tester circuit, then FDE becomes 0.Table 1 shows the details of the circuit and fault coverage

achieved by the proposed scheme for different benchmarkcircuits. Column 1 provides the name of the circuit. Column2 and Column 3 illustrate total number of gates and totalnumber of faults of the circuit, respectively. In Column 4reports the percentage of fault coverage of the proposedscheme. If there doesn’t exist any FD-transition to detecta fault then that fault is called a redundant fault. Thefollowing points may be noted.

– More than 95% of faults are covered by the proposedscheme. However, remaining faults (less than 5%) arenot covered because in such cases there doesn’t existany FD-transitions (i.e., these faults are redundantfaults).

– We cannot compare fault coverage of proposed schemewith [25] because the scheme reported in [25] basedon checking of a predefined protocol, so fault coveragecannot be guaranteed.

– To the best of our knowledge, the size of the benchmarkcircuits for which the on-line tester could be designedby the proposed scheme are much higher than theones considered in the OLT literature for asynchronouscircuits. This scalability could be achieved due to theapplication of BDDs.

Table 2 illustrates the area overhead of the on-linetester circuit for different benchmark circuits under differentvalues of FD-transitions exclusion. We have calculated area

Fig. 15 On-line tester circuit todetect FD1

C

c

d

logic−0

S

J Electron Test (2019) 35:715–727724

Table 1 Fault Coverage of theproposed scheme Circuits Number of gates Number of Faults Fault coverage (%) CPU time (sec.) �

2 David cells 6 44 95.45 37

4 David cells 12 88 96.59 45

e chu172 9 47 95.83 48

alloc-outbound 15 130 95.38 53

sbuf-read-ctl 19 152 96.71 69

sbuf-send-ctl 18 140 95.00 63

ram-read-sbuf 23 197 95.43 78

� Intel Core i5-7200U CPU with 8 GB RAM in Linux OS

overhead for 3 different values of FD-transitions exclusion;FDE = 0, FDE = 3 and FDE = 5. In case of zero FD-transitions exclusion (FDE = 0), all FD-transitions for allfaults are incorporated in on-line tester circuit design, whichresults high area overhead. However, some FD-transitionsof each fault are dropped, depending on the values of FD-transitions exclusion, in design of on-line tester circuit,thereby leading to a reduction in area overhead. Column1 shows the name of the benchmark circuits. Column 2and Column 3 show the area overheads of the on-linetester under zero FD-transitions exclusion for the proposedscheme and the existing scheme, respectively. Similarly,Column 4, 5, 6 and 7 illustrate area overheads under thevalues of FD-transitions exclusion 3 and 5, respectively.The following points may be noted.

– With the increase of value of FD-transitions exclusion,the area overhead of the on-line tester is decreased.

– For a given value of FD-transitions exclusion, the areaoverhead of the proposed scheme is less than that of[25]. The reason is, the existing scheme ([25]) designedon-line tester circuit using Mutex elements and the areaof the Mutex elements is high.

– It can be observed in the table that the area overhead ofthe proposed scheme decreases with increase in circuit

size. This is because of common FD-transitions whichcan detect more than one faults simultaneously. Thecommon FD-transitions are selected first for design ofon-line tester circuit, hence area overhead is decreased.

– In this work, we have dropped some FD-transitionsof each fault depending on tradeoff required to reducethe area overhead of the tester. It is observed thatfor some faults the number of FD-transitions is quiteless compared to other faults. If we drop some FD-transitions for such faults, then they may not covered,leading to decrease in fault coverage, which is notdesirable in OLT perspective. Hence, we have assumeda threshold based on number of FD-transitions for eachfault in the circuit. For the faults whose number ofFD-transitions is less than the threshold value, all theFD-transitions of such faults are taken in the designof on-line tester circuit. For other cases, some FD-transitions are dropped to reduce the area overhead.

– It can be noted that the existing scheme reported in [25]does not provide any information regarding flexibilityin terms of trade-offs between area overhead of theon-line tester versus FD-transitions exclusion, whereasthe proposed scheme demonstrates area overhead fordifferent values of FD-transitions exclusion. Thus,provides flexibility in on-line tester design.

Table 2 Area overhead of theproposed scheme with differentvalue of FD-transitionsexclusion and comparison withexisting scheme [25]

Area overhead for FD-transitions exclusion (FDE)

Circuits FDE=0 FDE=3 FDE=5

Proposed [25] Proposed [25] Proposed [25]

Scheme Scheme Scheme

2 David cells 2.9 3.3 2.1 1.34

4 David cells 2.3 4.9 1.76 1.17

chu172 1.81 N/A 1.42 1.04

alloc-outbound 1.75 N/A 1.25 N/A 0.98 N/A

sbuf-read-ctl 1.56 N/A 1.05 0.93

sbuf-send-ctl 1.18 N/A 0.95 0.86

ram-read-sbuf 0.96 N/A 0.89 0.78

J Electron Test (2019) 35:715–727 725

6 Conclusion

In this paper, we have proposed a Binary Decision Diagram(BDD) based on-line testing scheme for asynchronouscircuits with static and dynamic C-elements. The proposedscheme works by representing circuit under normal andfaulty conditions using separate Signal Transition Graphs(STGs), then corresponding Ordered Binary DecisionDiagrams (OBDDs), normal and faulty OBDDs, areconstructed from the STGs. The normal and faulty OBDDsare XORed and FD-transitions are generated from theXORed OBDD. Finally, on-line tester is designed usingthese FD-transitions. Experimentally, it has seen that morethan 95% of faults are covered and area overhead of theproposed scheme is less than that of existing scheme. Thearea overhead of the on-line tester is further reduced withincrease in value of FD-transitions exclusion. The proposedscheme can be easily applicable to any asynchronous circuitirrespective of it’s design protocol.

In this work, we select FD-transition randomly fromthe set of FD-transitions for a fault in design of on-line tester circuit. However, the selection of FD-transitionscan be better accomplished by solving a multi-criterionoptimization problem using area and power of the tester,fault coverage, FD-transitions exclusion, importance ofFD-transitions in functionally of the circuit, numberof tappings in the critical paths, etc., as optimizationparameters. Further, it is assumed that the on-line tester isfree of faults. To make the OLT scheme more robust, testingof the on-line tester is required. This can be accomplishedby designing another tester circuit for the on-line tester.Testing of the on-line tester can be performed either on-lineor off-line. Off-line testing will incur less design issues, lowarea overhead, etc. However, in fault tolerant systems OLTof the on-line tester is necessary. Thus, further research isrequired to solve these issues.

Fault equivalence generally reduces the number of faults(thus, number of test patterns) for a circuit and it hasbeen fruitful in testing of sequential circuits. Generallythe size of asynchronous circuits is less compared tosynchronous circuits, so the number of faults in case ofasynchronous circuits is also less compared to that oftraditional synchronous circuits. Like synchronous circuits,fault equivalence technique can be applied in asynchronouscircuits in order to reduce number of faults. To thebest of our knowledge, no work has been proposed onequivalence of faults in asynchronous circuits. Thus, detailand independent study is required to show the effect of faultequivalence in testing of asynchronous circuits.

In this work BDD has been used to handle thecomplexity of generating the FD-transitions. Alternativetechniques like SAT can also be used in on-line testing toimprove scalability. It requires a separate study to find the

applicability of SAT-based technique in on-line testing tohandle the issue of complexity.

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Publisher’s Note Springer Nature remains neutral with regard tojurisdictional claims in published maps and institutional affiliations.

Pradeep Kumar Biswal completed his MTech and PhD from theDepartment of Computer Science and Engineering, IIT Guwahati. Atpresent he is a faculty member in IIIT Bhagalpur. His research interestsinclude VLSI testing.

Santosh Biswas received B.E degree from NIT, Durgapur, India, in2001. He has completed his M.S. and Ph.D from IIT Kharagpur, India,in the year of 2004 and 2008, respectively. He works as an AssociateProfessor at the Department of Computer Science and Engineering,IIT Guwahati. His research interests include networking, VLSI testingand discrete event systems.

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