16- layer pcb channel design with minimum crosstalk and …vagrawal/jetta/full_issue_35-4/p06... ·...

16- Layer PCB Channel Design with Minimum Crosstalkand Optimization of VIA and TDR Analysis

A. Kavitha1 & Ch. Sekhararao Kaitepalli2 & J. N. Swaminathan3& Shaik Ahemedali4

Received: 2 January 2019 /Accepted: 17 June 2019 /Published online: 4 July 2019# Springer Science+Business Media, LLC, part of Springer Nature 2019

AbstractA transparent interconnects on a 16 layer PCB stack-upwith a 100Ω differential impedance with interconnects is proposed in thispaper. To minimize the differential crosstalk, a differential spacing is maintained between interconnects. The trans-mitter and receiver are demonstrated as Input Buffer Information Specification (IBIS) models. An IBIS modeldescribes the V-I characteristics information about the particular buffer. To provide better channel performance, theinterconnect Via structures are optimized in this paper. To observe the channel performance in the frequency domain,S-parameter analysis is performed. To view BER plots, eye diagram and bathtub curve analysis is implemented. Toobserve the impedance with respect to the propagation delay of the channel, Time Domain Reflectometer (TDR) analysis isperformed. Debugging and impedance discontinuity correction are performed using TDR analysis. ADS 9 (Advanced DesignSystem) simulation software is used in this paper.

Keywords Crosstalk . Insertion loss . PCB stack-up . Surface roughness . S-parameters . TDR analysis . Trace . Via

1 Introduction

In the present era, the foremost challenge is to design a printedcircuit board (PCB) for routing on a multilayer, the packagingof the PCB should not crack during the assembly. The same isdiscussed in the paper. The electrical properties like rise time,impedance discontinuities, quarter wave stubs have no mucheffect in degrading any system performance at Megahertz fre-quencies. In the current modern applications like Gigabit andTerabit routers, DDR3 and DDR4 SD-RAM memories, 3G–

4G or LTE-A base stations, broadband applications, etc., theclock frequencies are running in hundreds of MHz and GHzrange. So the interconnects used between the transmitter andreceiver are no more transparent, also the impedance discon-tinuities start reflecting the signals. Even the frequency depen-dent losses like copper loss and dielectric loss have muchmore impact at GHz frequencies. Further, non-linear effectslike surface roughness (CuRz) and the glass weave effect ofdielectric might affect the interconnect performance and re-sults in a low bit error rate. The reduction in the rise time of the

Responsible Editor: B. C. Kim

* A. [email protected]

Ch. Sekhararao [email protected]

J. N. [email protected]

Shaik [email protected]

1 Department of Electronics and Communication Engineering, VelTechMulti TechDr. Rangarajan Dr. Sakunthala Engineering College,Avadi, Chennai, Tamilnadu, India

2 Department of Electronics and Communication Engineering, AnnaUniversity, Chennai, Tamilnadu, India

3 Department of Electronics and Communication Engineering,Godavari Institute of Engineering Technology (Autonomous),Rajamundry, Andhra Pradesh 533296, India

4 Department of Electronics and Communication Engineering, SasiInstitute of Technology & Engineering, Tadepalligudem, India

Journal of Electronic Testing (2019) 35:497–517https://doi.org/10.1007/s10836-019-05814-y

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http://orcid.org/0000-0002-8921-4923

http://orcid.org/0000-0002-7520-4839

mailto:[email protected]

signals in real time applications has become a challenge forsignal integrity engineers for ensuring proper eye opening andto meet out timing at the receivers. Especially timing marginshave become so burdensome for the applications using DDR3(or 4) SD-RAMS [1].

A contemporary application requires a higher bandwidth.So that, there is a requirement of High Density Interconnect(HDI) [2] boards which involve three layers [3] or eight layers[4] or more than 24 layers of PCB stack-up. The stack-up hasground-power-ground symmetrical layer with two groundplanes edges are connected to reduce emissions caused byground-signal planes [5]. Present requirements demand mini-mum spacing between interconnects which increases the near

end and far end crosstalk between signals resulting in failureof signal integrity at the receiver. The crosstalk can be reduced

Table 1 16 layer PCB stack-upLayerNo

Type oflayer

Thickness(mils)

Dielectricconstant

Trace width singleended (mils)

Trace widthdifferential (mils)

Architecture

1 Signal 1.7 4.5 3.75/10.5 Copper Foil

Dielectric 2.58 3.4 Laminate

2 Ground 1.7 Copper Foil


3 Signal 0.6 3.5 3.5/10.5 Core

Dielectric 3 3.3

4 Ground 0.6


5 Signal 0.6 3.5 3.5/10.5 Core

Dielectric 3 3.3

6 Ground 0.6


7 Signal 0.6 3.5 3.5/10.5 Core

Dielectric 3 3.3

8 Ground 1.2


9 Power 1.2 Core

Dielectric 3 3.3

10 Ground 0.6


11 Signal 0.6 3.5 3.5/10.5 Core

Dielectric 3 3.3

12 Ground 0.6


13 Signal 0.6 3.5 3.5/10.5 Core

Dielectric 3 3.3

14 Ground 0.6


15 Ground 1.7 Copper Foil


16 Signal 1.7 3.75/10.5 Copper Foil

Fig. 1 Differential 4-port S-parameters

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by stepped impedance LPF configuration and open circuitstub LPF configurations [6]. Further, complex Via structures[7] in the interconnect through which signal can be guided tothe internal layers of stack-up appear as capacitive discontinu-ity results in high reflection loss. In recent days, much techni-cal advancement happened in PCB fabrication units where thestubs on a Via can be removed using back-drilling [8].Advancements in a Via design are extended up to micro -

Fig. 2 Sweeping roughness values at constant trace length

Table 2 Shows the near end and far end crosstalk values for differentspacings

Space (mil) Near end crosstalk (dB) Far end crosstalk (dB)

1 W −21.399 −29.3792 W −25.267 −35.4673 W −31.243 −44.9464 W −45.853 −51.521

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Via, blind-Via and buried -Via. By using these technologies, aVia can be designed [9] transparent and will not appear asimpedance discontinuity [10]. There are several studies show-ing that the design of microstrip and strip lines in PCB is donethrough multiple available tools such as Ansoft Maxwell,

Q3D etc. As per the literature, well-defined design procedureof a Via is not discussed till now [11]. In a PCB design, Via ofstandard libraries are available from 8, 10 and 12 mil in whichthe signal integrity may not be taken into account [12, 13].The Via-hole reactance has been calculated in [14], while the

Fig. 3 Sweep length with constant roughness value

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other discontinuity models of Via and the impact on high-speed design is discussed in [15, 16]. The organization of thispaper is as follows: Section 2 discusses about the design pa-rameters of a transparent interconnect in PCB stack-up. InSection 3, S-parameter analysis is discussed. Section 4 dis-cusses about the proper selection of Via parameters.Section 5 explains IBIS Algorithmic Modeling Interface(AMI) and discussions about the results and Section 6 de-scribes the conclusion.

2 PCB Stack-up

By using standard stack up rules, a 16 layer PCB stack-up stripline and microstrip line is designed in this paper. The follow-ing parameters are considered in designing the strip lines to

achieve approximate 50Ω single ended impedance and 100Ωdifferential impedance:

Dielectric constant εr (forMegtron-6): 3.4Loss tangent tanD: 0.003Trace width W: 3.5 milsDielectric Height H1: 3.95 milsDielectric Height H2: 3 milsThickness T: 0.6 mils.

The following parameters are considered in designing themicro strip lines to achieve approximate 50 Ω single endedimpedance and 100 Ω differential impedance:

Dielectric constant εr (for Megtron-6): 3.4Loss tangent tanD: 0.003

Fig. 4 Nature of discontinuityfrom TDR

Table 3 TDR set-up

Case Parameters Case0 Case1 Case2 Case3 Case4 Case5 Case6

Drill diameter (mils) 8 8 8 8 8 8 8

Pad diameter (mils) 18 18 18 18 18 18 18

Anti-pad (mils) 30 30 30 40 45 50 60

Anti-pad type Circular, NFP’spresent

Circular, NFP’sremoved

Oval Oval NFP’sremoved

Oval NFP’sremoved

Oval NFP’sremoved

Oval NFP’sremoved

Separation betweendifferential Via’s (mils)

40 40 40 40 40 40 40

No of ground Via’s 2 2 2 2 2 2 2

Separation between differentialVia and ground Via (mils)

40 40 40 40 40 40 40

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Trace width W: 4.5 milsDielectric Height H: 2.58 milsThickness T: 1.7 mils.

The dielectric constant value of FR4 is 4.2. In this paper,the dielectric chosen is Megtron-6 having a low dielectricconstant compared to FR4 material and better loss tangent.The PCB stack-up is designed by consolidating all the strip-lines and micro-strip lines.

PCB Stack-up dimensions are shown in Table 1. MultilayerPCB board design is considered in this paper. A 16 layer PCBstack-up is designed well for the board in order to meet thecontrolled impedance. The same parametric values are usedfor the further simulations of our work in this paper.

3 S- Parameter Analysis

3.1 Cross-Talk Analysis

The traces may pick up noise from fringe fields and that con-tributes to a crosstalk. The differential crosstalk would beminimized if the interconnects will maintain differential spac-ing. S-parameter analysis is performed to find the crosstalk.Differential signals are widely used in Ethernet, in the smallcomputer scalable interface (SCSI) bus, in many of the tele-communication optical-carrier (OC) protocols and for com-munications in general over twisted pairs. A Low-VoltageDifferential Signal (LVDS) is one of the familiar signalingschemes used in this paper.

Fig. 5 a S-Parameters curve forDifferential Via Case 0. bImpedance curve for DifferentialVia Case 0

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The most important downside of differential signals is tocreate electromagnetic interference (EMI). If the differentialsignals are not properly balanced or filtered, there is a possi-bility of the presence of a common signal. Then, there may bereal differential signals that are driven on external twisted-paircables to cause EMI problems. The second downside is totransmit a differential signal and it requires twice the numberof signal lines so as to transmit a single-ended signal. The thirddownside is that there are many new principles and a few keydesign guidelines to understand differential pairs. Due to thecomplicated effects in differential pairs, there are many mythsin the industry which have needlessly complicated their de-sign. In our work, effectively four transmission lines with

eight port configuration is considered. Each two transmissionlines in the port is treated as a differential pair. In Fig. 1,SDD11 indicates the differential Return loss, SDD21 indicatesthe differential insertion loss, SDD31 indicates the differentialnear-end X-talk and finally, SDD41 indicates the differentialfar-end X-talk.

The crosstalk simulation set-up is designed with two dif-ferential pairs connected from board 1 to board 2 through aconnector backplane. All the ports are terminated with 100 Ωdifferential terminations. The PCB stack is considered as perthe design in Fig. 1. The spacing between the two differentialpairs is varied in terms of multiples of trace width (1 W, 2 W,3 W, etc.,) and the near-end and far-end X-talk values are


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measured in dB, which is shown in Fig. 2. As per the inter-connect specifications, the attained near end crosstalk is -26 dB and far end crosstalk is -40 dB maximum. Table 2shows the near end and far end crosstalk values for differentspacings.

The near end and far end crosstalk as per the specification(−26 dB for near end and − 40 dB for far end X-talk) is satis-fied only for spacing greater than 3 W spacing. So the pair topair separation should be greater than 3 W minimum.

3.2 Effects of Surface Roughness and Insertion Loss

While considering the surface roughness of copper conductoris small, the current will flow through the contours of the

surface and will lead to increase in the distance of current flowas well as increases the resistance. Hence, the smaller skindepth of d than copper surface roughness at very high frequen-cies is considered in this paper. Figure 2 shows the variation ofattenuation with respect to frequency roughness values whichis in μm. It shows that the surface roughness is increased atlower frequencies will lead to increase in attenuation. At highfrequencies such as 1GHz, the surface roughness is less andattenuation is also less. It is found that below 1GHZ, the sur-face roughness attenuation is insignificant. The attenuationwill be noticed from below the hundreds of MHz and theroughness value of copper is 7 to 9 μm, VLP foil is 3 to4 μm and HVLP foil is 1.5 to 2 μm.The simulation setup isconsidered by sweeping roughness values and keeping the


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trace length constant at 15 in.. The results are shown in Fig. 2.The value 0 μm roughness is the smooth copper for which theinsertion loss is very low. As roughness increases,SDD21(dB) is becoming worse and signal attenuation ismore. According to the standard, SDD21(dB) attained6.6 dB at 3.1 GHz and 12 dB at 5 GHz. So, for a 15″ channelmaximum allowed roughness value is only 3.5 μm.

Another simulation is performed by sweeping length andkeeping roughness value constant at 7 μm. The results areshown in Fig. 3. If channel length is greater than 15,000 milsor 15 in., SDD21 will be more than 6.6 dB. If we are usingcopper with the roughness of 7 μm which is commerciallyavailable in the market and comparatively cheaper thansmooth copper, the channel length is limited to 10 in.. So,

there is always a trade-off between Channel length (in inches)and Roughness (in μm).

4 Via Optimization

4.1 Differential Via Modeling

PCB designers have often failed to notice the source of chan-nel discontinuity in the signal Via. Eye openings will be re-duced by Via’s as it will cause data misinterpretation of thereceiver. Via needs to be optimized and designed carefully fora smooth transition and transparently to faster edge rates. Inorder to analyze the behavior of Via’s in an effective manner,


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geometric structures are considered and the frequency domain(S11 and S21) and TDR results are processed and illustrated inthis paper.

4.2 TDR Analysis

Directly from the TDR response, we can make out the natureof the discontinuity (inductive or capacitive) and impact (inohm). A typical rising signal has been applied to each Viamodel through an ideal 50 Ω transmission line with a delayof 0.778 ns (6 in.) after and before Via model. Incorporation ofideal transmission line models avoids any signal distortionand the effect of the analyzed Via is included. As a non-

ideal element, Via’s exhibits a discontinuity and it has ashoot-bounce decreasing behavior. The observed shoot haspositive values (overshoot) or negative values (undershoot).From signal integrity theory, it is known that this behavior isclosely tied to a dominant capacitive (inductive) behavior ifundershoot (overshoot) is observed. Inductive behavior andcapacitive behavior are analyzed using TDR and plotted inFig. 4 which shows impedance on the y-axis and time on thex-axis for different cases. In cases C4, C17 have maximumpositive and negative overshoots occurred and C9 close to50Ω impedance. Any discontinuity after the first transmissionline will have impedance mismatch and the reflected signalwill travel to reach the port 1 after 1.556 ns. Directly from the


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TDR response, we can make out the nature of the discontinu-ity (inductive or capacitive) and impact (in ohms).

Table 3 shows the TDR set-up parameters for differentcases which were used in this paper.

4.3 Simulation Set-up and Results

PCB stack-up is designed using a PCB design simula-tion tool. We designed a 16 layer PCB with the follow-ing parameters

Frequency Plan: 0 to 15 GHz (As fundamental frequencyis 3 GHz, Considered up to 5 harmonics).

Arc Resolution: 10 degrees (For circular shaped Viapads).Mesh Density: 60 cells per wavelength.Matrix solver: direct dense.

All Transmission lines and Via’s are considered as3D distributed. Layout is drawn in the Via-utility ofthe tool. The simulation is performed using a momen-tum microwave simulator and exported to the schematicwindow for doing S-parameter analysis and TDR.

Simulation results were taken for differential via returnloss, insertion loss and impedance variations with respect tofrequency and time.


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Figures 5a, b shows return loss attained in case 0 is−17.273 dB at 3.1GHz and Via impedance is in capacitivenature at anti pad diameter 30 mil.

Figure 6a, b shows return loss attained in case 1 is−24.781 dB at 3 GHz frequency and the impedance value isslightly moving in upward direction.

Figure 7a, b, shows the capacitive impedance at constantanti pad diameter is 30mils, drill diameter is 8mils, pad diam-eter is18mils and separation between differential via’s is40mils.

From Figure 8, b, it is noticed that the anti pad diameterincrease from 30mil to 40mil and − 35.064 dB return loss isobtained at 3GHz frequency. It is found that impedance valueis close to inductive nature.

It is observed from Fig. 9a, b that impedance valueat t1 time becomes changed from capacitive to inductiveas anti pad diameter increases and at the same timereturn loss decreases.


Table 4 TDR results

Sl. No. Anti-pad Type Antipad Size (mil) Return-loss (dB)

1 Circular (with NFP’s) 30 −17.2732 Circular (without NFP’s) 30 −24.7813 Oblong 30 −29.124 Oblong 40 −35.065 Oblong 45 −33.776 Oblong 50 −31.357 Oblong 60 −27.69

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From Figures 10, b and 11a, b, it is noticed that return lossdecreases as the anti pad diameter increases and it shows theinductive impedance.

From Table 4, it is observed that initially, the Via is incapacitive nature (from TDR results). After 40 mil anti-pad,the return loss starts to increase again, means it is becominginductive. Anti-pad size 40 mil gives the best return loss valueand fits our channel.

4.4 Total Channel S-Parameter Analysis

The following parameters are considered for set-up:

Stack up used: As per designed stack-up (which isexplained in Section 2)

Differential pair trace width: 3.5 mil (as per PCB stack updesigned)P and N spacing: 6.5 mil (as per PCB stack up designed)Pair to Pair spacing: 14 mil (as per crosstalk simulation inSection 3)Roughness: 7um (as per roughness simulation inSection 3)Differential Via: used as per case 0,1,3 which is simulatedin the optimization of differential Via (Section 5).

5 Ibis Ami

The transmitter and receiver are demonstrated as Input BufferInformation Specific (IBIS) models. Multi-gigabit serial links

Fig. 12 a S(1,1) andS(2,1)-parameters simulation forwhole channel with Circularanti-pad (NFPs Not removed)Differential Via. b S(3,1) andS(4,1)-parameters simulation forthe whole channel with Circularanti-pad (NFPs Not removed)Differential Via

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Fig. 13 a Eye diagram at thetransmitter for the whole channelwith Circular anti-pad (NFPs Notremoved) Differential Via. b Eyediagram at receiver for the wholechannel with Circular anti-pad(NFPs Not removed) DifferentialVia. c Eye diagram afterequalization for the wholechannel with Circular anti-pad(NFPs Not removed) DifferentialVia

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need to pass heavy data traffic to produce enough number ofsamples needed for making reliable eye diagrams to accurate-ly predict BER. IBIS-AMI is the extension made to IBIS in2007 [9]. It enables executable, software-based, algorithmicmodels to work together with traditional IBIS circuit models.It enables SerDes adaptive equalization algorithms to bemodeled and used during channel simulation. IBIS-AMI en-ables plug-and-play simulation compatibility between SerDesmodels from different suppliers, in a standard commercialEDA format.

5.1 IBIS AMI Simulation Results and Discussions

5.2 Case a: S-Parameter Simulation for the WholeChannel with Circular Anti-Pad (NFPs Not Removed)Differential Via

The simulation results in Fig. 12a shows that −12.709 dBreturn loss and − 7.266 dB insertion loss is attained at the3.1GHz frequency.

The simulation result of Fig. 12b shows the near-endcrosstalk as −49.771 dB and far end crosstalk as−55.107 dB.

The eye diagram is shown in Fig. 13a, b and c and bathtubcurve is shown in Fig. 14a, b, c and d for the whole channelwith Circular anti-pad (NFPs Not removed) Differential Via.The eye width is 101.1 ps and the height is 173 mVat receiverand after equalization, eye width is 122.3 ps and height is300 mV.

5.3 Case B: S-Parameter Simulation for the WholeChannel with Circular Anti-Pad Via

Similarly, the same simulation procedure is followed for CaseB also, in which NFPs are present in whole channel withCircular anti-pad Via. The simulation results are plotted forcase B.

Figure 15a showed that channels return loss decreases to−21.157 dB as compared to case-A at same 3.1 GHz operatingfrequency with the allowable loss.

There is no notable variation, the near end crosstalk is−49.563 dB and far end crosstalk is −54.581 dB and is shownin Fig. 15b.

Channel with Circular anti-pad Via eye diagram at thetransmitter, receiver and after equalization results are shownin Fig. 16a, b and c. It is shown that eye height increases to

�Fig. 14 a Voltage Bath-tub curve at probe 2 for the whole channel withCircular anti-pad (NFPs Not removed) Differential Via. b Voltage Bath-tub curve at probe 1 for the whole channel with Circular anti-pad (NFPsNot removed) Differential Via. c Timing Bath-tub curve at probe 2 for thewhole channel with Circular anti-pad (NFPs Not removed) DifferentialVia. d Timing Bath-tub curve at probe 1 for the whole channel withCircular anti-pad (NFPs Not removed) Differential Via

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183 mV with width 103.8 ps at receiver and small variation isobserved in height and width after equalization.

Figures 17a, b, c and d indicated voltage and timing bath-tub curves for the whole channel with Circular anti-pad Via.

5.4 Case C: S-Parameter Simulation forWhole ChannelOptimized Differential Via

Similarly, the same simulation procedure is followed for CaseC i.e., for the whole channels optimized Differential Via. Thesimulation results are plotted for case c.

In S- parameter simulation, the observed S11 value is−26.132 dB. Hence, there is a better return loss when theconstant insertion loss is maintained at the same 3.1GHz op-erating frequency and is shown in Fig. 18a.

Near-end crosstalk decreases to −50.115 dB and far-endcrosstalk increases and is shown in Fig. 18b.

Eye diagram for the whole channel optimized DifferentialVia at the transmitter, at the receiver, and after equalization isplotted in Fig. 19a, b and c respectively. It is seen that eyeheight and widths varied at receiver and equalization for thewhole channel optimized Differential Via. Voltage Bath-tubcurve for the whole channel optimized Differential Via atprobe 2 and at probe 1 is shown in Figs. 20a, b respectively.Timing Bath-tub curve for the whole channel optimizedDifferential Via at probe 2 and at probe 1 is shown in Figs.20c, d respectively.

5.5 Discussion

Crosstalk really did not changemuch as the setting for spacingin three simulations did not change and is meeting the speci-fication. But there is a severe problem when it comes to returnloss. From Table 5 return loss is very high in case A and the

Fig. 15 a S(1,1) and S(2,1)-parameters simulationfor wholechannel with Circular anti-padVia. b S(3,1) and S(4,1)-parame-ters simulation for the wholechannel with Circular anti-padVia

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Fig. 16 a Eye diagram at thetransmitter for the whole channelwith Circular anti-pad Via. b Eyediagram at receiver for the wholechannel with Circular anti-padVia. c Eye diagram afterequalization for the wholechannel with Circular anti-padVia

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best value is given by case C. So, Via optimization is reallyimproving the return loss and helping in meeting the specifi-cation. After channel results are shown in Table 6, the signif-icant improvement in eye height as the channel is optimized.However there is nomuch improvement in width. After equal-ization results show that even if the channel is bad it can beimproved by equalization and both eye height and width areimproved in three cases. But the best channel is case C.

6 Conclusion

A 16 layer PCB stack-up is designed well for the board inorder to meet the controlled impedance. The same is usedfor the differential crosstalk measurement. The pair to pairseparation was maintained at a value greater than 3 W to getminimum crosstalk and the observed trade-off betweenChannel length (in inches) Vs Roughness (in μm). The layoutis drawn in the Via-utility of the tool. The proposed method issimulated using a momentum microwave simulator andexported on to the schematic window for doing S-parameteranalysis and obtaining the TDR results. The transmitter and

Fig. 17 a Voltage Bath-tub curve at probe 2 for the whole channel withCircular anti-pad Via. b Voltage Bath-tub curve at probe 1 for the wholechannel with Circular anti-pad Via. cTimingBath-tub curve at probe 2 forthe whole channel with Circular anti-pad Via. d Timing Bath-tub curve atprobe 1 for the whole channel with Circular anti-pad Via

Fig. 18 a S(1,1) and S(2,1)-parameters simulation for whole channeloptimized Differential Via. b S(3,1) and S(4,1)-parameters simulationfor the whole channel optimized Differential Via

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Fig. 19 a Eye diagram at thetransmitter for the whole channeloptimized Differential Via. b Eyediagram at receiver for the wholechannel optimized DifferentialVia. c Eye diagram at afterequalization for the wholechannel optimized DifferentialVia

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receiver are modeled as Input Buffer Information Specific(IBIS). Anti-pad size of 40 mil is found to be giving the bestreturn loss value that fits our channel.

Optimized differential via analysis of all S-parameters re-sulted in return loss of - 26.132 dB, insertion loss of−6.646 dB, near end crosstalk of −50.115 dB and far endcrosstalk of 54.906 dB respectively. Similarly, afterequalization, Eye diagram and bathtub analysis havebeen performed to observe the BER plots and the Eyeheight and widths are found to be 303 mV and 124.6 psrespectively indicating that the proposed model is suit-able for high-speed data rate requirements. Further, themodel can be extended up to 40 layers PCB from theproposed 16 layer and can be synthesized with availableCAD tools in the market.

References

1. D. N. de Araujo, M. Cases, D. Kuchta, C. Baks, Y. Kwark,“Electrical Optical High-Speed Serial Server Scalability Link”,Proceedings of IEEE 56th Electronic Components andTechnology Conference, June 2007.

2. C. Chastang, C. Gautier, A. Amedeo, F. Costa THALES “CrosstalkAnalysis ofMultigigabit Links on High Density Interconnects PCBusing IBIS AMI Models”, Proceedings of IEEE Electrical Designof Packaging and Systems Symposium, February 2013.

3. Kai-Bin W, Lin C-Y, Huang S-Y, Ruey-Beei W (January 2016)Design of Stackup and Shorting Vias and for Reducing EdgeRadiation in Multilayer PCB. Proceedings of IEEE ElectricalDesign of Packaging and Systems Symposium

4. Gabriel Mounce, Jim Lyke, Stephen Horan, Rich Doyle, RafiSome, “Chiplet Based Approach for Heterogeneous Processingand Packaging Architectures” Proceedings of IEEE 56th

Electronic Components and TechnologyConference, 30 June 2016.

Fig. 20 a Voltage Bath-tub curve at probe 2 for the whole channeloptimized Differential Via. b Voltage Bath-tub curve at probe 1 for thewhole channel optimized Differential Via. c Timing Bath-tubcurve at probe 2 for the whole channel optimized DifferentialVia. d Timing Bath-tub curve at probe 1 for the whole channel optimizedDifferential Via

Table 5 Cases conclusions

Case Para meters A B C

Insertion Loss(dB) −7.266 −6.768 −6.646Return Loss (dB) −12.709 −21.157 −26.132Near End X-Talk (dB) −49.771 −49.563 −50.115Far End X-Talk (dB) −55.107 −54.581 −54.906

Table 6 Channel conclusion

Case After Channel After Equalization

EyeHeight(mV)

Eye Width(ps)

Eye Height(mV)

EyeWidth(ps)

A 173 101.5 300 122.3

B 183 103.8 296 124.6

C 190 101.5 303 124.6

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https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10951

https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10951

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16. Howard Johnson,Martin Graham, “High-speed signal propagation:Advanced Black Magic” 1st Edition, Prentice Hall, Febraury 2003.

A. Kavitha is currently working as Professor, Department of Electronicsand Communication Engineering, Veltech Multitech Dr. Rangarajan andDr. Sakuntala Engineering College, Chennai, Tamilnadu. She has com-pleted Doctor of Philosophy in Information and Communication

Engineering at Anna University, Chennai. She has completed Master ofEngineering in Computer and Communication from Periyar ManiammaiCollege of Engineering and Technology, Vallam, Anna University,Chennai and Bachelor of Engineering in Electronics andCommunication from PSNA College of Engineering and Technology,Dindigul, Kamaraj University, Madurai. She is marching towards17thyear of the Teaching Profession. She has published her work in 14refereed National and International journals and 20 National andInternational conference proceedings. She is an active reviewer forInternational Journal of Electronics and in various IEEE Conferencesaround the world. She is one of the Editorial and review board membersin International Journal of Research in Engineering and Technology. Sheis the lifetime member in Indian Society for Technical Education. She hasworked as Publication chair for IEEE Sponsored ICCCA-2012(International Conference on Computing, Communication andApplication), chaired a Special session in INDIACOM 2015 and CSI2015, National Conference on Information Communication andComputing and Internat ional Conference on Computing,Communication and Application.

Ch. Sekararao Kaitepalli received Bachelor of technology from JNTUHyderabad in the year 2008; Master of technology from AndhraUniversity, Andhra Pradesh in the year 2012 and doing Ph.D. in AnnaUniversity, Chennai. Life member of ISTE. His area of expertise includesRF antenna design and communication system modeling.

J.N. Swaminathan has received the B.E. Degree from Anna University,Chennai and the M.Tech. Degree from Sastra University, Thanjavur. Hehas completed Doctor of Philosophy in Information and CommunicationEngineering at Anna University, Chennai and done his research in PowerAmplifier Modeling. He is currently working as Professor in theDepartment of Electronics & Communication Engineering at GodavariInstitute of Engineering and Technology, Rajamundry. He has publishedhis work inmany refereed International journals and Conference proceed-ings. He is an active reviewer for Wireless Personal Communication(Springer), Guest editor for many scopus indexed journals and in variousIEEE & springer conferences around the world. His area of interestsincludes Device Modeling and OFDM. He has chaired a Special sessionin INDIACOM 2015, CSI 2015. He is lifetime corporate member inIETE and GISFI India. He is a volunteer and member of IEEE andIEEE COMSOC.

Shaik Ahemedali received Bachelor of technology from JNTUKakinadaUniversity in the year 2010. Master of technology from SathyabamaUniversity in the year 2013 and doing Ph.D. in VisvesvarayaTechnological University, Karnataka. Life member of ISTE. His area ofinterest includes Low power circuit designs and communication systemdesign. Working as an Assistant Professor in Sasi Institute of Technology& Engineering.

Publisher’s Note Springer Nature remains neutral with regard to juris-dictional claims in published maps and institutional affiliations.

J Electron Test (2019) 35:497–517 517

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