6.776 Laboratory 2 Report

Rachel Chaney and Daniel Vickery

May 12, 2010

1 Introduction

In this report we describe the construction and evaluation of a fractional-N synthesizercontrolled by a Σ∆ modulator. Sections 2 and 3 detail the design and construction of aninteger-N synthesizer, and Section 4 covers the addition of a 4-bit Σ∆ modulator to completethe fractional-N synthesizer. In Section 5, we describe our improvement to the synthesizer,which expands the Σ∆ modulator to 5 bits, allowing for either doubled range or doubledfrequency resolution.

2 VCO and Output Buffer

The voltage-controlled oscillator (VCO) is designed using a 74LS628 IC, and configured tobe able to synthesize all frequencies from 5MHz to 10MHz within an input range of 1.4V to3.6V. This input range constraint comes from the LF353 operational amplifier used in ourphase-locked loop (PLL) filter, which internally contains two base-emitter junctions betweeneither rail and the output. Because we are using a 5V power source with no negative supplyrail, these limit our output swing to the aforementioned range.

Our 74LS628 is configured with a 15pF capacitor, Cext and a 590Ω resistor, Rext. Therange configuration pin is tied to the 5V supply rail. A full schematic of the VCO configu-ration is given in Appendix A.

Figure 1(a) shows a VCO range plot taken from the 74LS628 datasheet. The very lowestline corresponds closely to our configuration, the only discrepancy being a 10Ω differencein the resistance of Rext. We found in our experience that this plot did not reflect thebehavior of the VCO well, as shown by a similar plot of experimental data in Figure 1(b)that demonstrates that the configuration suits our purpose in practice. We attribute thediscrepancies between the two plots to chip variation and datasheet inaccuracy.

Finally, the VCO must be capable of cleanly driving a 50Ω load (the sprectrum analyzerinput). For this purpose we implemented a simple 2N3904-based NPN emitter-follower bufferdriven by the complementary output of the 74LS628. We use the complementary outputbecause phase is not a concern in our measurements on the spectrum analyzer. We size theemitter resistor at 50Ω not for matching purposes, but coincidentally because this sets thecollector current of the NPN device conservatively below its maximum rated value (200mA)

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SN54LS624 THRU SN54LS629,SN74LS624 THRU SN74LS629

VOLTAGE-CONTROLLED OSCILLATORS

SDLS186 – JANUARY 1980 – REVISED MARCH 1988

7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(a) Listed Range

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 52

4

6

8

10

12

14

16

Output Voltage vs Frequency−Control Input Voltage (R=590Ω, C=15pF, Vrange

=5)

VI(freq)

= Frequency−Control Input Voltage (Volts)

f o = O

utpu

t Fre

quen

cy (

MH

z)

(b) Measured Range

Figure 1: Plots of the VCO range with respect to input frequency. Plot (a) shows thepredicted response from the 74LS628 datasheet, and plot (b) shows our demonstrated results.

when its base is driven with a 5V pulse:

IC <5V

50Ω||50Ω= 200mA (1)

Output spectra of the VCO are shown in Figure 2.

3 Phase-Locked Loop

The Phased-Locked Loop (PLL) is implemented with the MC145151-P2 IC. Its design pri-marily consists of the loop filter, while the rest is mostly setting programming parameters onthe chip. A full schematic of the PLL configuration, including the generation of its referencefrequency from a crystal oscillator, is provided in Appendix A.

A block diagram of the PLL (and complete DIP-switch-controlled integer-N synthesizer)is shown in Figure 3. The loop filter transfer function is indicated by H(s). The VCO gainKO is given by df

dVinwhich is roughly 2.6, according to the data shown in Figure 1(b). The

phase detector gain, KD, is a linearization of the discrete output of the phase detector. Inthe case of the single-ended tri-state output PD that we use, this is 2.5, given that the tri-state output is held at 2.5V when in the “high impedance” state. This linearization comesfrom the fact that for a positive phase difference the output jumps up 2.5V to 5V, and fora negative phase difference, it falls to 0V.

Thus, the loop transfer function is:

L(s) =KOKDH(s)

Ns(2)

A bode plot of the uncompensated open-loop system (H(s) = 1) is shown in Figure 4(a).

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(a) 75MHz Span (b) 30MHz Span

Figure 2: Plots of the VCO output spectrum, recorded from the 6.776 lab spectrum analyzer.Both plots are centered at 0Hz, but plot (a) has a 75MHz span, while plot (b) has a 30MHzspan.

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Figure 3: Block diagram of phase-locked loop synthesizer.

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−20

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20

40

60

80

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dB)

102

103

104

105

106

107

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−90.5

−90

−89.5

−89

Pha

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deg)

Bode Diagram of Uncompensated Loop Transfer (N=8)

Frequency (rad/sec)

(a) Uncompensated PLL

−150

−100

−50

0

50

100

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dB)

102

103

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105

106

107

−180

−150

−120

Pha

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deg)

Bode Diagram of Compensated Loop Transfer (N=8)

Frequency (rad/sec)

(b) Compensated PLL

Figure 4: Bode plots of the uncompensated and compensated loop transfer function of thePLL.

3

to increase the high frequency attenuation. If this pole is placed beyond the loop crossover frequency, therewill be negligible change in the FM step response, except that the high frequency teeth will be removed.

Now try increasing the FM frequency deviation so that the loop breaks lock. Note the response at thephase comparator output and VCO input.

2.2 XOR Phase Detector

What happens if you substitute phase comparator I (an exclusive-or gate) for phase comparator II in thelag compensated PLL described in Part 2.1? You should be able to answer this question theoretically andexperimentally. Specifically, what is the phase detector gain KD, the loop bandwidth, the phase margin, thesteady state phase error, the lock range, and the ease of acquiring lock (experimentally)?

Note: if you have di!culty in acquiring lock, try slowly scanning the input frequency until the circuitlocks. Will this circuit lock on harmonics? Is the circuit duty cycle sensitive?

3 Active Filters

Return to the lag compensated PLL using phase comparator II as in Part 2.1. Apply a FM modulatedinput to observe the step response as before. Look at the output of the phase comparator (pin 13). Thesteady state phase error and dynamic tracking error should be apparent if you mentally average out the highfrequency components4. Try varying the input frequency range.

Active filters are used to reduce this tracking error. A possible active filter PLL realization is illustratedin Figure 4.

PHASE

COMPARATOR I

PHASE

COMPARATOR

II

COMPARATOR

IN

SIGNAL

IN

VCO

SOURCE

FOLLOWER

DEMODULATOR

OUT

VCO IN

PHASE PULSES

PHASE COMP II OUT

PHASE COMP I OUT

VCO

OUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

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+5

R2

R1

C

+5V

C1

10k!

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+

C2

R3

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10k!

10k!

10k!

+5V

10k!

R4

Figure 4: Active loop filter

Certain precautions must be taken when such filters are used. The opamp can easily supply voltagesto the 4046 that will burn it out. For this reason, it is a good idea to diode clamp the inputs to the PLL

4Note: If you find mental averaging unsatisfying, filtering vD with a simple passive RC filter with RC = 0.1 ms will giveyou a picture of the average value of the phase error. To avoid loading the phase comparator with a low impedance, make theresistor R a large value (1M! is fine). IMPORTANT: this filter is not in the loop, it is between the phase comparator outputand the scope.

4

Figure 5: Loop filter simplified schematic.

The loop filter design is important because it determines both the stability and closed-loop bandwidth of the PLL. Our design specification is to have zero steady-state error. FromEquation 2, we find the phase error:

φe

φref

=1

L(s) + 1=

Ns

KOKDH(s) +Ns(3)

Integrating, we get the phase error with respect to frequency:

φe

ωref

=N

KOKDH(s) +Ns(4)

The final-value theorem states that our steady-state error is thus:

ess, φeωref

= lims→0

Ns

KOKDH(s) +Ns(5)

This indicates that in order to have a zero steady-state error, our loop filter must containan integrator. While an integrator satisfies our steady-state error specification, it brings thephase of the loop transfer function down to −180 across all frequencies. We mitigate thisby implementing a combination of an integrator and lead compensator in our loop filter.

A schematic of the loop filter is shown in Figure 5. It is implemented with an LF353dual op-amp IC. The transfer function of the loop filter, assuming ideal op-amps is:

H(s) =sR3(C1 + C2) + 1)

sC1R4(sC2R3 + 1)(6)

The two capacitors C1 and C2 control the spread of the pole and zero and therein the phasebump. R3 can be tuned to move the position of the phase bump in frequnecy, and R4 adjuststhe gain to set ωc appropriately.

Our choice of ωc is important in this system because as we lower the closed-loop band-width, we also reduce phase noise, as more attenuation is applied to the dithering of thefrequency divider bits, N0−3. We choose to set the crossover frequency at about 2kHz, which

4

Figure 6: Plot of the phase difference between the PLL reference frequency measured atOSCin (top trace) and the VCO output frequency (bottom trace). The PLL is configuredto run at 5MHz.

is well beyond a decade below the clock frequency of the Σ∆ modulator, 625kHz, but highenough to avoid the use of large electrolytic capacitors which have poor high frequency char-acteristics. We set our final component values to: C1 = 150nF, C2 = 15nF, R3 = 1.8kΩ, andR4 = 100kΩ. The loop transfer function of the compensated system is shown in Figure 4(b).

We measure the phase-error of our constructed PLL by comparing the phases of thereference frequency and the output of the VCO. A plot of these waveforms with the PLLset to operate at 5MHz is shown in Figure 6. As depicted in the figure, the phase error isnearly zero. The slight offset is on the order of nanoseconds and can largely be attributedto propagation delay from the point of measurement to the phase detector.

We measure the closed-loop bandwidth of our constructed PLL by replacing the inputreference oscillator with a series of FM steps, and monitoring the response at the output ofthe loop filter. We can make a rough estimate of closed-loop bandwidth by approximating:

tr =2.2

ωh

(7)

Where tr is the 10%-to-90% rise time of the step response, and ωh is the closed-loop band-width of the PLL in radians per second.

Our test signal is a 5V 7.5MHz square wave frequency modulated with a step functionat 15Hz, using a 1MHz FM deviation. The response measured at the output of the loopfilter is shown in Figure 7. It is worth noting that this step response does not resemble thecanonical second-order step response well, and there does not appear to be any measurableovershoot or oscillation. We measure tr at roughly six milliseconds which corresponds to abandwidth of 60Hz. This is significantly below our predicted estimate, is still well below theclock frequency of the Σ∆ modulator.

5

Figure 7: Plot of the step response of the PLL to a 1MHz FM step, measured at the outputof the loop filter.

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Figure 8: Block diagram of Σ∆ modulator. Additional 5-bit logic chain not shown.

6

4 4-bit Σ∆ Modulator

The standard four-bit sigma-delta modulator was implemented using two 74LS181 arithmeticlogic units and one 74LS174 DQ Hex flip-flop. A block diagram of the modulator is shownin Figure 8. The full circuit schematic for the final five bit sigma delta modulator, which isslightly different than the four bit one discussed here, is shown in Appendix A.

The first adder is implemented as an ALU that is configured as a combinational two’scomplement active-high adder. We choose to configure the ALU as an adder for simplicity,and facilitate negative feedback by inverting the sign of the feedback signal at the integrator.The reference input word is a non-negative value manually entered using the DIP switchesand the feedback input word is a value that corresponds to the sign of the integrator output.In the case that the integrator output is positive, indicating that the frequency of oscillationis less than the desired value, the feedback term is 0d = 0000b. In the case that the integratoroutput is negative, indicating that the frequency of oscillation is greater than the desiredvalue, the feedback term is −7d = 1001b. The use of these two feedback terms ensures thatit is impossible to create an overflow condition in the subtractor, because the input from theDIP switch will always be greater than or equal to zero.

The integrator is implemented with an ALU configured as an adder that sums the errorsignal and the previous integrator output, which is stored on the DQ flip-flop. The clock ofthe flip-flop runs at 625kHz, which is created by dividing the output of the crystal oscillatorusing a binary counter.

The output of the sigma delta modulator is the sign of the integrator output (activehigh). This value is inverted, then sent to the least significant bit of the N input on the PLL,while bits N1−2 are grounded and N3 is tied to 5V. Thus, the duty cycle of the inverted signbit commands the desired fractional multiplier of the PLL to generate an output frequencybetween 8/8 and 9/8 of 5MHz. To give an example, in the case of an input word of 0000b,the integrator output will never become negative, so its output will always be high. SinceN0 is the inverted integrator output, it will always below, and the PLL output frequencywill remain at 8/8 · 5MHz = 5MHz.

Because we are controlling only N0, the range maximum is 9/8 · 5MHz = 5.625MHz.With a 3-bit input word, the resolution of the Σ∆ modulator is 5MHz

56≈ 89kHz.

A full spectral analysis of the output of the Σ∆-controlled synthesizer is given for the5-bit version in Section 5.

5 5-bit Σ∆ Modulator

When choosing our design improvement, we sought to find an improvement that would beeffective, but could still be implemented easily without making drastic changes to the existingcircuit. Our choice to expand the Σ∆ modulator to five bits is motivated by this desire, as itcan double either the range or resolution of the existing PLL using the existing discretizer,and it can be implemented using only two 14-pin 7400-series logic ICs. It connects with theoriginal 4-bit logic chain at only three points.

The 5-bit sigma delta modulator is implemented by adding a 74LS00 Quad NAND IC anda 74LS86 Quad XOR IC to the existing digital logic chain. These logic chips are configured

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Figure 9: Half-adder schematic and truth table.

S[0]

B[0]

Bit

Adde

r

A[0] CarryS[0]

S[1:4]

1B

HalfA

r

A[0:4] A[1:4]S[1:4]

CarryoutB[0:4]

4Bit

Adde

r

B[1:4]

4Full

Figure 10: Half-adder schematic and truth table.

as half-adders and are used to compute the least significant bits in the logic chain. The logicproperties of the half adder are shown in Figure 9. By connecting the Carry-Out bits of thehalf adders to the Carry-In bits on the ALUs, the 4-bit adders from the original circuit areeasily converted to 5-bit adders with minimal modification. A block diagram of the entire5-bit Σ∆ system is shown in Figure 10.

In the 5-bit system, the feedback values corresponding to the integrator output signare changed to reflect the new increase in range. When the integrator is negative, thefeedback value is 0d=00000b and when when the integrator is positive, the feedback valueis -15d=10001b. This set of feedback values provides the same benefit as before; we don’tneed to worry about overflow in the error signal.

The 5-bit arithmetic can be used either to increase the output frequency range of thesynthesizer while retaining the same resolution or to retain the same range and increaseresolution. If the inverted sign bit, with pulse density corresponding to desired fraction,is connected to the least significant bit in the N input on the PLL, the range of outputfreuencies is 5MHz to 5.625MHz while the resolution increases to about 45kHz. In contrast,if the inverted sign bit is connected to the N1 and N0 is tied low, the range of outputfrequencies increases to 5MHz to 6.25MHz, while the resolution stays at about 89kHz..

A plot showing measured achievable frequencies is shown in Figure 11, demonstratingvery good precision and linearity.

Plots of the output spectrum of the synthesizer controlled by the 5-bit Σ∆ modulator isshown in Figure 12. Phase noise measurements are given in Table 1. At 5MHz (modulatornot used), spurs can be seen at seven evenly spaced frequencies between 5MHz and thesecond harmonic at 10MHz. These spurs are the so-called “reference spurs” that result fromfeedthrough and up-modulation of our PLL reference frequency (625kHz). Their magnitudesare given in Table 2. As would be expected, spurs closer to the synthesized frequency have

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0 5 10 155

5.5

6

6.5

Syn

thes

izer

Out

put F

requ

ency

(M

Hz)

Input Data Word From DIP

Frequency Range and Resolution, 5−bit Σ∆

Figure 11: Frequency range and resolution of 5-bit Σ∆ modulator fractional-N synthesizer.

Offset Phase Noise1kHz -13dBc/Hz10kHz -73dBc/Hz100kHz -99dBc/Hz

Table 1: Synthesizer phase noise measurements at a center frequency of 5MHz.

DIP = 0b00000 DIP = 0b00001 DIP = 0b00011Spur Magnitude Spur Magnitude Spur Magnitude5.625MHz -55dBm 6.251MHz -66dBm 5.881MHz -59dBm6.250MHz -69dBm 7.629MHz -62dBm 6.508MHz -58dBm6.875MHz -63dBm 9.007MHz -62dBm 7.003MHz -60dBm7.500MHz -63dBm 7.883MHz -61dBm8.125MHz -65dBm 8.752MHz -67dBm8.750MHz -72dBm 9.258MHz -62dBm9.375MHz -10dBm 10.006MHz -58dBm

Table 2: Spur data for 5-bit Σ∆ modulator synthesizer at three input settings.

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(a) fout = 5MHz (b) fout = 5.0893MHz

(c) fout = 5.2679MHz (d) fout = 5.625MHz

Figure 12: Spectra plots of the synthesizer output using the 4-bit and 5-bit Σ∆ modulator.Plots (a)-(c) correspond to input words 0b00000, 0b00001, 0b00011 respectively on the 5-bitmodulator, plot (d) corresponds to an input word of 0b0111 on the 4-bit modulator.

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higher power levels due to the addition of heavy phase noise near the center frequency.When the Σ∆ modulator is used (DIP word is positive) we continue to see reference

spurs, but the undesired power in our spectrum is dominated by fractional spurs caused bythe rapid change in phase error as a result of the pulsing of N1 (or N0, as the case wouldbe in the 4-bit Σ∆). These spurs consequently appear in smaller intervals corresponding tothe resolution of the synthesizer (in our case, ≈ 89kHz). The magnitudes and frequencies ofsome of the biggest spurs in a few example DIP settings are given in Table 2, though not allare listed here.

6 Conclusion

We have designed and constructed a 4-bit Σ∆ modulator controlled fractional-N synthesizer,and expanded it to a 5-bit system, enabling either double range or double the resolution ofthe original 4-bit system. This expansion is accomplished through the use of two 14-pin7400-series logic ICs, with minimal additional wiring. Possible future improvements couldinclude additional logic designed to apply the range and resolution of the 5-bit system todifferent areas of the spectrum attainable with the PLL by varying the bits N0−3 controlledby the modulator. Such a configuration would take advantage of the simplicity of a 5-bitsystem. Other improvements could include randomized dithering to reduce spur intensity,or higher-order modulators for better noise shaping.

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A Schematics

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Figure 13: Loop Filter and VCO Schematic

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Figure 14: Arithmetic and Σ∆ Modulator Schematic

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Figure 15: Schematic of Clock References

14

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Figure 16: Phase-Locked Loop Schematic

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