2k-bit 2-wire serial cmos eeprom with permanent and ... is34c02b (rev.00e 09_2009).pdfthe is34c02b...

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1Rev. 00E09/08/09

IS34C02B

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

2K-bit 2-WIRE SERIAL CMOS EEPROMwith Permanent and Reversible Write-Protection

FEATURES

• Two-WireSerialInterface,I2CTM compatible

– Bidirectional data transfer protocol – 400 kHz transfer rate

• Organization:

–256x8-bit

• DataProtectionFeatures

–WriteProtectPin –PermanentSoftwareProtection

–ReversibleSoftwareProtection

• 16-BytePageWriteBuffer –PartialPage-writespermitted

• LowPowerCMOSTechnology

– Active Current less than 3 mA (3.6V)

– Standby Current less than 1 µA (1.7V)

– Standby Current less than 2 µA (3.6V)

• LowVoltageOperation

–IS34C02B-2:Vcc=1.7Vto3.6V

• RandomorSequentialReadModes

• FilteredInputsforNoiseSuppression

• SelftimedWritecycle(5msmax.)

• HighReliability

–Endurance:1,000,000Cycles

–DataRetention:40Years

• Industrialtemperaturerange

• 8-pin:TSSOP,UDFNandDFN

• Lead-freeavailable

ADVANCED INFORMATIONSEPTEMBER 2009

DESCRIPTION

TheIS34C02BisanelectricallyerasablePROMdevicethatusestheindustry-standardI2C communication pro-tocol.TheIS34C02Bcontainsanon-volatilememoryarrayof2,048-bits(256bytes),andisfurthersubdividedinto16pagesof16byteseachforPage-writemode.Thedeviceoperatesoverthevoltagerangeof1.7Vto3.6VtosatisfythevoltagerequirementsofDDR2,DDR1,andmanyotherspecifications.InnormalReadorWriteoperations,amasterdevicecommunicateswiththeEEPROMviathetwowiresSerialClockandSerialData.Duringapplicationsystemboot-up,itmaybenec-essary to read out the contents of the IS34C02B that pertaintotheconfigurationofaDRAMmodule.Ifthemodule manufacturer wishes to safeguard this memory content,thefirsthalfofthearraycanbewrite-protectedwith either a permanent or reversible software com-mand,ortheentirearraycanbewrite-protectedwiththeWPinputpin.TheIS34C02Bhasthreeaddresspins,allowing up to eight devices (or memory modules) to beuniquelyaccessibleinasystem.Tominimizeboardreal-estate,IS34C02Bisavailableinfollowing8-pinpackages:TSSOP,UDFNandDFN.AllthesefeaturesmakethedeviceidealforuseasaSerialPresenceDetect(SPD)EEPROMinvarioustypesofmemorymodules.

2 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00E09/08/09

IS34C02B

FUNCTIONAL BLOCK DIAGRAM

>

CONTROLLOGIC

XD

EC

OD

ER

SLAVE ADDRESSREGISTER &

COMPARATOR

WORD ADDRESSCOUNTER

HIGH VOLTAGEGENERATOR,

TIMING & CONTROL

YDECODER

DATAREGISTER

ClockDI/O

ACKGND

WP

SCL

SDA

Vcc

nMOS

A0

A1

A2

ARRAY

80H-FFH

00H-7FH

Integrated Silicon Solution, Inc. — www.issi.com 3Rev. 00E09/08/09

IS34C02B

PIN DESCRIPTIONS

A0-A2 AddressInputs

SDA SerialAddress/DataI/O

SCL SerialClockInput

WP WriteProtectInput

Vcc PowerSupply

GND Ground

SCL

Thisinputclockpinisusedtosynchronizethedatatransferto and from the device.

SDA

TheSDAisaBi-directionalpinusedtotransferaddressesanddataintoandoutofthedevice.TheSDApinisanopendrainoutputandcanbewireOr'edwithotheropendrainoropencollectoroutputs.TheSDAbus apullupresistor to Vcc.

PIN CONFIGURATION8-Pin TSSOP

WP

WPistheWriteProtectpin.IftheWPpinistiedtoVcc,theentirearraybecomesWriteProtected,andsoftwarewrite-protectioncannotbeinitiated.WhenWPistiedtoGNDorleft floating, normal read/write operations are allowed to the device.Ifthedevicehasalreadyreceivedawrite-protectioncommand,thememoryintherangeof00h-7Fhisread-onlyregardlessofthesettingoftheWPpin.

A0, A1, A2

TheA0,A1,andA2arethedeviceaddressinputsthatare hardwired or left unconnected for hardware flexibility. Whenpinsarehardwired,asmanyaseightdevicesmaybeaddressedonasinglebussystem.Whenthepinsarenot hardwired, the default values of A0, A1, and A2 are zero.

DEVICE OPERATION

The IS34C02B features a serial communication andsupportsabi-directional2-wirebustransmissionprotocolcalled I2CTM.

2-WIRE BUS

Thetwo-wirebusisdefinedasaSerialDataline(SDA),andaSerialClockline(SCL). TheprotocoldefinesanydevicethatsendsdataontotheSDAbusasatransmitter,andthereceivingdeviceasareceiver. ThebusiscontrolledbyMasterdevicewhichgeneratestheSCL,controlsthebusaccessandgeneratestheStopandStartconditions. TheIS34C02B is the Slave device on the bus.

8-pad UDFN and DFN

1

2

3

4

8

7

6

5

A0

A1

A2

GND

VCC

WP

SCL

SDA

1

2

3

4

8

7

6

5

A0A1A2

GND

VCCWPSCLSDA

(Top View)


IS34C02B

The Bus Protocol:

– Datatransfermaybeinitiatedonlywhenthebusisnotbusy

– Duringadatatransfer,theSDAlinemustremainstablewhenevertheSCLlineishigh. AnychangesintheSDAlinewhiletheSCLlineishighwillbeinterpretedasaStart or Stop condition.

ThestateoftheSDAlinerepresentsvaliddataafteraStartcondition.TheSDAlinemustbestableforthedurationoftheHighperiodoftheclocksignal. ThedataontheSDAlinemaybechangedduringtheLowperiodoftheclocksignal. Thereisoneclockpulseperbitofdata. Eachdatatransfer is initiated with a Start condition and terminated with a Stop condition.

Start Condition

TheStartconditionprecedesallcommandstothedeviceandisdefinedasaHightoLowtransitionofSDAwhenSCLisHigh. TheIS34C02BmonitorstheSDAandSCLlines and will not respond until the Start condition is met.

Stop Condition

TheStopconditionisdefinedasaLowtoHightransitionofSDAwhenSCLisHigh.Alloperationsmustendwitha Stop condition.

Acknowledge (ACK)

After a successful data transfer, each receiving device is requiredtogenerateanACK. TheAcknowledgingdevicepullsdowntheSDAline.

Reset

TheIS34C02Bcontainsaresetfunctionincasethe2-wirebustransmissionisaccidentallyinterrupted(eg.apowerloss),orneedstobeterminatedmid-stream.TheresetiscausedwhentheMasterdevicecreatesaStartcondition.Todothis,itmaybenecessaryfortheMasterdevicetomonitortheSDAlinewhilecyclingtheSCLuptoninetimes.(ForeachclocksignaltransitiontoHigh,theMasterchecksforaHighlevelonSDA.)

Standby Mode

Power consumption is reduced in standby mode. TheIS34C02Bwillenterstandbymode:a)AtPower-up,andremaininituntilSCLorSDAtoggles;b)FollowingtheStopsignalifnowriteoperationisinitiated;orc)Followinganyinternal write operation

DEVICE ADDRESSING

The Master begins a transmission by sending a Startcondition. The Master then sends the address of theparticularSlavedevicesitisrequesting.TheSlavedevice (Fig.5)addressis8bits.

ThefourmostsignificantbitsoftheSlavedeviceaddressare fixed as 1010 for normal read/write operations, and 0110forpermanentwrite-protectionoperations.

Thisdevicehasthreeaddressbits(A1,A2,andA0)thatallowuptoeightIS34C02Bdevicestosharethe2-wirebus.UponreceivingtheSlaveaddress,thedevicecompares the three address bits with the hardwired A2, A1, and A0 input pins to determine if it is the appropriateSlave.IfanyoftheA2-A0pinsisneitherbiasedtoHighnorLow,internalcircuitrydefaultsthevaluetoLow.

ThelastbitoftheSlaveaddressspecifieswhetheraReadorWriteoperationistobeperformed.Whenthisbitissetto 1, a Read operation is selected, and when set to 0, a Writeoperationisselected.

AftertheMastertransmitstheStartconditionandSlaveaddressbyte(Fig.5),theappropriate2-wireSlave(eg.IS34C02B)willrespondwithACKontheSDAline.TheSlavewillpulldowntheSDAontheninthclockcycle,signalingthatitreceivedtheeightbitsofdata.TheselectedIS34C02BthenpreparesforaReadorWriteoperation by monitoring the bus.


IS34C02B

WRITE OPERATION

Byte WriteIntheByteWritemode,theMasterdevicesendstheStartcondition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates anACK,theMastersendsabyteaddressthatiswritteninto the address pointer of the IS34C02B. After receiving anotherACKfromtheSlave,theMasterdevicetransmitsthe data byte to be written into the address memory location. The IS34C02BacknowledgesoncemoreandtheMastergeneratestheStopcondition,atwhichtimethedevicebeginsitsinternalprogrammingcycle. Whilethisinternal cycle is in progress, the device will not respond toanyrequestfromtheMasterdevice.

Page Write

TheIS34C02Biscapableof16-bytePage-Writeoperation.APage-WriteisinitiatedinthesamemannerasaByteWrite,butinsteadofterminatingtheinternalWritecycleafterthefirstdatabyteistransferred,theMasterdevicecan transmit up to 15 more bytes. After the receipt of each databyte,theIS34C02BrespondsimmediatelywithanACKonSDAline,andthefourlowerorderdatabyteaddressbits are internally incremented by one, while the higher order bits of the data byte address remain constant. If a byte address is incremented from the last byte of a page, itreturnstothefirstbyteofthatpage.IftheMasterdeviceshould transmit more than 16 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previouslywrittendatawill beoverwritten. Onceall 16bytes are received and the Stop condition has been sent bytheMaster,theinternalprogrammingcyclebegins.Atthis point, all received data is written to the IS34C02B in a singleWritecycle.AllinputsaredisableduntilcompletionoftheinternalWritecycle.

Acknowledge (ACK) Polling

ThedisablingoftheinputscanbeusedtotakeadvantageofthetypicalWritecycletime. OncetheStopconditionisissuedtoindicatetheendofthehost'sWriteoperation,theIS34C02BinitiatestheinternalWritecycle.ACKpollingcanbeinitiatedimmediately. ThisinvolvesissuingtheStartconditionfollowedbytheSlaveaddressforaWriteoperation.IftheIS34C02BisstillbusywiththeWriteoperation,no No Acknowledge (NoACK) will be returned. If theIS34C02Bhascompleted theWriteoperation,anACKwill be returned and the host can then proceed with the nextReadorWriteoperation.

WRITE PROTECTION

Hardware Write Protection

TheIS34C02Bhastwoformsofsoftwarewriteprotec-tionandoneformofhardwarewriteprotection.ThehardwarewriteprotectionisenabledwhentheWPinput is held High. In this case, the entire array of the IS34C02Bisread-onlyregardlessofthestatusofthesoftwareprotection.ThehardwareprotectionisdisabledwhentheWPinputisheldLoworisfloating.Inthiscase,theupperhalfofthearray(80h-FFh)canbemodi-fiedbyavalidWritecommand,andthelowerhalfofthearray (00h-7Fh) can be modified only if software write protection has not been enabled.

Reversible Software Write Protection

Thereisanon-volatileflagforeachofthetwoformsofsoftwarewriteprotection.Whenthebitvalueforeither flag or both flags is 1, it is not possible to modify the contents of the lower 128 bytes of the array (00h-7Fh). If the bit value for both flags is 0, it is possible to modifythishalfofthearraywithavalidWritecommand,assumingWPisheldLoworisfloating.Thedeviceisshippedwithbothflagscleared.OneofthoseflagsistheReversibleSoftwareWriteProtection(RSWP)flag,andcanbechangedwiththeSetRSWPandClearRSWPcommands.TheflagcanalsobeverifiedwithoutbeingchangedwithaReadSWPcommand.Inordertoset,clearorreadtheRSWP,theIS34C02Binputpinsmustbeasfollows:A0mustbeheldtoanextrahighvoltageofVHV(seeDCCharacteristics),whileA2andA1mustbesetHigh,Low,orleftfloating,dependingonthede-siredcommand(seeFigure5).Oncetheseinputcondi-tions are met, a command can be issued to the device.

Thereversiblesoftwarecommandsareinitiatedsimilarlytoanormalbytewriteoperation;however,theslavedeviceaddressbeginswiththebitvalues0110.ThenextthreebitsareA2=0,A1=0or1,andA0=1,sothat they logically match the values on the input pins. If the last bit of the slave device address (R/W) is 0, the RSWPflagcanbeClearedorSet.IfR/W is 1, the flag canbeverifiedwiththeReadSWPcommand.Followingthisbit,thedevicerespondswitheitherACKorNoACK,depending on the exact command and the flag status (seeTable1:ReversibleInstructions).TocompletetheSetRSWPorClearRSWPcommand,theMastermusttransmit a dummy address byte, a dummy data byte, andaStopsignal.ToactuallymodifytheRSWPflag,


IS34C02B

WPshouldbeheldLoworbefloatingduringentirecom-mandsequence.Beforeresuminganyothercommand,theinternalwritecycletimeshouldbeobserved.TocompletetheReadSWPStatusorReadCWPStatuscommand,theMastercantransmitaStopsignalaftertheACK/NoACK.TheWPinputisnotevaluatedfortheReadSWPStatusorReadCSPStatuscommands.

Permanent Software Write Protection

TheIS34C02Bcontainsapermanentsoftwarewriteprotection(PSWP)feature.Ifthenon-volatilePSWPflaghasabitvalueof1,thearrayregionof00h-7Fhisprotectedfrommodification.IfthePSWPflaghasabitvalue of 0, the write protection for the lower half of the arrayisdeterminedsolelybythestatusesofRSWPandtheWPinput.AfterthePSWPflagissetto1viathePermanentWriteProtectcommand,theprotectedareabecomesirreversiblyread-onlydespitepowerremovalandre-applicationonthedevice.Onceenabled,thepermanent protection is independent of the status of the WPpin.

ThePermanentSoftwareWriteProtectcommandisinitiatedsimilarlytoanormalbytewriteoperation;however, the slave device address begins with the bit valuesof0110(seeFigure5).ThefollowingthreebitsareA2-A0, so that they logically match the values on the input pins.Thelastbitoftheslaveaddress(R/W) is 0.TheIS34C02BrespondswitheitherACKorNoACK,dependingontheflagstatus(seeTable1:PermanentInstructions).AssuminganACKisreceived,Masterthenmustcompletethesequencebytransmittingadummy address byte, dummy data byte, and a Stop sig-nal(seeFigure11).TheWPpinshouldbeheldLoworleft floating during the entire command. Before resuming any other command, the internal write cycle should be observed.

ThestatusofthePSWPcanbesafelydeterminedwith-out any changes by transmitting the same slave address as above, but with the last bit (R/W) setto1(seeFigure12).IfthePSWPhasbeenset,theIS34C02Bwillnotacknowledge any slave address starting with bits 0110 (seeFigure5).Tocompletethecommand,theMastercantransmitaStopsignalaftertheACK/NoACK.


IS34C02B TABLE 1

Normal Instructions

Command PSWP RSWP WP1 ACK Address ACK Data Byte Data Byte Write (Permanent) (Reversible) Command Address ACK Cycle Read X X X ACK 00h-FFh ACK DataByte ACK NoWrite 0 0 0 ACK 00h-FFh ACK DataByte ACK YesWrite X X 1 ACK 00h-FFh ACK DataByte ACK NoWrite 1 X X ACK 00h-7Fh ACK DataByte ACK NoWrite X 1 X ACK 00h-7Fh ACK DataByte ACK NoWrite X X 0 ACK 80h-FFh ACK DataByte ACK Yes

Permanent Instructions

Command PSWP RSWP WP1 ACK Address ACK Data Byte Data Byte Write (Permanent) (Reversible) Command Address ACK CycleReadPSWPStatus4 0 X X ACK Dummy ACK Dummy ACK No Address ByteReadPSWPStatus 1 X X NoACK — — — — NoSetPSWP 0 X 0 ACK Dummy ACK Dummy ACK Yes Address ByteSetPSWP 1 X 0 NoACK — — — — NoSetPSWP 0 X 1 ACK Dummy ACK Dummy ACK No Address ByteSetPSWP 1 X 1 NoACK — — — — No

Reversible Instructions

Command PSWP RSWP WP1 ACK Address ACK Data Byte Data Byte Write (Permanent) (Reversible) Command Address ACK CycleReadSWPStatus4 X 0 X ACK Dummy ACK Dummy ACK No Address ByteReadSWPStatus X 1 X NoACK — — — — NoReadCWPStatus3,4 0 X X ACK Dummy ACK Dummy ACK No Address ByteReadCWPStatus3 1 X X NoACK — — — — NoSetRSWP X 0 0 ACK Dummy ACK Dummy ACK Yes Address ByteSetRSWP X 1 0 NoACK — — — — NoSetRSWP X 0 1 ACK Dummy ACK Dummy ACK No Address ByteSetRSWP X 1 1 NoACK — — — — NoClearRSWP 0 X 0 ACK Dummy ACK Dummy ACK Yes Address ByteClearRSWP 1 X 0 NoACK — — — — NoClearRSWP 0 X 1 ACK Dummy ACK Dummy ACK No Address ByteClearRSWP 1 X 1 NoACK — — — — No

Notes: 1.WP=1ifinputlevelisHigh.WP=0ifinputlevelisGNDorfloating. 2.X=Don’tCare. 3.ReadCWPStatusyieldsthesameresultasReadPSWPStatus.4.ReadoutDon'tCareDummyAddressandDummyDataisoptional.


IS34C02B

Sequential Read

Sequential Reads can be initiated as either a CurrentAddress Read or Random Address Read. After the IS34C02B sends the initial byte sequence, the MasterdevicerespondswithanACKindicatingitrequiresadditionaldata from the IS34C02B. The IS34C02B continues tooutputdata foreachACKreceived. TheMasterdeviceterminatesthesequentialReadoperationbypullingSDAHigh(noACK) indicating the lastdatabyte toberead,followed by a Stop condition.

Thedataoutputissequential,withthedatafromaddressnfollowedbythedatafromaddressn+1,...etc. Theaddresscounter increments by one automatically, allowing the entire memorycontentstobeseriallyreadduringsequentialReadoperations. Whenthememoryaddressboundary255isreached, the address counter “rolls over” to address 0, andtheIS34C02BcontinuestooutputdataforeachACKreceived.(RefertoFigure10.SequentialReadOperationStartingwithaRandomAddressReadDiagram.)

READ OPERATION

Read operations are initiated in the same manner as Writeoperations,exceptthatthe(R/W) bit of the Slave address is set to “1”. There are three Read operationoptions:currentaddressread,randomaddressreadandsequentialread.

Current Address Read

TheIS34C02Bcontainsaninternaladdresscounterwhich maintains the address of the last byte accessed, incrementedbyone. Forexample,ifthepreviousoperationiseitheraReadorWriteoperationaddressedto the address location n, the internal address counter wouldincrementtoaddresslocationn+1. WhentheIS34C02BreceivestheDeviceAddressingBytewithaRead operation (R/W bit set to “1”), it will respond an ACKandtransmitthe8-bitdatabytestoredataddresslocationn+1. TheMastershouldnotacknowledgethe transfer but should generate a Stop condition so the IS34C02B discontinues transmission. If the last byte of the memory was the previous access, the data fromlocation'0'willbetransmitted.(RefertoFigure8.CurrentAddressReadDiagram.)

Random Address Read

SelectiveReadoperationsallowtheMasterdevicetoselectatrandomanymemorylocationforaReadoperation. TheMasterdevicefirstperformsa 'dummy'Writeoperationby sending the Start condition, Slave address and word address of the location it wishes to read. After the IS34C02Backnowledgesthewordaddress, theMasterdevice resends the Start condition and the Slave address, this time with the R/Wbitsettoone. TheIS34C02BthenrespondswithitsACKandsendsthedatarequested. TheMasterdevicedoesnotsendanACKbutwillgeneratea Stop condition. (Refer to Figure 9. Random AddressReadDiagram.)


IS34C02B

SCL

SDA

MasterTransmitter/

Receiver

IS34C02B

Vcc

Figure 1. Typical System Bus Configuration

tAA

Data Outputfrom

Transmitter

SCL fromMaster

Data Outputfrom

Receiver

1 8 9

ACK

tAA

Figure 2. Output Acknowledge

ST

OP

Co

nd

ition

SCL

SDA

ST

AR

TC

on

dit

ion

Figure 3. Start and Stop Conditions


IS34C02B

Figure 5. Command Configuration

Figure 4. Data Validity Protocol

SCL

SDA

Data Stable Data Stable

Data Change

Figure 6. Byte Write

SDABus

Activity

START

MSB

LSB

MSB

WRITE

STOP

R/W

ACK

ACK

ACK

DataDevice

Address Word Address* * *

* Acknowledges provided by the slave regardless of hardware or software Write Protection.

7BIT 4 3 1256 0

R/WA0A1A20101 Normal Instruction2

R/WA0A1A2010 1Permanent Write Protection Instruction2

Pin Connection1 Slave Device Address

A2

A2 A1 A0

A2 A1 A0

0100010 1Set Write Protection (SWP)GND GND VHV

0110010 1Clear Write Protection (CWP)GND Vcc VHV

1100010 1Read SWP

GND GND VHV

1110010 1Read CWP

GND Vcc VHV

A1 A0

Note:

1. A2-A0 input pin connections must be GND (or floating), Vcc, or VHV.

2. Bits 1, 2, and 3 of the device address will be compared with the values on the external pins.


IS34C02B

Figure 8. Current Address Read

Figure 9. Random Address Read

SDABus

Activity

START

MSB

LSB

NO

ACK

READ

STOP

ACK

DataDevice

Address

R/W

SDABus

Activity

ACK

ACK

ACK

Data nWord

Address (n)Device

Address

DUMMY WRITE

DeviceAddress

START

WRITE

READ

START

STOP

MSB

LSB

NO

ACK

R/W

Figure 7. Page Write

SDABus

Activity

START

MSB

LSB

WRITE

ACK

ACK

ACK

ACK

Data (n+1) Data (n)Word Address (n)Device

Address

STOP

ACK

Data (n+15)

R/W

* * * **

* Acknowledges provided by the slave regardless of hardware or software Write Protection.


IS34C02B

Figure 11. SET PERMANENT WRITE PROTECTION

Figure 12. READ PERMANENT WRITE PROTECTION

SDABus

Activity

START

MSB

LSB

READ

ACK

DeviceAddress

R/W

STOP*

*Theslavedoesnotprovideanacknowledgementifthepermanentwriteprotectionisalreadyenabled.

SDABus

Activity

START

MSB

LSB

MSB

WRITE

STOP

R/W

ACK

ACK

ACK

DataDevice

Address Word Address*

* The slave does not provide an acknowledgement if the permanent write protection is already enabled.

# # # # # # # # # # # # # # # #

# Don't care bits are required.

Figure 10. Sequential Read

STOP

NO

ACK

ACK

ACK

ACK

ACK

Data Byte n+XData Byte n+1Data Byte n Data Byte n+2

R/W

SDABus

Activity

DeviceAddress

READ


IS34C02B

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit Vs Supply Voltage –0.5 to +6.5 V Vp VoltageonAnyPin –0.5toVcc+0.5 V Tbias TemperatureUnderBias –55to+125 °C TsTg StorageTemperature –65to+150 °C iouT OutputCurrent 5 mANotes:1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycauseper-

manentdamagetothedevice.Thisisastressratingonlyandfunctionaloperationofthedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING RANGE (IS34C02B-2)

Range Ambient Temperature VCC

Industrial –40°Cto+85°C 1.7Vto3.6V

CAPACITANCE(1,2)

Symbol Parameter Conditions Max. Unit

Cin Input Capacitance Vin = 0V 6 pF

CouT OutputCapacitance VouT = 0V 8 pF

Notes:1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.2. Testconditions:Ta = 25°C, f=400KHz,Vcc=3.0V.


IS34C02B

DC ELECTRICAL CHARACTERISTICSIndustrial(Ta=-40oC to +85oC)

Symbol Parameter Test Conditions Min. Max. Unit Vol1 OutputLowVoltage VCC = 1.7V, iol = 0.15mA — 0.2 V

Vol2 OutputLowVoltage VCC = 3.6V, iol = 2.1mA — 0.4 V

Vih Input High Voltage VCC x 0.7 VCC + 0.5 V

Vil InputLowVoltage –1.0 VCC x 0.3 V

VhV A0 High Voltage VhV - VCC > 4.8V 7 10 V

ili InputLeakageCurrent Vin = VCC max. — 3 µA

ilo OutputLeakageCurrent — 3 µA

AC ELECTRICAL CHARACTERISTICSIndustrial(Ta=-40oC to +85oC)

1.7V ≤ Vcc ≤ 3.6V

Symbol Parameter Min. Max. Unit fSCL SCLClockFrequency 0 400 KHz

T NoiseSuppressionTime(1) — 50 ns

tLow ClockLowPeriod 1.2 — µs

tHigh ClockHighPeriod 0.6 — µs

tBUF BusFreeTimeBeforeNewTransmission(1) 1.2 — µs

tSU:STA StartConditionSetupTime 0.6 — µs

tSU:STO StopConditionSetupTime 0.6 — µs

tHD:STA StartConditionHoldTime 0.6 — µs

tHD:STO StopConditionHoldTime 0.6 — µs

tSU:DAT DataInSetupTime 100 — ns

tHD:DAT DataInHoldTime 0 — ns

tsu:wp WPpinSetupTime 0.6 — µs

thd:wp WPpinHoldTime 1.2 — µs

tDH DataOutHoldTime(SCLLowtoSDADataOutChange) 50 — ns

tAA ClocktoOutput(SCLLowtoSDADataOutValid) 50 900 ns

tR SCLandSDARiseTime(1) — 300 ns

tF SCLandSDAFallTime(1) — 300 ns

tWR WriteCycleTime — 5 ms

POWER SUPPLY CHARACTERISTICSIndustrial(Ta=-40oC to +85oC)

Symbol Parameter Test Conditions Min. Max. Unit iCC1 VccOperatingCurrent Readat100KHz(Vcc=3.6V) — 1.0 mA

iCC2 VccOperatingCurrent Writeat100KHz(Vcc=3.6V) — 3.0 mA

isb1 StandbyCurrent Vcc=1.7V — 1 µA

isb2 StandbyCurrent Vcc=3.6V — 2 µA

Notes: Vil min and Vih max are reference only and are not tested.

Note: 1.Theseparametersarecharacterized,butnot100%tested.


IS34C02B

8th BIT ACK

WORD nSTOPCondition

STARTCondition

tWR

SCL

SDA

FIGURE 14. WRITE CYCLE TIMING

FIGURE 13. AC WAVEFORMS

tSU:STA

tF tHIGH tLOWtR tSU:STO

tBUF

tDHtAA

tHD:STA

tHD:DAT

tSU:DAT

SCL

SDAIN

SDAOUT

tSU:WPtHD:WP

WP


IS34C02B

ORDERING INFORMATIONIndustrial Range: -40°C to +85°C, Lead-free Voltage Range Part Number Package Notes

1.7V IS34C02B-2DLI-TR DFN Notrecommendedfornewdesign to3.6V IS34C02B-2UDLI-TR UDFN IS34C02B-2ZLI-TR TSSOP

* 1. Contact ISSI Sales Representatives for availability and other package information.2.Thelistedpartnumbersarepackedintapeandreel“-TR”(4Kperreel).UDFN/DFNis5Kperreel.3.Fortube/bulkpackaging,remove“-TR”attheendoftheP/N.4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable.


IS34C02B

2k-bit 2-wire serial cmos eeprom with permanent and ... is34c02b (rev.00e 09_2009).pdfthe is34c02b...

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