20.5: a single-chip cmos radio soc for v2.1 bluetooth applications · 2017. 11. 29. · 20.5: a...
TRANSCRIPT
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20.5: A Single-chip CMOS Radio SoC for v2.1 Bluetooth Applications
David Weber, William W. Si, Shahram Abdollahi-Alibeik, MeeLan Lee, Richard Chang, Hakan Dogan,
Susan Luschas, Paul Husted
Atheros Communications, Santa Clara, California
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Outline
• Bluetooth Requirements
• SoC block diagram
• Frequency Plan
• Polar Transmitter and Synthesizer
• 500kHz low-IF Receiver
• Summary
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Bluetooth Requirements• Operates in ISM band (2.402 – 2.480GHz)
• Hops through 79 channels, each 1MHz bandwidth
• There are now three data ratesOriginal 1Mbps rate uses GFSK modulationEDR (2 & 3Mbps) uses π/4-DPSK and 8-PSK modulation
• Primarily for short range communication
• Goal is to reduce power consumption and cost
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SoC Block diagram
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Frequency Plan
• VCO operates between 4.8 and 5 GHzLO signals generated efficiently with divide-by-2
• For transmit, VCO operates at 2x channel frequency
Divide-by-two block drives power amplifier
• For receive, VCO is shifted by 1MHz relative to 2x channel frequency
Creates 500kHz low-IF receive topology
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TX Architecture
• Polar architectureModem divides signal into AM and FM pathsMinimizes silicon areaParticularly efficient for 1Mbps rate when only FM data is needed (amplitude is constant)
• AM data is added at power amplifierRequired for 2Mbps and 3Mbps rates
• 2-point modulation for FM dataFM data is subdivided into High Frequency (HF) and Low Frequency (LF) paths
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Two-point modulation• Allows FM path bandwidth to be wider than
synthesizer loop bandwidth
•Variation in loop bandwidth does not affect FM
freq
freq
freq
freq
Ref: R. Meyers, P. Waters, Colloquium on VLSI implementations, 1990
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Synthesizer and FM modulation
•Elements in Red add frequency modulation path
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TX Block Diagram
•For 1Mb rate, PA simply amplifies Synth output
•For 2Mb and 3Mb rates, AM signal is added at PA
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EDR Signals3Mbps rate uses 8-PSK constellation
•AM dynamic range: need 26dB min Spectral mask
•FM bandwidth:need 6.5MHz min EVM
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VCO design
•HF modulation gain must be calibrated
HF gain variation vs. process
8000850090009500
1000010500110001150012000
0 512 1024 1536 2048
HF data input (11-bit code)
HF
gain
(Hz/
bit)
HF data
Vc
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PA designDC current@2dBmSwitching mode:
10.1mALinear mode:
20mA
LOp+FMp LOp+FMpLOn+FMn
AMpAMn
VDDswitching
mode
OUTp
OUTn
bondwires
M1
M2
M3
M4
M5 M6 M8 M7
M9 M10 M12 M11bias
GND
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EVM measurement
•Transmitting 3Mbps packet (8psk) at 2dBm
< 13% RMS DEVM
< 25% peak DEVM
99% symbols < 20% DEVM
3Mb specification
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TX Spectrum measurements
1Mb GFSK Spectrum (2dBm channel power)
3Mb 8PSK Spectrum (2dBm channel power)
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RX architecture
• 500kHz IF optimizes area and powerTraditional low-IF uses analog BPF more areaDirect conversion overlaps signal and DC offset
signal detection challenge500kHz IF analog components similar to zero-IF
both area efficient and robust
• Minimal analog filteringΔΣ ADC has 74dB dynamic rangeModem removes DC offset and close-in blockersLPF and notch prevent ADC saturation and aliasing
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RX block diagram
•Similar to zero-IF
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RX performance
• Battery life is more important than range!-88dBm sensitivity @ 1Mb requires 12dB NFRX signal path consumes 18.5mW
7.08.09.0
10.011.012.013.014.015.016.0
0 6 12 18 24 30 36 42 48 54 60 66 72 78channel
Noi
se F
igur
e (d
B)
-93-92-91-90-89-88-87-86-85-84
1Mb
sens
(dB
m)
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In-Band Blocking for 1Mb/s
-50
-40
-30
-20
-10
0
10
20
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
Frequency Offset (MHz)
C/I
(dB
)
Bluetooth SpecMeasurements
RX blocker rejection
•No exception for image channel needed
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DC Offset
budget <= 140mV
measured vs. channel and process
•Offset is quantized by ADC and removed by modem
0
20
40
60
80
100
120
140
160
2400 2410 2420 2430 2440 2450 2460 2470 2480
frequency (MHz)
DC
off
set (
mv)
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LNA/Switch schematicbo
ndw
ires
bond
wire
s
Ref: R. Chang, ISSCC 2007
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-140
-130
-120
-110
-100
-90
-80
-70Ph
ase
Noi
se (d
Bc/
Hz)
Phase Noise
Frequency Offset10k 100k 1M 10M
-87dBc/Hz inband
-112 dBc/Hz @ 1MHz
•Affects TX spectral mask and RX blocker rejection
•Synth power consumption is 14mW
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Die Photo
•0.13um CMOS
•Standard digital process
•Analog area: 3mm2
•Total die size: 9.2mm2
•QFN 40pin package
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Performance SummaryThis work2dBm <6%<18%19.3mA
10.1mA20mA-88 dBm-90 dBm-84 dBm<12dB29.7mA
9.2mm2
3.0mm2
0.13um standard CMOS
5x5 QFN
TX output power Class 2 operation3Mbps Transmit DEVM rms
peak<13% spec<25% spec
Continuous TX power consumption (All analog/RF functions excluding PA)
1.2V supply
PA power consumption – basic rateEDR
tested with 3.3V supply voltage
RX sensitivity – 1Mb (GFSK)2Mb (π/4 DPSK)3Mb (8PSK)
-70dBm specfor all rates
RX noise figureContinuous RX power consumption(All analog/RF functions)
1.2V supply
Die Area SoC including Analog/RFAnalog/RF portion only
Technology
Package
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Conclusions• Demonstrated a single-chip Bluetooth v2.1
SoC supporting EDR
• Polar transmitter architecture reduces area
• 500kHz IF Receiver minimizes analog filtering
• Smallest published Bluetooth SoC to date in 0.13um CMOS
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AcknowledgementsAn SoC requires more than a radio to succeed.
The authors gratefully acknowledge the work of the entire Bluetooth team at Atheros.
Additional thanks to Eric Dukatz, Soner Ozgur, Haitao Gan, Yashar Rajavi, and Joe Jamp for their help in preparing this paper for presentation.