2014 ieee a half-bridge llc resonant converter adopting

8/10/2019 2014 IEEE a Half-Bridge LLC Resonant Converter Adopting

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014 841

A Half-Bridge LLC Resonant Converter Adopting

Boost PWM Control Scheme for Hold-Up

State OperationIn-Ho Cho, Student Member, IEEE, Young-Do Kim, Student Member, IEEE, and Gun-Woo Moon, Member, IEEE

AbstractThis paper presents a half-bridge LLCresonant con-verter having a boost pulse width modulation (PWM) convertercharacteristic for hold-up state operation. The proposed converteris based on a half-bridge LLCresonant converter structure and asingle auxiliary switch is added at the primary side. The converterhas two different operational characteristics. It shows the same op-erational characteristic with the conventional LLCresonant con-verters during nominal state, which is frequency modulation (FM)method. However, when ac line lost and the converter enters intothe hold-up time state, which requires wide voltage gain changes,

the control method of the proposed converter is changed to thePWM method using the auxiliary switch. Since the proposed con-verter compensates wide voltage gain variation with PWM methodof the auxiliary switch rather than adopting the FM method ofmain switches, the frequency variation range for the LLCresonantconverter is highly reduced in the proposed converter. Therefore,the transformer in the proposed converter can be designed at theoptimal operating point and it results in decreased conduction lossof the magnetizing inductor current. Furthermore, the maximumvoltage gain of the proposed converter is easily increased by ex-tending the duty ratio of the auxiliary switch. It helps to decreasethe link capacitance. To verify the effectiveness of the proposedcircuit, operational principle will be explained and experimentalresults will be presented with following specification. 100 kHz ofswitching frequency, 250400 V of input voltage range, 250 V of

output voltage, and 75 W output power.

Index TermsBoost PWM control and zero voltage switching(ZVS), hold-up time,LLCresonant converter.

NOMENCLATURE

M1 , M2 Main switches.Qa Auxiliary switch.D1 , D2 , D3 , D4 Rectifier diodes.Cr , Lr Resonant capacitor and resonant inductor.Lm Magnetizing inductor of transformer.Clink Link capacitor.

CO , RO Output capacitor and output resistor.

Manuscript received November 8, 2012; revised January 8, 2013 and March24, 2013; accepted March 30, 2013. Date of current version August 20, 2013.Recommended for publication by Associate Editor K. Ngo.

I.-H. Cho is with LG Electronics, Seoul 150-721, Korea (e-mail: [email protected]).

Y.-D. Kim is with Samsung Electro-MechanicsCompany, Gyeonggi-Do 443-743, Korea (e-mail: [email protected]).G.-W. Moon is with the Department of Electrical Engineering, KAIST,

Daejeon 305-701, Korea (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2257863

Fig. 1. Block diagram of two-stage ac/dc converter.

NP, NS Transformer primary turns and secondaryturns.

n Turn ratio of transformer,NP/NS.VS, VO Input voltage and output voltage.Vpr i, VLm Magnetizing inductor voltage.VC r, VLr Resonant capacitor and resonant inductor

voltage.

VQ a Auxiliary switch voltage.Ipr i Primary side current.ILr Resonant inductor current.ILm Magnetizing inductor current.

IQa Auxiliary switch current.Irect Current flows to the load.CO SS Output capacitance of switch.Clink Input link capacitor.DQ a Duty ratio of the auxiliary switch.Fr , FS Resonant frequency and switching frequency.K Lm/Lr .tdead Dead time of gate signals.PO Output power.Vno m , Vm in Nominal and minimum input voltage.

I. INTRODUCTION

IN recent years, considerable researches have been performedfor ac/dc converters to increase the power density and to im-

prove the efficiency. These researches are mainly focused on

two-stage type ac/dc converter which includes a power-factor-

correction (PFC) stage besides output regulation circuit. Fig. 1

shows the structure of two-stage ac/dc converter. The PFC stage

is used to achieve unity power factor of the system and galvanic

isolation and output voltage regulation characteristics are sat-

isfied by the dc/dc stage. In these two parts, the dc/dc stage is

regarded as the more critical part to improve the efficiency of the

system, because it converts high voltage input into variable load

voltage/current output, which results in a significant power loss.

Furthermore, some specifications require that the system should

0885-8993 2013 IEEE


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842 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014

Fig. 2. Input voltage variation of dc/dc converter.

maintain output voltage for a certain amount of time after loss

of ac line voltage, called hold-up time (see Fig. 2), which make

dc/dc converters have limited efficiency and low power density.

The hold-up time period is varied depends on specifications,

from a few milliseconds to dozens of milliseconds. During this

time, a dc/dc converter is powered by the stored energy in linkcapacitors, so that the dc/dc converter should be designed to be

able to compensate the wide input voltage range.

Many approaches have been suggested for a high efficient

dc/dc converter [1][9]. Among these approaches,LLCresonant

converter [9] is chosen as the most promising candidate in low-

power application, due to the zero voltage switching (ZVS)

characteristic for the primary switches and no reverse-recovery

problem for the rectifier diodes.

An LLC resonant converter shows the maximum efficiency

in the nominal condition, when the converter is operated at the

resonant frequency. However, the switching frequency becomes

reduced and growing apart from the resonant switching point

as the input voltage decreases. This frequency change becomes

a considerable issue under a wide input variation condition.

It makes LLC resonant converters have difficulty in magnetic

design, and it also decreases nominal efficiency of the convert-

ers. Furthermore, output voltage in the converter is not well

regulated using the conventional dc gain equation ofLLCcon-

verters because the converter is affected by harmonics when

it is operated out of the resonant point. The dc conversion ra-

tio of a conventional LLC resonant converter is represented as

follows [9][11]:

VO

VS=

1

2n

1+ 1K

1

FrFs

2

2+

FsFr FrFs

2

8n 2Q

2

(1)

where Q=

Lr /Cr(1/RO ) , Fr = 1/2

Lr Cr , and K=Lm /Lr .

A number of different methods have been proposed to over-

come this drawback of the LLC resonant converter [12][14].

Modulating transformer secondary turns is suggested in Fig. 3

[12]. By increasing secondary turns during hold-up time, the

converter makes higher voltage gain than the conventionalLLC

converter, and it results in reduction of frequency variation

range. However, additional transformer windings increase the

transformer size, and an additional diode and a switch make the

Fig. 3. AnLLCresonant converter using various transformer turn ratios.

Fig. 4. AnLLCresonant converter with a secondary auxiliary circuit for hold-

up time.

Fig. 5. Asymmetric PWM control scheme during hold-up time for an LLCresonant converter.

converter have low power density and increased circuit complex-ity. Boosting-up primary current is another method proposed in

Fig. 4 [13]. The converter applies zero voltage to the trans-

former using the secondary auxiliary circuit and the primary

current is build up during this period. Although higher voltage

gain characteristic can be achieved with this method, the pro-

posed converter requires many bulk components. Asymmetric

PWM control scheme is proposed in Fig. 5 [14]. This method in-

creases voltage gain without using any additional components,

but with changing control scheme from frequency modulation

(FM) to PWM control for the hold-up time operation. High volt-

age gain is achieved using this method while maintaining high

power density characteristic. However, the gain variation range

is limited in the converter (see Fig. 6) and the maximum gainis determined by the resonant tank design. Also, the dc offset

current of the magnetizing inductor increases the transformer

size.

In this paper, a new half-bridge (HB)LLCresonant converter

having wide gain variation characteristic is proposed. The pro-

posed converter is operated at the resonant frequency, which is

the maximum efficiency point of theHBLLCresonant converter,

during nominal state and the converter shows boost PWM con-

verter operation to increase the voltage gain with an auxiliary

switch during hold-up state. The input energy is build up while

the auxiliary switch is conducted and it is transferred to the sec-

ondary side for the last period. Since switching frequency is not


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CHOet al.: HALF-BRIDGE LLC RESONANT CONVERTER ADOPTING BOOST PWM CONTROL SCHEME 843

Fig. 6. Gain characteristic of the Asymmetric PWM Control (APWM)LLCConverter adopting the APWM control method.

Fig. 7. Schematic diagram of the proposed converter.

widely varied in the proposed converter operation, the converter

can be designed with the optimal operating point. Also, the size

of link capacitors can be reduced in the converter. To verify the

advantages, theoretical analysis and experimental results of the

proposed converter will be presented with 75 W prototype.

II. FEATURES OF THEPROPOSED CONVERTER

The circuit diagram of the proposed converter is represented

in Fig. 7. It is based on the conventional HBLLCresonant con-

verter and an auxiliary switch is added to the primary side of the

converter. Fig. 8 shows the key operations of the proposed con-

verter for the nominal state and for the hold-up state. In nominal

state, the proposed converter is operated just the same as theconventional LLCresonant converter operated at the resonant

switching frequency. The soft switching condition is naturally

realized and no unnecessary conduction loss is appeared in this

operation. Therefore, the maximum efficiency is showed with

the proposed converter during nominal state. When the converter

enters into the hold-up state, the converter increases the volt-

age gain using the auxiliary switchQa . The resonant inductorcurrent is build up, while the auxiliary switch is conducted and

it is transferred to load during off-state of the auxiliary switch.

Therefore, higher voltage gain is easily achieved in the proposed

converter by increasing the duty ratio ofQa . The operational

characteristic is similar to the boost PWM operation.

Fig. 8. Key operations of the proposed converter. (a) Nominal state operation.(b) Hold-up state operation.

Fig. 9. Key waveforms of the proposed converter.

III. OPERATIONALPRINCIPLES

Operations of the proposed converter are analyzed in this sec-

tion. The operational principle for the nominal sate is the same

with that of the conventionalLLCresonant converter operated at

resonant frequency [9][14]. Thus, only the operation for hold-

up time is explained in this section. For the convenience of the

mode analysis, several assumptions are made as follows:


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Fig. 10. Equivalent circuit of the proposed converter in hold-up state.

1) the converter is operated in the steady state;

2) the switches M1 , M2 , and Qaare ideal components exceptfor their output capacitances and body diodes;

3) the diodesD1

D4 are ideal components;4) the windings of the transformer are well coupled so that

the leakage inductance is negligible;

5) the output voltage is constant;

6) the turn ratios of the transformer is expressed as n (n=NP/NS);

7) the resonant capacitance is very high, so thatVCr is re-garded as constant value.

Each switching cycle can be divided into six modes t0t6for hold-up state operation. The operating waveforms and the

equivalent circuits are represented in Figs. 9 and 10.

A. Mode 1 (t0 t1 ) : The switch M1is conducted in this modeand resonant inductor current ILr resonates with Cr and Lm +

Lr . The secondary side is disconnected from the primary sideand output energy is supplied with the output capacitor.

B. Mode 2 (t1t2 ) : As M1 is turned OFF, the parasiticcapacitors ofM1 and M2 start to be charged and discharged,respectively, in a resonant manner. Since the large magnetizing

inductor energy is participated in this resonance, ZVS condition

ofM2 is easily achieved.C. Mode 3 (t2t3 ): Qa and M2 is turned ON at t2 . HB

capacitor voltage VCr is applied to the resonant inductor Lr andresonant inductor current is linearly increased in this mode. It is

expressed as follows:

ILr = (VC r /Lr )DQ a T. (2)

D. Mode 4(t3t4 ): After theQa switch is turned OFF, thebuilt-up resonant inductor current is transferred to the load side.

Reflected output voltage is applied to magnetizing inductance

of the transformer and negative voltage, VC r

(NP

/NS

)VO

,

is found at the resonant inductor Lr . Therefore, the resonantinductor current decreases in this mode.

E. Mode 5 (t4t5 ) : When the resonant inductor currentreaches the magnetizing inductor current, ILm , the secondaryside is disconnected from the primary side and resonance be-

tweenCr and Lm + Lr appears in the converter.F. Mode 6(t5t6 ): M2 is turned OFF att5 and the primary

current flows through the body diode ofM2 .

IV. ANALYSIS ANDDESIGNCONSIDERATION

In this section, key characteristics and design considerations

of the proposed converter are presented and compared with theconventional LLC resonant converter. Generally, high capaci-

tance design for a resonant capacitor and low inductance design

for a resonant inductor are preferred in conventionalLLCres-

onant converters for high power density and high efficiency, so

that the capacitor voltageVC r is regarded as a constant value inthis analysis for an easier understanding of the proposed con-

verter. Also the magnetizing inductor current, ILm , is consideredas a constant value in this analysis during the switching period

because the magnetizing inductor Lm is normally designed tohave very high inductance value compared to Lr , sothat the cur-rent variation ofILm is neglected in conventionalLLCconverter

operation.


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Fig. 11. Simplified key waveforms of the proposed converter.

A. Voltage on the Resonant Capacitor

The voltage applied to the resonant capacitor VC r is used toderive the dc conversion ratio and current stress of the proposed

converter, andVC r can be achieved by using the simplified keywaveforms (see Fig. 11).

Since each increment of resonant inductor currents iLr dur-ing the period of DQ a TandDPT are the same, the durationDPT is achieved as follows:

VC rLr

DQ a T = (nVO VC r )

LrDP T DPT

= VC r

(nVO VC r )DQ a T. (3)

Using the voltage-second balance rule of the magnetizing in-

ductanceLm the voltage of the resonant capacitor is expressedas (4) and the final equation of (4) means the average magnetiz-

ing inductor voltage during the time DQ a T+DPT,

0.5T(VS VC r ) =nVO DP T+ VC r(0.5DQ aDP) T

VC r = 0.5VO nVO DP

1DQ a DP=

nVO DPDQ a + DP

. (4)

Therefore, the resonant capacitor voltage can be represented

as (5). It means the half of the input voltage is applied to the

resonant capacitor during the hold-up state operation

VC r = 0.5VS. (5)

B. DC Conversion Ratio

The proposed converter has two different inputoutput volt-

age conversion ratios depending on its operational state. For

nominal state, it has the same operational characteristic with

the conventionalLLCresonant converter. Thus, voltage gain is

affected by switching frequency, Fs , and the dc conversion ratiois expressed as

VOVS

= 1

2n

1+ 1K

1

FrFs

22

+

FsFr Fr

Fs 2

8n 2Q2

.

(6)

Fig. 12. Dc conversion ratio during nominal period (at 75 W Specification).

At nominal state when the converter has fixed input voltage

condition, the proposed converter is operated at the resonant

frequencyFr , and the switching frequency is ideally fixed tothe resonant frequency at any load condition. The relation of

voltage gain and switching frequency is depicted in Fig. 12.

A PWM method is adopted in the proposed converter to in-

crease the voltage gain during hold-up state operation. Fig. 11

shows the key waveforms of the proposed converter during hold-

up state operation. The shaded area AP in Fig. 11 implies thetotal chargeQ transferred from the input side to the secondaryload side. Thus, output voltage can be derived by calculating the

area ofAP, andtotal chargetransferred to the load is representedas follows:

Q=0.5 (Ipk DP T)

T =

VORO

1n

. (7)

Since DPT and Ipk values in (7) are calculated from thefollowing equations:

DP T = VC r

(nVO VC r )DQ a T (8)

Ipk =VC r

LrDQ a T. (9)

The dc conversion ratio of the proposed converter in hold-up

operation is expressed as (10) and Fig. 13

VOVS

=

1n

+

1n 2

+ 2 R OL r T D2Q a

4 . (10)

As shown in Fig 13, the voltage gain in hold-up state is

affected by theduty ratio ofQa , andthe gain is linearly increasedfollowed by the duty ratio.

C. Reduction of the Link Capacitor

After ac line lost, dc/dc converters are powered by energy

stored in link capacitors. Therefore, hold-up time condition and

the size of link capacitance are the major considerations when


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Fig. 13. Dc conversion ratio during hold-up period (at 75 W Specification).

Fig. 14. Required link capacitance depending on minimum link voltage.

designing converters. This relation is represented as

1

2Clink

V2no m V2mi n

PO t, t= hold - up time. (11)

Since the hold-up time condition and output power ratings are

given specifications in the system, minimum link voltage is the

only one factor which affects the link capacitance design. The

equation for the link capacitance design is derived from (11)

and it is expressed as (12) and Fig. 14.

Clink PO t2

(V2no m V2mi n ). (12)

As shown in Fig. 14, the required capacitance for link capac-

itors can be reduced by decreasing the minimum link voltage.

Therefore, converters are required to have high voltage gain

characteristic to minimize the link capacitor size and increase

the power density.

Since the dc conversion ratio of the proposed converter

shows linear characteristic, reduction of link capacitor is easily

TABLE ISTANDARDRATINGS OFCAPACITORS

Fig. 15. Current-second balance of the resonant capacitor.

achieved simply by increasing the maximum duty ratio of the

auxiliary switch Qa . Size of capacitors is highly affected by thecapacitances and the trend is represented in Table I.

D. Current Stress of Switches

The current stress of switches is a very important factor when

designing the proposed converter. In nominal state, the current

stresses of switches are the same with those of the conven-tional converters, but this condition is changed for the hold-up

time operation. Different from the conventional LLCresonant

converter, the proposed converter shows boost PWM operation

during the hold-up state. Thus, the peak value and RMS value of

the resonant inductor current are varied depending on the duty

ratio ofQa . Also, the dc offset current which is represented inthe magnetizing inductor affects the current stress of the con-

verter. The dc offset current is calculated using current-second

balance rule of the resonant capacitor Cr (see Fig. 15). Accord-ing to the current-second balance rule of the capacitor, sum of

the total charge flows in and out of the resonant capacitor is zero.

Therefore, the positive and the negative area in Fig. 15 should

be equal.

The shaded area of each period, tatb , tbtc , tctd , tdte ,andtetfare expressed as follows:

Shaded area oftatb

1

2

VC rLr

ILm ILm . (13)

Shaded area oftbtc

1

2

VC rLr

DQ a TILm

DQ a T ILmLr

VC r

.

(14)


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Fig. 16. Dc offsetcurrent of the magnetizing inductor (at 75 W Specification).

Shaded area oftctd1

2

VC rDQ aVC rnVO

LrILm(VC rnVO ) T

VC rLr

DQ a TILm

.

(15)

Shaded area oftd te1

2 ILm

ILm

Lr(nVO VC r )

. (16)

Shaded area oftetf

ILm T DQ a T

VC r DQ a T(nVO VC r ) . (17)

By utilizing the aforementioned equations, (13), (14), (15),

(16), and (17), the dc offset current can be obtained as (18) and

it is represented as Fig. 16

ILm = 1

2

VC rLr

D2Q a T1 + VC r

NP/NS

VO VC r

.

(18)

Since the resonant inductor current is build up in direct op-

position to the dc offset current of the magnetizing inductor

during the switching period ofQa , DQ a , the peak current stress

of the primary switch is obtained as (19) and Fig. 17. Also, themaximum current stress of the auxiliary switch is the same as

that of the primary switch

Ipk = VC r

LrDQ a T ILm , (0 DQ a 0.5). (19)

As shown in (19) and Fig. 17, the larger duty ratio requires

the switches with the higher current stress.

E. Reduction of Conduction Loss in the Nominal State

In conventional LLC resonant converters, the converter in-

creases voltage gain by decreasing switching frequencies. Thus,

the converter should be designed to be able to operate in wide

Fig. 17. Maximum current stressof theprimary switch(at 75 W Specification).

Fig. 18. Voltage gain graph of LLC resonant converters with different K (at75 W Specification).

frequency variation range for hold-up state regulation. This de-

sign condition increases the size of magnetic components and

makes the converter operated in far from the optimal operat-

ing point. To reduce the frequency variation range, a low K

(K=Lm/Lr )design with small magnetizing inductance Lm istypically used [9][20] (see Fig. 18) in LLCresonant convert-

ers. Although this method is beneficial to the magnetic compo-

nents design, the reduced magnetizing inductor Lm increasesthe RMS value of the primary current. Therefore, a low Kde-sign helps to decrease the frequency variation range, but it also

increases conduction loss of the converter in the nominal state.

Conduction loss comparison on differentKvalue is presentedin Table II. Unlike the conventional converter, the proposed

converter adopts boost PWM operation for hold-up state. Thus,

frequency variation is not required for hold-up state regulation

and magnetic components design is not affected by hold-up time

condition. It makes the converter enable to design with high K


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TABLE I ICONDUCTIONLOSS ONVARIABLEK (AT75 W SPECIFICATION )

value and higher efficiency is achieved in the nominal state with

the proposed converter.

F. ZVS Condition for the Switches

To achieve high efficiency for converters, ZVS condition

should be considered when designing converters. The opera-

tional principle of the proposed converter in the nominal state

is the same as that of the conventionalLLCresonant converters.

The output voltage builds up the magnetizing inductor current

during the powering period (20) and the built-up current is used

to discharge output capacitors of the switches during the dead

time of gate signals (21). Therefore, ZVS condition of the main

switches in anLLCresonant converter is represented as

IL m p k = 1

2

(NP/NS)VOLm

T

2 tdead

. (20)

IL m p k tdead 2CO S S VS. (21)

Lm1

8

(NP/NS)VO T tdeadCos s VS

(22)

where IL m p k is the peak value of magnetizing inductor current,tdead is the dead time of the switches, and Cos s represents theoutput capacitance of switches. The high magnetizing induc-

tor current results in conduction loss increases in the converter,

so that the magnetizing inductance should be designed to sat-

isfy both conditions, satisfying ZVS condition and minimizing

conduction loss increases.

V. EXPERIMENTAL RESULTS

To verify the effectiveness of the proposed converter, pro-

totypes of the proposed converter and the conventional LLC

resonant converter are designed with following 75 W LED TV

specifications:1) input voltage range : 250 400 V;

2) hold-up time : 60 ms;

3) output voltage : 250 V;

4) output power : 75 W (250 V/0.3 A);

5) nominal switching frequency: 100 kHz.

The components which are used in the experiment are listed

in Table III. The conventional LLCresonant converter is de-

signed with low K( = Lm/Lr ) design condition to regulatethe output voltage with small frequency changes based on the

theoretical analysis. Some margin is also considered due to the

loss of the converter. The same input voltage range is applied in

designing both converters to match the size of input capacitors.

TABLE II ICOMPONENTSUSED IN THEEXPERIMENT

Fig. 19. Experimental waveforms of the proposed converter operation at min-imum input voltage. (a) Nominal state. (b) Hold-up state.

Also, the components used in both converters are the same ex-

cept the auxiliary switch and the transformers. The auxiliary

switch is newly added in the proposed converter. Although the

proposed converter does not need any frequency changes for

hold-up operation, the same transformer size is used in the ex-

periment because of the dc offset current of the magnetizing


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Fig. 20. ZVS condition at nominal input voltage. (a) Proposed converter.(b) Conventional converter.

inductor. However, the transformer in the proposed converter

can be designed to have higher magnetizing inductance to re-duce the RMS value of magnetizing inductor current. Fig. 19

shows the experimental waveforms of the proposed converter

both in nominal state operation and hold-up state operation with

theminimum input voltage condition(Vs= 250V). As expected,the proposed converter grows up its voltage gain by increasing

the duty ratio of the auxiliary switch. When no PWM gate signal

is applied to the auxiliary switch, the output voltage becomes

153 V and it increases to 250 V for hold-up state operation

with 20% duty ratio of the auxiliary switch Qa . The proposedconverter shows boost PWM operation during hold-up state and

the resonant inductor current is build up to2.4 A while theauxiliary switch is conducted. Operational comparisons of the

proposed converter and the conventionalLLCresonant converterin nominal state are represented in Fig. 20. The ZVS conditions

are achieved in both converters. Since the proposed converter

has higher magnetizing inductance, the RMS value and the peak

value of the primary current, which is the same with the reso-

nant inductor current in nominal state operation, is smaller in

the proposed converter than those of the conventional converter.

Transient response of the proposed converter is shown in Fig. 21.

Transient response is tested by changing the operational mode

of the proposed converter under the same input voltage con-

dition. Increased voltage gain is represented as the converter

changes its operational modes from nominal operation condi-

tion to hold-up time operation condition. A resonant inductor

Fig. 21. Experimental waveforms of the proposed converter in transient state:iLr , andVO.

Fig. 22. Efficiency results in the nominal state.

current overshoot is represented when the operational mode is

changed, but this overshoot can be decreased by slowly increas-

ing the duty cycle of the auxiliary switch. Efficiency results in

nominal state are shown in Fig. 22. The proposed converter hashigher efficiency over the entire load condition because the loss

made by the primary current is reduced in the proposed con-

verter. The efficiency difference becomes maximized at light

load condition when the magnetizing inductor current takes up

significant portion in the total primary current.

VI. CONCLUSION

A new HBLLCresonant converter having boost PWM oper-

ation characteristic has been proposed. By adopting the PWM

control method with an auxiliary switch, the proposedLLCreso-

nant converter reduces its frequency variation range while main-

taining the advantages of the conventional LLC resonant con-verters. Thus, high-K design with highLm becomes enabled inthe proposed converter. It makes the converter have low magne-

tizing inductor current which results in reduced conduction loss

in the proposed converter. The characteristics of the proposed

converter are verified with a 75 W prototype and it is compared

with the LLC resonant converter. Efficiency increase is repre-

sented in the proposed converter over the entire load condition

from 0.86% efficiency improvement at full load condition to

3.69% efficiency improvement at 20% load condition. The effi-

ciency results verifies that the effectiveness of the proposed con-

verter and the benefit of the proposed converter becomes max-

imized at light load condition when the magnetizing inductor


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current takes a large part in the total primary RMS current value.

Consequently, the proposed converter is expected to find wide

use for high-efficient dc/dc converter having hold-up time re-

quirements.

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In-Ho Cho (S09)receivedthe B.S.degreefrom Han-Yang University, Seoul, in 2007, and the M.S. andPh.D. degrees in the electrical engineering from theKorea Advanced Institute of Science and Technol-ogy (KAIST), Daejeon, Korea, in 2009 and 2013,respectively.

He is currently with LG Electronics. His mainresearch interests include dc/dc converter, power-

factor-correction (PFC) ac/dc converters, and serverpower system.

Young-Do Kim(S08) was born in Korea, in 1983.He received the B.S. degree in the electrical engi-neering and computer science Kore, the M.S. degreein automobile engineering, and the Ph. D degrees inthe electrical engineering from the KAIST, Daejeon,Korea, in 2006, 2008, and 2013, respectively.

He is currently a Senior Engineer in Power R&Dteam of Samsung Electro-Mechanics Company, Ko-rea. His main research-interests are dc/dc converters,

power-factor-correction (PFC) ac/dc converters, soft-switching technique, sever power supply, and note-

book adapter.

Gun-Woo Moon(S92-M00) received the M.S. andPh.D. degrees in electrical engineering from the Ko-rea Advanced Institute of Science and Technology(KAIST), Daejeon, in 1992 and 1996, respectively.

He is currently a Professor in the Department ofElectrical Engineering, KAIST. His research inter-ests include modeling, design and control of powerconverters, soft-switching power converters, resonantinverters, distributed power systems, power-factorcorrection, electric drive systems, driver circuits ofplasma display panels, and flexible ac transmission

systems.

Dr. Moon is a Member of the Korean Institute of Power Electronics (KIPE),Korean Institute of Electrical Engineers (KIEE), Korea Institute of Telematicsand Electronics (KITE), Korea Institute of Illumination Electronics and Indus-trial Equipment (KIIEIE), and Society for Information Display (SID).

2014 ieee a half-bridge llc resonant converter adopting

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