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A SERIES-PARALLEL RESONANT CONVERTER FOR
ELECTROCHEMICAL WASTEWATER TREATMENT
By
KATHRYN M. KLEMENT
A thesis submitted to the
Department of Electrical and Computer Engineering
in conformity with the requirements for
the degree of Master of Applied Science
University of Toronto
Toronto, Ontario, Canada
© Copyright by Kathryn M. Klement (2009)
ii
Abstract
A Series-Parallel Resonant Converter for Electrochemical Wastewater Treatment
Kathryn M. Klement
Master of Applied Science
Department of Electrical & Computer Engineering
University of Toronto
(2009)
Advantages of electrochemical wastewater treatment over conventional wastewater treatment
include its smaller footprint, modularity, and ability to meet increasingly stringent government
regulations. A power supply that can be packaged with an electrochemical stack could make
electrochemical wastewater treatment more cost-effective and scalable.
For this application, the series and series-parallel resonant converters are suitable power
converter candidates. With an output current specification of 100A, the series-parallel resonant
converter (SPRC) is superior due to its simpler output stage.
The thesis presents the design of a 500W SPRC for a wastewater treatment cell stack. A
rudimentary cell model is derived experimentally. The closed loop analysis, controller design
and simulation results are presented. The output voltage and current are estimated using sensed
quantities extracted from the high voltage, low current primary side. Low voltage experimental
results verify the operation of the power stage and voltage estimation circuitry in open loop
pulsed operation.
iii
Acknowledgements
I would like to express my deepest gratitude to Professor Francis Dawson for his invaluable
guidance, encouragement and support throughout this work.
I would also like to thank my co-supervisor Professor Steve Thorpe for his guidance on the
electrochemical aspects of this work.
I thank Xogen Technologies Inc. and in particular Angella Hughes for supporting this project.
For their technical input, I would like to thank Professor Peter Lehn, Professor Don Kirk and
Professor Aleksandar Prodic.
For their technical guidance, administrative support, and help in general, I would like to thank
Lorie Roberts, Ryan Gilliam, Amgad El-Deib, Hamid Timorabadi, Jim Prall and Belinda Li.
Finally, I thank my family and friends for their support and encouragement.
Funding for this project was generously provided by Xogen Technologies Inc., the Ontario
Centres of Excellence and the Natural Sciences and Engineering Research Council of Canada.
iv
Table of Contents
Abstract ........................................................................................................................................... ii
Acknowledgements ........................................................................................................................iii
Table of Contents ........................................................................................................................... iv
List of Tables .................................................................................................................................vii
List of Figures ..............................................................................................................................viii
List of Symbols ............................................................................................................................xiii
List of Abbreviations...................................................................................................................xvii
Chapter 1 Introduction ................................................................................................................ 1
1.1. Scope of Thesis ................................................................................................................. 4
1.2. Thesis Objectives .............................................................................................................. 5
1.3. Thesis Organization........................................................................................................... 7
Chapter 2 Electrochemical Load Characterization ..................................................................... 8
2.1. Overview of Electrochemical Cells................................................................................... 8
2.1.1. Basic Cell Structure.................................................................................................... 8
2.1.2. Electrical Double Layer ........................................................................................... 10
2.1.3. Electrochemical Cell Model..................................................................................... 12
2.1.4. Pulsed versus Steady State Electrochemical Processes............................................ 14
2.2. Experimental Apparatus .................................................................................................. 17
2.3. Voltage Regime Selection ............................................................................................... 19
2.4. Model Identification........................................................................................................ 21
2.4.1. Pulse Tests ................................................................................................................ 22
2.4.2. Cyclic Voltammetry.................................................................................................. 23
v
2.5. Model under consideration.............................................................................................. 25
Chapter 3 Converter Selection and Design............................................................................... 28
3.1. Resonant Converter Options ........................................................................................... 28
3.2. Steady state converter analysis........................................................................................ 30
3.3. Series Resonant Converter Design.................................................................................. 34
3.3.1. Output Filter ............................................................................................................. 34
3.3.2. Transformer Design.................................................................................................. 36
3.3.3. Open Loop Transient Studies: Design of Q ............................................................. 40
3.3.4. Design Summary...................................................................................................... 45
3.3.5. Small signal model ................................................................................................... 46
3.4. Series-Parallel Resonant Converter Design .................................................................... 55
3.4.1. Output filter .............................................................................................................. 55
3.4.2. Transformer Design.................................................................................................. 56
3.4.3. Open Loop Transient Studies: Design of Q ............................................................. 56
3.4.4. Design Summary...................................................................................................... 61
3.4.5. Small signal model ................................................................................................... 63
3.5. Rectifier........................................................................................................................... 69
3.5.1. Schottky versus synchronous rectification............................................................... 69
3.5.2. Standard full wave rectifier versus current doubler rectifier.................................... 70
3.6. Choice of Converter Topology........................................................................................ 76
Chapter 4 Closed Loop Design................................................................................................. 78
4.1. Voltage and Current Estimation ...................................................................................... 80
4.2. Gating signal generator ................................................................................................... 84
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4.3. Small Signal Model......................................................................................................... 84
4.4. Current sensor and compensator ..................................................................................... 86
4.5. Voltage sensor and compensator ..................................................................................... 88
Chapter 5 Experimental Results ............................................................................................... 94
5.1. Prototype circuit board .................................................................................................... 94
5.2. Steady state circuit verification ....................................................................................... 95
5.2.1. Gating waveforms .................................................................................................... 95
5.2.2. Resonant tank waveforms ........................................................................................ 97
5.2.3. Output waveforms .................................................................................................... 99
5.3. Pulsed circuit verification under open loop conditions................................................. 102
5.4. Voltage estimation verification...................................................................................... 104
5.5. Discussion ..................................................................................................................... 105
Chapter 6 Conclusions, Contributions and Future Work ........................................................ 107
6.1. Contributions................................................................................................................. 108
6.2. Future Work................................................................................................................... 108
References ................................................................................................................................... 110
Appendix A Magnetics............................................................................................................ 114
A.1. Output Filter Inductors .............................................................................................. 114
A.2. Series Resonant Inductor ........................................................................................... 117
Appendix B Prototype Circuit Parts List ................................................................................ 123
Appendix C Prototype Circuit Schematics ............................................................................. 124
vii
List of Tables
Table 2.1: Effect of voltage on removal of E. Coli, BOD and NH3 at 1.25V, 2.0V and 2.5V....... 20
Table 2.2: Curve fit data for the Butler-Volmer and exponential models. .................................... 23
Table 2.3: Summary of CV results at half cell voltages of interest, neglecting the electrolyte iR
drop................................................................................................................................................ 24
Table 2.4: Estimated actual half cell potentials and system efficiency. ........................................ 25
Table 3.1: Comparison between SRC and SPRC topologies. ....................................................... 30
Table 3.2: Resonant tank parameters for the SRC and SPRC topologies. .................................... 33
Table 3.3: Transformer parameter definitions. .............................................................................. 38
Table 3.4: SRC parameter and component values......................................................................... 46
Table 3.5: SPRC parameter and component values. ..................................................................... 62
Table 3.6: Comparison between SRC and SPRC device ratings................................................... 76
viii
List of Figures
Figure 1.1: Conventional wastewater treatment plant [1]. .............................................................. 2
Figure 1.2: Electrochemical wastewater treatment plant [1]........................................................... 3
Figure 1.3: Power supply connected to a rudimentary model of the electrochemical load. ........... 5
Figure 2.1: Basic water electrolysis cell.......................................................................................... 9
Figure 2.2: Basic schematic of the electrical double layer. ........................................................... 11
Figure 2.3: Basic large signal circuit model for an electrochemical cell. ..................................... 12
Figure 2.4: Schematic of Faradaic current as a function of overpotential (the Butler-Volmer
equation)........................................................................................................................................ 13
Figure 2.5: Linearized equivalent cell circuit model..................................................................... 13
Figure 2.6: Experimental apparatus for electrochemical cell studies in wastewater..................... 17
Figure 2.7: Cell circuit model and control loop. ........................................................................... 18
Figure 2.8: Wastewater temperature at 5 minute intervals during each voltage regime experiment.
....................................................................................................................................................... 19
Figure 2.9: Half cell (anodic) voltage decay under open circuit conditions. ................................ 23
Figure 2.10: Cyclic voltammetry curve for the 2 plate cell in wastewater, 0.01V scan rate......... 24
Figure 3.1: Series resonant converter with LC resonant tank. ...................................................... 29
Figure 3.2: Series-parallel resonant converter with LCC resonant tank. ...................................... 29
Figure 3.3: Gating of input switches Q1, Q2, Q3, and Q4, and the resonant tank input voltage Vs.
....................................................................................................................................................... 32
Figure 3.4: Sample input voltage and resonant current waveforms for a converter above
resonance (zero voltage switching). .............................................................................................. 32
Figure 3.5: Conversion ratio as a function of normalised switching frequency and Q factor for the
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(a) SRC and (b) SPRC................................................................................................................... 34
Figure 3.6: EE core schematic....................................................................................................... 40
Figure 3.7: Equivalent circuit, neglecting the transient response of the output filter. .................. 41
Figure 3.8: Effect of Q on the SRC equivalent circuit transfer function poles. ............................ 42
Figure 3.9: SRC open loop transient response for Q = 4. ............................................................. 43
Figure 3.10: SRC open loop transient response for Q = 0.1. ........................................................ 43
Figure 3.11: SRC open loop transient response for Q = 1.6. ........................................................ 46
Figure 3.12: Equivalent converter circuit for model. .................................................................... 48
Figure 3.13: Response of output voltage to an input voltage step, for the generalized average
model versus circuit simulation..................................................................................................... 51
Figure 3.14: SRC frequency-to-output current transfer function at full and half rated loading
conditions. ..................................................................................................................................... 54
Figure 3.15: Poles of the frequency-to-output current transfer function....................................... 54
Figure 3.16: Equivalent circuit, neglecting the transient response of the output filter. ................ 57
Figure 3.17: Effect of Q on the poles of the SPRC equivalent circuit transfer function............... 58
Figure 3.18: SPRC open loop transient response for Q = 4. ......................................................... 59
Figure 3.19: SPRC open loop transient response for Q = 0.1. ...................................................... 60
Figure 3.20: SPRC open loop transient response for Q = 1. ......................................................... 60
Figure 3.21: Conversion ratio curves for minimum and maximum Q, at Cp/Cs = 1.................... 61
Figure 3.22: SPRC open loop transient response for Q = 1 at N = 96. ......................................... 62
Figure 3.23: Equivalent converter circuit for model. .................................................................... 63
Figure 3.24: Response of output voltage to an input voltage step, for the generalized average
model versus circuit simulation..................................................................................................... 66
x
Figure 3.25: SPRC frequency-to-output current transfer function at full and half rated loading
conditions. ..................................................................................................................................... 68
Figure 3.26: SPRC with standard full wave rectifier (top) and current doubler rectifier (bottom).
....................................................................................................................................................... 70
Figure 3.27: Current doubler circuit (top) with modes of operation for Vprim > 0 (bottom left) and
Vprim < 0 (bottom right) . ............................................................................................................... 71
Figure 3.28: Primary and secondary waveforms for the SPRC with full wave rectifier............... 72
Figure 3.29: Primary and secondary waveforms for the SPRC with current doubler rectifier. .... 72
Figure 3.30: Step response for the SPRC with current doubler versus standard full wave rectifier.
....................................................................................................................................................... 75
Figure 4.1: Cascade control system with inner current control and outer voltage control loop. .. 78
Figure 4.2: Equivalent cell circuit model load impedance............................................................ 79
Figure 4.3: SPRC with high side voltage and current sensing. ..................................................... 81
Figure 4.4: Thevenin equivalent circuit of the output filter. ......................................................... 82
Figure 4.5: Precision rectifier circuit............................................................................................. 83
Figure 4.6: Sample waveform for the precision rectifier circuit fed with 2Vpk-pk square wave at
100kHz. ......................................................................................................................................... 83
Figure 4.7: Voltage controlled oscillator transfer function............................................................ 84
Figure 4.8: Bode plots of the frequency-to-output current transfer functions at rated and half
rated load. ...................................................................................................................................... 86
Figure 4.9: Bode plots of current loop HiGifGfc. ........................................................................... 87
Figure 4.10: Simulated output current for current loop control at rated load (top) and half rated
load (bottom). ................................................................................................................................ 88
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Figure 4.11: Reference-to-secondary voltage transfer functions. ................................................. 90
Figure 4.12: Closed loop transfer function for the system with PI compensator. ......................... 91
Figure 4.13: Closed loop transfer function with 2nd order LPF for noise rejection. .................... 91
Figure 4.14: Closed loop simulation results at nominal load........................................................ 92
Figure 4.15: Closed loop simulation results at half rated load...................................................... 92
Figure 5.1: Prototype circuit.......................................................................................................... 95
Figure 5.2: Full bridge gating waveforms at 103kHz. .................................................................. 96
Figure 5.3: Gating delays between switches on the same leg of the full bridge. .......................... 96
Figure 5.4: Input voltage to the resonant tank, Vs, at Vg = 50V. ................................................... 97
Figure 5.5: Series resonant inductor voltage, vLs, and its integral, which is used to estimate the
series resonant current, iLs. ............................................................................................................ 98
Figure 5.6: Magnification of vLs and its integral showing the extent to which resonant current
lags the input voltage..................................................................................................................... 98
Figure 5.7: Steady state voltage across the series resonant capacitor, vCs, (left) and voltage across
the parallel resonant capacitor, vCp, (right).................................................................................... 99
Figure 5.8: Voltage across the transformer secondary winding, vsec. .......................................... 100
Figure 5.9: Drain-to-source voltage, vds1, and gating signal, SR1,gate, for one sychronous rectifier
MOSFET. .................................................................................................................................... 101
Figure 5.10: The sum of the drain-to-source voltage across each synchronous rectifier switch,
giving the rectified secondary side voltage. ................................................................................ 101
Figure 5.11: Converter output voltage. ....................................................................................... 102
Figure 5.12: 10Hz pulsed output voltage. ................................................................................... 103
Figure 5.13: Evolution of vout and vCp at the beginning of a pulse.............................................. 103
xii
Figure 5.14: Magnification of the turn on transient for vout and vCp. .......................................... 104
Figure 5.15: Actual and estimated output voltage....................................................................... 105
Figure 5.16: Magnification of actual and estimated output voltage............................................ 105
xiii
List of Symbols
ℓe Effective magnetic path length
ℓm Magnetic path length
α Symmetry factor in Butler-Volmer equation
β Magnetic core loss exponent
η Electrochemical overpotential
λ1 Volt-seconds applied to the transformer primary winding
µ Magnetic permeability
ρ Effective wire resistivity
τci Output current-to-control transfer function time constant
τcv Output voltage-to-control transfer function time constant
φshift Angular phase shift
ωs Angular switching frequency
ω2fs Angular frequency corresponding to double the switching frequency
Ac Cross sectional magnetic core area
AL Effective magnetic core inductance
B Magnetic flux density
Cdl,a/c Double layer capacitance at the anode/cathode
Cf Output filter capacitor
Cleg Snubber capacitor
Cp Parallel resonant capacitor
Cs Series resonant capacitor
CT Equivalent total resonant capacitance
xiv
EOCP Open circuit potential
F Faraday’s constant
f0 Resonant frequency
fs Converter switching frequency
Gci Output current-to-control transfer function
Gcv Output voltage-to-control transfer function
Gfc Control-to-frequency transfer function
Gif Frequency-to-output current transfer function
H Magnetizing field intensity
Hi Current sensor gain
Hv Voltage sensor gain
Idc Inductor dc bias current
iest Estimated output current
if,a/c Faradaic current at the anode/cathode
ÎL Peak inductor current
iLf Output filter inductor current
iLs Series resonant inductor current
io Exchange current density
Iout Output current
iref Reference current
Itot Total rms winding currents, referred to the transformer primary winding
Kci Output current-to-control transfer function gain
Kcv Output voltage-to-control transfer function gain
xv
Kfe Transformer core loss coefficient
Kgfe Magnetic transformer core size
Ku Transformer winding fill factor
Lf Output filter inductor
Lm Magnetizing inductance
Ls Series resonant inductor
M Input-to-output voltage gain of a power converter
n Number of electrons involved in an electrochemical reaction
N Transformer winding ratio
n1 Number of primary transformer winding turns
n2 Number of secondary transformer winding turns
PCu Power dissipated in transformer copper windings
PFe Power dissipated in transformer iron core
Ptot Total transformer power dissipation
Q Quality factor
R Ideal gas constant
Re Effective ac load resistance
Relec Electrolyte resistance
Req Effective ac load resistance referred to the transformer primary winding
Rf,a/c Faradaic resistance at the anode/cathode
Rint,a/c Interfacial resistance at the anode/cathode
t Time
T Temperature
xvi
tδ Commutation interval length
Ts Converter switching period
tshift Time shift in phase shift controller
WA Transformer core window area
v1 Primary transformer voltage
va/c Half cell voltage at the anode/cathode
vaux Transformer auxiliary winding voltage
vc Control voltage
vCf Output filter inductor voltage
vCp Parallel resonant capacitor voltage
vCs Series resonant capacitor voltage
Vcell Total voltage across an electrochemical cell
VDD Logic supply voltage
vest Estimated output voltage
Vg Input voltage to power converter
Vo Output voltage
Voff,a/c Equivalent offset voltage at the anode/cathode in a linearized circuit model
Vout Output voltage
Vref Reference voltage
Vs Input voltage to resonant tank
vsec Transformer secondary winding voltage
Z0 Resonant tank impedance
ZL Equivalent load impedance
xvii
List of Abbreviations
AWG American wire gauge
BOD Biological oxygen demand
CE Counter electrode
CFU Colony-forming unit
CV Cyclic voltammetry
E. Coli Escherichia Coli
EIS Electrochemical impedance spectroscopy
EMI Electromagnetic interference
IHP Inner Helmholtz plane
LPF Low pass filter
MLT Mean length per turn
OF Output filter
OHP Outer Helmholtz plane
PCB Printed circuit board
PED Pulse electrodeposition
xviii
PI Proportional integral
RE Reference electrode
SA Surface area
SHE Standard hydrogen potential
SMPS Switched mode power supply
SPRC Series-parallel resonant converter
SRC Series resonant converter
SS Suspended solids
VCO Voltage-controlled oscillator
WE Working electrode
1
Chapter 1 Introduction
Electrochemical wastewater treatment (EWT) is a promising alternative to conventional
wastewater treatment due to its ability to address increasingly stringent government regulations
in developed countries as well as its potential to meet the needs of developing communities with
inadequate water treatment.
In most developed nations, before wastewater is discharged into a natural body of water, it must
be treated to meet regulations specific to the location where the water is discharged. These
regulations typically include limits on the following 5 parameters:
Suspended solids (SS),
Total phosphorus (Tot. P),
Biological oxygen demand (BOD),
Escherichia Coli (E. Coli), and
Ammonia (NH3).
To address all 5 of these parameters, wastewater treatment is conventionally accomplished
through a number of biological and chemical steps which take a long time and require a
relatively large footprint. A typical schematic for a conventional wastewater treatment plant is
shown in Figure 1.1.
In contrast, electrochemical wastewater treatment is accomplished by one or more of the
following four electrochemical processes [2]:
2
In metal recovery, metal ions in the water are reduced and deposited on the cathode.
In electrocoagulation, pollutants adsorb to dissolved ions and then are floated out of the
water by generated hydrogen gas.
In electroflotation, pollutants are floated to the surface by oxygen and hydrogen bubbles
that are generated by water electrolysis.
In electrooxidation, new species such as peroxides are formed, which destroy pollutants in
the water.
Because no biological steps are involved, electrochemical wastewater treatment occurs on much
shorter timescales and therefore requires a smaller footprint to treat the same volume of water.
Moreover, an “all in one” electrochemical wastewater treatment process which incorporates more
than one of the above processes to address multiple regulatory parameters could significantly
reduce the number of steps required in a conventional plant, as shown in Figure 1.2. Therefore,
the process is easily scalable, lending itself to distributed wastewater treatment which could be
tailored to a range of community sizes.
Figure 1.1: Conventional wastewater treatment plant [1].
3
Figure 1.2: Electrochemical wastewater treatment plant [1].
Electrochemical wastewater treatment is currently employed by some companies to remove
metals being discharged into bodies of water. One major stumbling block in the adaption of
electrochemical wastewater treatment technologies for other purposes, such as urban wastewater
treatment needs, has been the associated cost of electricity. The development of new materials
and electrode geometries has the potential to significantly increase the efficiency of these
processes, making them commercially viable. Advances in power electronics have also made it
possible to design cheaper, more efficient and more versatile power supplies for these
technologies.
As mentioned above, one of the benefits of electrochemical wastewater treatment is its scalability.
One cell stack can operate alone or many stacks can be combined for a large scale process. By
assigning one power supply to each cell stack, each module would be self contained, thus taking
advantage of economies of scale and allowing for individual control over each cell stack.
4
Difference in wastewater composition over several cell stacks could therefore be dealt with by
the control loop in each module, similar to the distribution of microconverters in a photovoltaic
array. Currently, no power supply for distributed electrochemical wastewater treatment exists.
1.1. Scope of Thesis
This thesis deals with the design of a power supply for an electrochemical wastewater treatment
cell. To optimize cell operation, a nonlinear electrical model of the cell which includes reaction
chemistry, thermal characteristics and plate degradation with time would be required. This
would allow tight control around an optimal operating point to prolong cell life and maximize
efficiency. For the purpose of this work, an electrical model which captures the salient aspects of
cell behaviour from an electrical point of view will suffice so that the appropriate type of
converter and control strategy can be chosen. A simple electrical model will be used which is
linearised around an operating point of interest. This model includes the cell’s double layer
capacitance, Cdl, associated with the space charge region at each interfacial boundary, the
effective resistance associated with the current flowing across each interfacial boundary, Rint, and
the resistance of the electro-neutral electrolyte between the plates Relec. Reaction chemistry,
electro-thermal characteristics, plate degradation and other non-idealities are neglected. Only
voltage and current are sensed and controlled by the supply, as shown in Figure 1.3.
5
Figure 1.3: Power supply connected to a rudimentary model of the electrochemical load.
1.2. Thesis Objectives
The objective of this thesis is the design and verification of a prototype power converter for
electrochemical wastewater treatment. The supply must satisfy the following criteria.
• Galvanic isolation - For safety, the load should be connected to the source through a
transformer so there is no direct current path. This also allows a number of supplies to be
connected in parallel for a higher output power without generating a ground fault current.
• High power density - This means that a converter could be mounted directly onto a cell
stack for ease of manufacturing and modularity. To achieve high power density, the
converter would be required to operate at a high switching frequency with high efficiency
to minimize the required surface area to extract heat, and the topology should be selected
for a low component count.
• High efficiency - In addition to affecting the power density, high efficiency would lead to
minimum operating costs for the system and minimum carbon footprint.
6
• Low energy storage - The supply should store as little energy as possible so that if there is
a short, the energy dissipated is low, and under open circuit conditions (for example, in
case of a cell void), a small amount of energy is dissipated and the risk of causing a spark
which could ignite the combustible hydrogen oxygen gas mixture is minimized. This
requirement also requires a high switching frequency which satisfies the output ripple
current requirements.
• Inherent self protection - A current control loop built into the controller would limit the
output current to protect the switches in the converter under short circuit conditions. An
overvoltage situation under open circuit conditions (e.g., if the cell is voided) can be
mitigated by placing a voltage clamp (surge suppressor) across the output terminals of the
cell.
• Modularity - A modular supply means lower cost per unit by taking advantage of
economies of scale. An inner current control loop allows converters to be paralleled
while guaranteeing current sharing so modularity is ensured.
• Compliance with electromagnetic interference (EMI) requirements - This means low
ripple current is required on the output to minimize EMI. This and the fact that the load
is capacitive necessitate an inductor at the output of the converter. The low ripple current
requirement is also important to maintain a constant voltage across the capacitive
interfacial region in the cell so as to remain in the desired reaction regime. Thus, this
requirement may be stricter depending on the effective capacitance, as related to the area
of the plate.
• Variable frequency pulsing capability - Pulsing has been shown to improve process
7
efficiency and treatment times; however, flexibility in adjusting the frequency, pulse
width, and pulse amplitude is required to take advantage of the number of different
reaction time constants in the system.
1.3. Thesis Organization
Chapter 2 provides an overview of electrical modeling of electrochemical cells. Experimental
results of tests performed on a bench scale cell are presented and from these results, an operating
point and rudimentary cell model are derived.
Chapter 3 provides an overview of resonant converters and a comparison between the series
resonant converter (SRC) and series-parallel resonant converter (SPRC) topologies. The SPRC
topology is shown to be superior for this application.
Chapter 4 details a cascade controller design for the SPRC converter, which uses estimates of the
output voltage and current based on measurements performed on the high voltage, low current
primary side of the transformer. Simulations are presented to verify the design.
In Chapter 5, low voltage steady state and open loop pulsed experimental results from the
prototype SPRC converter are presented.
The final chapter contains conclusions, contributions and future work.
8
Chapter 2 Electrochemical Load Characterization
In this chapter, a model for the electrochemical load is developed using experimental results.
Section 2.1 provides a basic overview of electrochemical cell operation and modeling. Section
2.2 describes the experimental apparatus. Experimental results and the model development are
given in section 2.3. Section 2.4 gives the experimental motivation for selecting a specific
operating point. Section 2.5 identifies the cell models to be used over the full operating range for
the converter design.
2.1. Overview of Electrochemical Cells
The purpose of this survey is to provide sufficient background for the reader to understand how
the cell model arises and the experimental techniques used to identify it. The interested reader is
referred to [3] and [4] for a more detailed treatment of cell operation and to [3]-[6] for details on
transient analysis techniques.
2.1.1. Basic Cell Structure
An electrochemical cell is composed of an anode and cathode immersed in an electrolyte, as
shown in Figure 2.1. An external voltage is applied between the plates via an external circuit,
completing the path for current to flow in the system as follows. An electron leaves the negative
terminal of the power supply and moves to the cathode, where a charge transfer reaction occurs
between the electron and a molecule on the cathode surface. This reaction produces a negatively
charged ion which crosses the electrolyte to the anode. At the anode, a second charge transfer
reaction transfers the electron to the anode and it moves through the external circuit to the
positive terminal of the power supply. Therefore, an electric current flows through the external
circuit from the cathode to the anode and an ionic current flows through the electrolyte from the
9
anode to the cathode. The charge transfer reactions occurring at each cell plate are called half
cell reactions.
Although different types of electrolytes exist including non-aqueous liquids, solids, and molten
electrolytes, only aqueous electrolytes will be treated here because this work deals with
wastewater, an aqueous solution. Figure 2.1 shows an example of the most basic
electrochemical cell with an aqueous electrolyte, the water electrolysis cell. Water electrolysis is
the process by which water is split into hydrogen and oxygen. The half cell reactions are given
in 2.1 and 2.2. Transfer of electrons at the cathode produces hydroxide ions (OH-) and hydrogen
gas (H2), which bubbles to the surface. The hydroxide ions flow through the electrolyte to the
anode, where the charge transfer produces oxygen gas, O2, and water.
Cathode: 2H2O + 2e- H2 + 2OH- (2.1)
Anode: 2OH- ½O2 + H2O + 2e- (2.2)
Figure 2.1: Basic water electrolysis cell.
10
2.1.2. Electrical Double Layer
Each half cell reaction that occurs in the system is driven by a half cell potential, which is the
potential difference across the interface between the electrode and electrolyte. To understand the
behaviour of this interface requires an understanding of the electrical double layer. An electrical
double layer forms at the interface between any two media containing charged species [4], in this
case, the electrode-electrolyte interface. Near a phase boundary, the forces acting upon a particle
are anisotropic (directionally dependent) due to the existence of that boundary. The result is that
on one phase, an excess of negative charge gathers at the interface and on the other phase, an
excess of positive charge gathers. This charge separation forms a dipole, which, macroscopically,
can be represented in a circuit model by a capacitor. This effective capacitor is referred to as the
“double layer capacitance”, which is expressed per unit area since the total capacitance of the
interface depends on the area of that interface.
The basic structure of the electrical double layer is shown in Figure 2.2. The double layer
consists of 3 regions: the inner Helmholtz plane (IHP), the outer Helmholtz plane (OHP), and the
diffusion layer. The IHP is comprised of a layer of adsorbed ions and water molecules; its
location is defined by the centres of the adsorbed ions. The OHP is a layer of nonadsorbed,
hydrated ions and its location is defined by the centres of those ions. Beyond the OHP lies the
diffuse region, a region of positive ions whose concentration decays exponentially to balance the
electrode charge density [4].
With no external voltage applied, there exists some potential difference across the double layer
capacitance due to the charge separation. Because this potential difference occurs over a very
short distance (a few atomic lengths) an electric field as strong as 107 V/cm is formed [4]. An
applied voltage shifts this system away from equilibrium, changing the potential difference at the
11
interface (the half cell voltage), which increases the electric field, causing half cell reactions to
occur. The reactions that occur depend on the size of that potential difference.
Figure 2.2: Basic schematic of the electrical double layer.
Although macroscopically the electrified interface acts like a parallel plate capacitor, it differs
from a parallel plate capacitor in two ways: (i) the capacitance is dependent on the potential drop
and (ii) the electric field variation in the interfacial region is nonlinear with respect to position.
As a result, a number of different models have been created for the double layer, which are
described in detail in [4].
12
2.1.3. Electrochemical Cell Model
A basic circuit model for an electrochemical cell is shown in Figure 2.3. The electrolyte is
represented by a resistor Relec while each interface is represented by a capacitor Cdl,c/a in parallel
with a voltage-dependent current source if,c/a. Each current source represents the faradaic process
current which arises from the voltage-dependent reactions at the interface. If more than one
reaction occurs in the system, this current source could be expressed as a parallel combination of
current sources where each source represents one reaction.
Figure 2.3: Basic large signal circuit model for an electrochemical cell.
In the simplest model assuming activation-controlled reactions only (where the reactions
occurring are not limited by diffusion), the behaviour of the voltage-dependent current source
follows equation 2.3, the Butler-Volmer equation, which expresses the Faradaic current density, if,
as a function of the overpotential, η = va/c – EOCP. EOCP is the open circuit potential which arises
across the double layer capacitance with no electric current flowing in the system.
−−
−= ηα
ηα
RT
nF
RT
nFii f exp
)1(exp0 (2.3)
In this equation, io is the exchange current density, α is a symmetry factor, n is the number of
13
electrons involved in the reaction, F is Faraday’s constant, R is the ideal gas constant, and T is
the temperature. The result, if, is a current density expressed in mA/cm2, which can be
multiplied by the effective plate area to obtain the total current. This relationship is plotted for α
= 0.5 in Figure 2.4. In practice, α = 0.5 is a good approximation for many electrochemical
reactions; however, it can be significantly higher or lower than 0.5. A more detailed discussion
of the origin of this symmetry factor can be found in [4].
Figure 2.4: Schematic of Faradaic current as a function of overpotential (the Butler-Volmer equation).
Linearizing this model about an operating point gives the circuit model shown in Figure 2.5. For
low overpotential η, the current source appears as a linear Faradaic resistance of the form Rf =
RT/AnioF. For higher overpotentials, the current source can be expressed as an offset voltage in
series with a resistance Rf.
Figure 2.5: Linearized equivalent cell circuit model.
14
2.1.4. Pulsed versus Steady State Electrochemical Processes
Electrochemical wastewater treatment is conventionally performed as a steady state process,
whereby the system is operated at one voltage or current set point. However, it is possible to
make gains in the efficiency of the process by pulsing the waveform rather than operating in
steady state. The largest body of literature available on pulsed electrochemical processes is on
pulsed plating, which is a pulsed form of electrodeposition commonly used for electric contacts
and printed circuit boards. To provide insight into how pulsing could aid in other
electrochemical processes, a brief review of pulse plating will be provided in this section.
In electrodeposition, a conductive object is placed in an electrolyte bath containing metal ions
and a current is passed between that object and an anode. The current reduces metal ions in the
solution so that the metal deposits onto the object. Generally, this process uses a direct current,
but pulse electrodeposition (PED) is also used. In PED, the current is pulsed in either a unipolar
sense (on then off) or a bipolar sense (positive then negative).
The advantages of PED are as follows:
1. The double layer at the cathode surface discharges between pulses so that there is less
obstruction to ion flow from the solution to the electrode [7] and adsorption and
desorption can occur more easily [8].
2. It there is uneven current distribution and therefore uneven ion depletion in the
electrolyte, ions are able to migrate to the depleted portions during the off time so that
they are distributed more evenly over the electrode surface [7]. This is a significant
advantage for plating because it increases “throwing power”, the ability of a solution to
deposit into recessed areas.
15
3. To obtain the same average current density as in the dc case, much higher instantaneous
current densities are achieved. Higher instantaneous current density causes higher
overpotential at the electrode, which influences which reactions occur and the ratio in
which reactions of different kinetics occur [8]. Therefore, it is possible to improve the
current efficiency of a desirable reaction (the percentage of total current that goes into
that reaction) by pulsing.
According to Chandrasekar [7], the primary disadvantages of PED are (i) increased cost of the
power supply and (ii) more planning required for developing a process control algorithm since
there are three variables to set (current amplitude, on time, and off time) rather than one (current
amplitude).
In selection of the three variables for pulse electrolysis, two primary effects must be taken into
consideration: (i) charging of the double layer and (ii) mass transport effects. Although detailed
analysis of these phenomena are outside the scope of this work, the interested reader is referred
to [8]-[12] for more information.
2.1.4.1. Modeling of a pulse
Although detailed modeling of each pulse is beyond the scope of this work, this section provides
an analysis of how the circuit models of section 2.1.3 behave under pulsing. An experimental
comparison of these models is provided in section 2.4.1.
Take a simple case of a current step from some constant value to 0. When the current is shut off,
no net current is flowing through the system so at each interface, the double layer capacitor
current will be equal to that of the dependent current source of Figure 2.3. Assuming this half
cell behaviour is given by the Butler-Volmer equation and the simplified circuit of Figure 2.3
16
applies, the following equation is obtained, where v is the half cell voltage under consideration.
−−
−
−−
=− )(exp)()1(
exp0 OCPOCPdl EvRT
nFEv
RT
nFAi
dt
dvC
αα (2.4)
Assuming that α = 0.5, the Butler-Volmer equation simplifies to a hyperbolic sine function.
−=− )(2
sinh2 0 OCPdl EvRT
nFAi
dt
dvC (2.5)
Then, applying separation of variables and integrating each side gives the following relationship
between voltage and time.
00
)(4
tanhln1
tEvRT
nFC
nF
RT
Ait OCPdl +
−−= (2.6)
In contrast, if an operating point is assumed, the more classical model is obtained where the
voltage-dependent current sources are replaced by Faradaic resistances. For this case, the current
response is:
f
dlR
v
dt
dvC =− (2.7)
where the Faradaic resistance can be obtained by taking the first term in a Taylor series of the
Butler-Volmer equation:
nF
RT
AiR f
0
1= (2.8)
The analogous voltage-time relationship for the Faradaic resistance case is then as follows:
OCP
dl
EttCRT
nFAivv +
−−= )(
1exp 000 (2.9)
A similar expression exists for the other electrode as well; hence, the total cell voltage will be a
sum of the two half cell voltages as well as the electrolyte voltage drop.
17
2.2. Experimental Apparatus
The electrochemical cell under study consists of 2 electrodes made from 316 stainless steel.
Each electrode measures 5cm x 7.5cm. They are bolted in place at a constant distance of 2mm
using Teflon spacers at each corner. The electrode assembly is designed for wastewater which
was been screened through a 1mm screen so the 2mm gap is small enough to minimize the
electrolyte iR losses while preventing plugging of the plates.
The cell is contained in a Plexiglas reactor which holds 1 litre of wastewater. A variable speed
peristaltic pump is used to circulate the fluid at a rate of 0 to 8 L/min. All flow is channeled
directly between the plates. The reactor is shown in Figure 2.6.
Figure 2.6: Experimental apparatus for electrochemical cell studies in wastewater.
Dissolved oxygen meter
Thermometer
Salt bridge
Sampling tube
Electrode assembly
Flow channel
18
The cell is controlled using the CHI660C Electrochemical Workstation, which can operate in
voltage or current control mode. In voltage control mode, the full cell voltage or half cell
voltage can be controlled. To control the half cell voltage, a 3 electrode configuration is required.
The electrode at which the half cell voltage is controlled is labelled the working electrode (WE).
The other electrode is labelled the counter electrode (CE) and a reference electrode (RE) is added
to the system. In these experiments, an Ag/AgCl reference electrode (RE) is used. The reference
electrode is connected to a luggin tip via a salt bridge and the luggin tip, consisting of a steel
needle with 1mm diameter, is placed between the plates, equidistant from each plate. The salt
bridge conducts ions between the reference electrode and luggin tip so that the voltage measured
between the reference and one of the electrodes consists of the half cell voltage (across the
double layer), the iR drop across the part of the electrolyte between the luggin tip and electrode,
and a constant known voltage drop across the reference electrode. The approximate cell circuit
model of Figure 2.7 can then be considered.
Figure 2.7: Cell circuit model and control loop.
To control the half cell voltage, the working electrode is grounded and the voltage of the working
electrode with respect to the reference is measured. The CHI660C then adjusts the counter
electrode voltage until the requested half cell voltage is achieved.
19
2.3. Voltage Regime Selection
Hydrogen peroxide H2O2 and ozone O3 can each play a significant role in wastewater treatment.
Three reactions involving these chemicals and the corresponding approximate half cell potential
are as follows. Each potential is written versus standard hydrogen potential (SHE).
1. O3 + 2H+ + 2e- = O2 + H2O E ~ 2.3V
2. H2O2 + 2H+ + 2e- = 2H2O E ~ 1.5V
3. O3 + H2O + 2e- = O2 + 2OH- E ~ 1.0V
Tests were performed at voltages between each regime, at 1.25V, 2.0V and 2.5V vs. SHE to
examine the relative importance of these reactions in wastewater treatment in the given bench
scale system. In each test, the half cell voltage was held constant for 2 hours and wastewater was
continuously circulated between the plates at a rate of 25cm/s. Temperature was recorded at 5
minute intervals and is plotted in Figure 2.8. The plates were held with a 2mm gap between
them but the outside of each steel plate was left exposed so not all reactions were necessarily
occurring between the plates.
Figure 2.8: Wastewater temperature at 5 minute intervals during each voltage regime experiment.
20
At the beginning and conclusion of each test, samples were analyzed for E. Coli, BOD and NH3
to determine the effectiveness of treatment. Table 2.1 summarizes the results from each test. In
each voltage regime, comparable removal of each of these 3 parameters is achieved. The main
trend that can be observed from these tests is the tradeoff between treatment time and treatment
efficiency. Over the same length of test, test 1c accomplishes the best reduction in E. Coli and
BOD with a similar reduction of NH3 compared to the lower voltage tests. If the reduction in the
regulatory parameters is normalized with respect to total charge passed, test 1a shows a
significantly better treatment per coulomb than the higher voltage regimes.
Untreated wastewater
Test 1a (1.25V vs. SHE)
Test 1b (2.0V vs. SHE)
Test 1c (2.5V vs. SHE)
Total charge passed (C)
96.6 800 1350
Average current (mA)
13.4 111 188
E. Coli Net (CFU/100mL)
3,400,000 181,000 124,000 19,000
Decrease per Coulomb (CFU/100mL/C)
33,300 4,100 2,500
BOD Net (mg/L) 96 56 50 45 Decrease per Coulomb (mg/L/C)
0.41 0.058 0.038
NH3 Net (mg/L) 26.0 2.70 3.30 2.90 Decrease per Coulomb (mg/L/C)
0.24 0.028 0.017
Table 2.1: Effect of voltage on removal of E. Coli, BOD and NH3 at 1.25V, 2.0V and 2.5V.
21
While the faster treatment can be attributed to the higher average current in test 1c, a higher
percentage of the energy is lost to: (i) heating of the bulk fluid, as seen from the temperature rise
in Figure 2.8, (ii) the generation of hydrogen and oxygen gases, as significant bubble generation
was observed during this test, and (iii) corrosion of the steel plates, as the colour of the water was
a noticeably darker reddish brown at the conclusion of this test due to removal of iron from the
stainless steel anode. A more exact analysis of relative efficiency cannot be drawn from this data
since the percentage of current going into reactions that are useful for treatment (the current
efficiency) decreases as treatment occurs and fewer reactants are available. These tests only
gesture toward average current efficiency over a fixed time period.
From these tests, it can be concluded that each voltage regime is effective in treating these 3
regulatory parameters, although a tradeoff does exist between rate of treatment and efficiency.
For a more rigorous analysis of relative efficiency, more variables would need to be taken into
account including flow rate, temperature, and retention time, which is outside the scope of the
current work.
2.4. Model Identification
To design a power supply for operation in the voltage ranges considered in the previous section,
an approximate cell model can be derived from experimental data, given that no dynamic model
exists which can be used for design purposes. The following tests are performed in order to
validate the model derived in sections 2.1.3 and 2.1.4 and to obtain an approximate numerical fit
for this model. In these tests, each cell plate is coated on the back so that reactions occur only in
the 2mm gap between the plates. Therefore, this data scales with area for larger plates and for
cell stacks.
22
2.4.1. Pulse Tests
To examine the validity of the simplified cell models of equations 2.6 and 2.9, a current pulse of
0.01A was applied to the system for 30ms to achieve a steady state half cell voltage of
approximately 1.4V. Then, the current was removed and the half cell voltage response was
measured for t > 30ms.
The voltage decay data after the current was removed was fit with the Butler-Volmer model
(equation 2.6) and the exponential model (equation 2.9). The results are shown in Figure 2.9.
The data for each fit is summarized in Table 2.2.
In the experimental results of Figure 2.9, there is a bump in the voltage decay at approximately
0.4V. This corresponds to some change in reaction regime and so to model this step response
more accurately, at least two reactions would need to be incorporated into the model. Both the
Butler-Volmer and exponential models incorporating only one reaction capture the voltage decay
accurately below 0.2V but there is a discrepancy at higher voltages (above 0.5V). This occurs
because the data was sampled at constant time intervals so most of the data set falls within this
low voltage regime. The Butler-Volmer fit has a greater sample correlation coefficient (R2 =
0.9951 compared to R2 = 0.9641 for the exponential model) despite the discrepancy in behaviour
at the beginning of this pulse, which is as expected since the exponential model is a linearized
version of the more accurate Butler-Volmer model (corresponding to the equivalent cell circuit
of Figure 2.5). The exponential model, nonetheless, captures the dynamics of an actual
electrochemical cell reasonably well. To select a power converter and control strategy, this load
model is sufficient.
23
Figure 2.9: Half cell (anodic) voltage decay under open circuit conditions.
Butler-Volmer model fit Exponential model fit
General model: t = -a*(log(abs(tanh(b*v))) + c) Coefficients (with 95% confidence bounds): a = 74.11 (74.01, 74.2) b = 3.745 (3.732, 3.757) c = -0.5757 (-0.5773, -0.5742) Goodness of fit: SSE: 6.577e+005 R-square: 0.9951 Adjusted R-square: 0.9951 RMSE: 4.055
General model: v = a*exp(-b*(t-d))+c Coefficients (with 95% confidence bounds): a = 0.81 (-1.546e+005, 1.546e+005) b = 0.03548 (0.03533, 0.03562) c = 0.04339 (0.04283, 0.04395) d = 32.15 (-5.38e+006, 5.38e+006) Goodness of fit: SSE: 57.57 R-square: 0.9641 Adjusted R-square: 0.9641 RMSE: 0.03794
Table 2.2: Curve fit data for the Butler-Volmer and exponential models.
2.4.2. Cyclic Voltammetry
In cyclic voltammetry (CV), the half cell voltage is swept between two values a specified
number of times and at a specified rate. Cyclic voltammetry was performed on the cell in
wastewater at 25ºC, where the working electrode voltage was varied at a slow scan rate
24
(10mV/s) and the current and counter electrode voltage were recorded as a function of time. The
aim of this test was to obtain some steady state modeling data in the voltage ranges considered in
section 2.3. The scan rate is slow enough that the data can be treated as steady state data. The
current versus working electrode voltage is shown in Figure 2.10. The WE voltage is plotted
versus standard hydrogen potential SHE, meaning that the voltage drop due to the Ag/AgCl
reference electrode reaction has been subtracted from the applied voltage. The working and
counter electrode potentials, however, each include the iR drop across half the electrolyte
resistance.
Figure 2.10: Cyclic voltammetry curve for the 2 plate cell in wastewater, 0.01V scan rate.
WE potential (V) CE potential (V) Total cell voltage (V)
Current (mA) Current density (mA/cm2)
1.25 -0.63 1.88 1.09 0.0352 2.0 -1.74 3.74 210 6.77 2.5 -2.07 4.6 449 14.5
Table 2.3: Summary of CV results at half cell voltages of interest, neglecting the electrolyte iR drop.
25
Automatic iR drop compensation can be performed during an experiment, as described in [15].
However, it is not practical in wastewater at these voltages because (i) the composition of the
wastewater between the plates changes as reactions occur and as the water circulates due to the
inhomogeneous nature of the water and (ii) hydrogen and oxygen bubbles are generated between
the plates during operation, changing the effective conductivity of the medium. It is not strictly
correct to do so, but if a constant wastewater conductivity is assumed, the electrolyte voltage
drop can be calculated from the current and subtracted from the WE and CE potentials. The
conductivity of wastewater sampled from Orangeville, Ontario, (the location of the industrial
collaborator) has been shown to range between approximately 1200µS/cm and 2700µS/cm, or
1950 ± 750µS/cm. From the geometry of the cell, this gives an total effective resistance of 3.3 ±
0.9Ω.
Estimated WE potential (V)
Estimated CE potential (V)
Electrolyte iR drop (V)
Electrolyte power loss (W)
% Efficiency
Total cell voltage (V)
Current (mA)
1.25 -0.63 0.0018 2.0e-6 99.9 1.88 1.09 1.65 -1.39 0.69 0.14 82 3.74 210 1.75 -1.33 1.5 0.67 68 4.6 449
Table 2.4: Estimated actual half cell potentials and system efficiency.
2.5. Model under consideration
The cyclic voltammetry results showed that at the highest voltage regime under consideration, a
2.5V half cell potential, the total cell voltage is 4.6V and the current density is 15mA/cm2. To
design for the full range of voltages, the converter design will be rated for maximum operating
voltage of 5V at 100A. At 5V, the CV test showed a current density of nearly 20mA/cm2. Using
this figure, the total effective plate area serviced by a 100A supply is 5000cm2. This could take
the form, for example, of a stack of 20 plates, 250cm2 each, connected in parallel.
26
For a metallic plate, the double layer capacitance value tends to be on the order of 50µF/cm2.
Although this value will change under different operating conditions, it can be used as a rough
approximation. Then, assuming smooth plates, the equivalent double layer capacitor at each
interface is approximately 250mF. Moreover, the effective electrolyte resistance can be
estimated based on conductivity data. Measured conductivity of wastewater collected from
Orangeville, Ontario, ranged between 1200µS/cm and 2700µS/cm. Assuming a plate spacing of
2mm, the average electrolyte resistance can be calculated for this geometry as follows:
Relec = l / σA = 0.2cm / (1950e-6 S/cm x 5000cm2) ≈ 20mΩ
Assuming the anode and cathode have identical models (in actuality, they are not identical but
still similar since the electrodes are made of the same material), one can extrapolate from the
steady state current and solution resistance to obtain a value for the equivalent interfacial
resistances at 5V:
Rint = ½ ( V/I – Relec ) = 15mΩ
Worst case loading conditions can then be determined as follows. Under 5V, 100A rated
operation, the minimum equivalent load resistance will occur for a short time momentarily after
a transient when the double layer capacitances act as short circuits and only the electrolyte
resistance appears across the converter output. The minimum equivalent resistance to design for,
therefore, should be the equivalent electrolyte resistance for effluent with maximum conductivity.
For this design, that resistance is 20mΩ.
The maximum equivalent load resistance will depend on a number of other factors, including:
total void electrolyte fraction during operation due to the generation of bubbles,
27
number operational plates (e.g., if one pair in a stack malfunctions), and
amount of oxidation or calcium formation on the electrode surfaces.
More detailed modeling of the electrochemical system is required to design for these issues. In
the interim, some safety factor can be applied to ensure the converter can operate over a large
range of loading conditions. The converter in this work will be designed for 100A rated
operation and proven to operate down to 50A (half rated loading).
28
Chapter 3 Converter Selection and Design
In this chapter, the options for the converter topology choice are examined per the requirements
outlined in section 1.2. Detailed design procedures for the series and series-parallel resonant
converters are presented, including the output filter, transformer design, transient response
considerations, rectifier, and small signal modeling. The designs are compared and conclusions
are drawn on the feasibility of each design.
As discussed in section 1.2, this converter should satisfy a number of objectives including
galvanic isolation, high power density, high efficiency, low energy storage, inherent self
protection, modularity, satisfaction of EMI regulations, and pulsed output capabilities.
3.1. Resonant Converter Options
Resonant converters are a class of switched mode power supplies that are well-suited for high
power applications that require high switching frequencies because they have very low switching
losses. In a resonant converter, a switched voltage is input to a resonant tank, exciting a
sinusoidal current. This current either lags or leads the input voltage, causing the semiconductor
switches to turn on or off at zero voltage or zero current, respectively, so there is very little
switching loss. Since loss tends to scale with switching frequency in hard switched converters, it
is advantageous to use a resonant topology if the switching frequency is beyond some threshold,
depending on the power level of the converter (less than 100kHz at 500W and lower as the
output power is increased). Above that threshold, relatively high efficiency is achieved
compared to a hard switched converter. Moreover, a higher switching frequency makes it
possible to use smaller energy storage components. This results in an increased power density
and reduction in the amount of energy stored in the system, so less energy is dissipated under
29
fault conditions. From these considerations, a resonant converter seems to be the best candidate
to satisfy the design objectives. If, in the future, the ripple current specification can be relaxed
and a lower switching frequency with comparable filtering is acceptable, a hard switched
converter may also be viable.
The most basic resonant converter topologies (2 resonant components) are the series and parallel
topologies, which have a resonant tank consisting of a series inductor with either a series or
parallel capacitor. Since a transformer is required for galvanic isolation, it is advantageous to
choose a topology which includes a series dc-blocking capacitor to prevent transformer
saturation, so the parallel resonant converter will not be considered. The simplest options are
therefore the series resonant converter (SRC) and series-parallel resonant converter (SPRC),
shown in Figures 2.1 and 2.2, respectively. Some characteristics of these topologies are
contrasted in [16] and summarized in relation to this application in Table 3.1. From their general
characteristics, however, neither topology is clearly favourable for this application. To select the
best topology, a more in-depth comparison is required.
Figure 3.1: Series resonant converter with LC resonant tank.
Figure 3.2: Series-parallel resonant converter with LCC resonant tank.
30
Note that because the load is capacitive, an output inductor is required for each case to filter the
current, reducing electromagnetic interference and unwanted losses in the electrolyte due to high
frequency current harmonics. An output filter capacitor is only required for the series case since
the series resonant tank acts as a current source.
Point of comparison Series (SRC) topology Series-parallel (SPRC) topology
Component count Requires no discrete series resonant inductor, because the inductance can be designed into the transformer. Also, has no parallel resonant capacitor, but an output filter capacitor is required.
Requires a series resonant inductor and parallel resonant capacitor, but no output filter capacitor.
Transformer losses Transformer core loss is higher due to the square output voltage waveform, but transformer winding losses are lower due to the sinusoidal current profile.
Higher transformer winding loss due to the square output current waveform, but lower transformer core loss due to the sinusoidal voltage profile.
Current stress on the output rectifier switches
Higher peak current stress on the rectifier switches
Lower peak current stress on the rectifier switches
Rectifier options Difficulties in implementing synchronous rectification due to the square voltage waveform across the rectifier. A Schottky diode rectifier is used instead, which has significant power loss at high current due to the voltage drop across the diodes. A current doubler configuration is also not possible due to the filter capacitor.
Easier to implement synchronous rectification due to the sinusoidal voltage profile across the rectifier. A current doubler is also possible. These points are discussed further in section 3.5.
Table 3.1: Comparison between SRC and SPRC topologies.
3.2. Steady state converter analysis
A resonant converter is operated as follows. The switches are gated with variable frequency and
phase shift, as in Figure 3.3, to produce a pulsed voltage Vs. The frequency of this signal is close
to the resonant frequency of the resonant tank, and it excites the resonant tank with a sinusoidal
current. The sinusoidal waveform is rectified and filtered to produce a dc output.
31
Operation of a resonant converter above the resonant frequency, as shown in Figure 3.4, is ideal
since in this range, the resonant inductor current lags the input voltage forcing the body diodes of
the transistors to conduct before the transistors turn on. The transistors then turn on with zero
voltage across them, so turn on loss is eliminated. Turn off losses can be prevented by placing
snubber capacitors in parallel with each switch. The snubber capacitors, Cleg, are sized in such a
way that most of the current flows through the capacitor instead of the switch on turn off until
the voltage across the switch increases enough so that the antiparallel diode becomes forward
biased. The expression for Cleg is given in equation 3.1.
g
sLs
legV
TitC
2
)2/(δ= (3.1)
In this expression, iLs(Ts/2) is the resonant inductor current at half a switching period, Vg is the
input voltage and tδ is the length of the commutation interval, chosen longer than the MOSFET
turn-off time but much shorter than the conduction time of the MOSFETs and antiparallel diodes.
The energy stored in the capacitor is transferred to the tank inductor; however, the intrinsic drain-
to-source capacitance of each MOSFET is usually large enough that additional capacitors are not
necessary.
32
Figure 3.3: Gating of input switches Q1, Q2, Q3, and Q4, and the resonant tank input voltage Vs.
Figure 3.4: Sample input voltage and resonant current waveforms for a converter above resonance (zero
voltage switching).
Exact analysis of a resonant converter is complicated due to the number of different states in
which the converter operates over one switching cycle (the series-parallel topology can operate
in 9 different states, depending on operating conditions) and therefore not directly useful for
design purposes. The interested reader is referred to [17]-[18] for an exact state plane analysis of
these converters. Alternatively, if the converter operates close to the resonant frequency, a
sinusoidal approximation can be applied to the resonant waveforms, as in [19]-[20].
The input voltage seen by the resonant tank, Vs, is approximated by its fundamental component,
Vs1, which can be calculated by applying a Fourier series analysis.
33
=
s
shiftg
sT
tVV π
πcos
41 (3.2)
Similarly, the output of the resonant tank can be approximated by an effective load resistance Re
= 8R/π2. By ac analysis of the resultant circuit, the conversion ratio for the series and series-
parallel converters is derived. The expressions for these conversion ratios are as follows:
22 1
1
cos
−+
==
FF
Q
T
t
V
VM
s
shift
g
outSRC
π
(3.3)
( ) ( )
2
222
2
/1
111
cos
+−+−
+
==
pss
p
s
shift
g
out
SPRC
CCFFQF
C
C
T
t
V
VM
π
(3.4)
where Q = Z0/Re is the quality factor of the converter, Z0 is the resonant tank impedance, F = fs/f0
is the normalized switching frequency of operation, and f0 is the resonant frequency. The
resonant tank parameters are summarized in Table 3.2.
Series (LC) topology Series-parallel (LCC) topology
s
s
C
LZ =0 ,
ssCLf
π2
10 =
T
s
C
LZ =0 ,
TsCLf
π2
10 = ,
ps
ps
TCC
CCC
+=
Table 3.2: Resonant tank parameters for the SRC and SPRC topologies.
The voltage conversion ratio as a function of frequency for varying values of Q is shown in
Figure 3.5. For the SPRC, the ratio Cp/Cs is fixed at 1, which is a reasonable compromise
between the advantages of the series resonant converter (good part load efficiency) and the
parallel resonant converter (good regulation at no load) [20].
34
Figure 3.5: Conversion ratio as a function of normalised switching frequency and Q factor for the (a) SRC
and (b) SPRC.
3.3. Series Resonant Converter Design
The series resonant converter of Figure 2.1 will be designed for:
Vg = 400V
Vout = 5V
Iout = 100A
The 400V input voltage comes from a dc bus which is powered from 230V line-to-line ac mains.
The converter will be designed for Vout = 5.7V to account for the voltage drop across the output
rectifier diodes. Since synchronous rectification is not a viable option for the SRC, both
converters will be designed with a Schottky diode rectifier for the initial comparison.
3.3.1. Output Filter
The output filter consists of a capacitor Cf and inductor Lf. The specifications for the filter are as
follows.
35
1. Less than 15% capacitor ripple voltage.
The capacitor ripple voltage will be show up as a second harmonic of the switching frequency on
the primary side of the transformer. To prevent this harmonic from significantly distorting the
resonant tank waveforms, this ripple must be limited. A 15% ripple does not have a significant
impact in simulations but this specification can be tuned for further optimization.
Assuming an ideal rectified sinusoidal current is produced at the output of the rectifier, this
current will have an average value of Iout with peak (π/2)Iout. Then the capacitor charge can be
calculated as follows:
105.0
2sin
11
2sincos
2
1
12
sin2
11
2
2sin
2
2sin
1
1
s
out
s
out
Ts
Ts s
out
f
I
f
I
dttT
IQ
=
+
−
=
−
=
−−
−
∫
−
−
πππ
πππππ
ππ
(3.5)
Therefore, the peak-to-peak capacitor voltage can be calculated as follows:
fs
outpkpkc
Cf
IV
105.0, =− (3.6)
Then the capacitor can be sized as follows:
( ) outs
outf
Vfripple
IC
min,%max
105.0> (3.7)
2. Less than 1% ripple current to the load.
36
It is possible that the ripple specification could be made higher subject to EMI regulations and
the electrochemical cell model. For the present case, 1% is selected as a safe figure to use in the
design procedure.
Almost all of the ripple current at the rectified frequency (2x the switching frequency) should be
absorbed by the capacitor, so the impedance of Lf at this frequency should be at least 100 times
that of Cf.
( ) fs
f
ffs
ffsCf
LC
L 22
24
100100
πωω >⇒>
From the above equations, we obtain Cf > 140µF. Choose Cf = 200µF. Then Lf >300nH.
A high frequency polypropylene capacitor is required for the output filter, but polypropylene
capacitors are generally constructed for high voltage, low current applications. Paralleling
several capacitors is possible, but should be avoided due to parasitic inductances between
capacitors. For 100A output current, the rms capacitor current is 48.4Arms. One example of a
high current, large capacity polypropylene capacitor is the UNL5W100K-F. It is available in
sizes up to 100µF with 13.2Arms current rating at 75°C or 31.8Arms at 25°C. One could parallel
two of these to achieve 200µF.
3.3.2. Transformer Design
The gain of the SRC converter is always less than 1. If the minimum switching frequency is
specified to be 5% above resonant frequency, then the maximum achievable gain for a
reasonably quality factor Q = 4 is 0.9315. By adding an extra 20% margin to account for losses,
the maximum required output voltage at resonant frequency would be 7.3V. This voltage is
37
achieved by selection of the transformer turns ratio. For an input voltage of 400V, a turns ratio
N=55 will give the desired output voltage.
A resonant frequency of f0 = 100kHz is selected. Next, the Q factor must be chosen. For this
high frequency, high power type of converter, the magnetizing inductance of the transformer
cannot necessarily be neglected in the design. To obtain an estimate on the magnetizing
inductance Lm, the transformer design procedure in [19], detailed below, is used. Parameters are
defined in Table 3.1.
1. Determine core size
The magnetic size of the core is given by the inequality below.
ββ
βρλ/)2(
/2221
4 +≥totu
fetot
gfePK
KIK (3.8)
The maximum acceptable power loss is chosen to be 0.5% of the total output power, in this case,
Ptot = 2W. The maximum applied primary volt-seconds λ1 is found by referring the rectifier
voltage to the primary side and integrating over half a switching period at the minimum
switching frequency, 100kHz. The total rms current Itot is calculated by finding the equivalent
rms current rectified to produce the rated dc output current.
222
2)(
,
)2/(1
0
1
⋅=
=== ∫∫
N
II
f
NVdtNVdttv
outSRCtot
s
dc
f
dc
cycleofportionpositive
SRC
s
π
λ
(3.9)
38
Symbol Definition Units ρ Effective wire resistivity Ω cm Itot Total rms winding currents, referred to the
primary A
N = n1/n2 Turns ratio λ1 Applied primary volt-seconds V s Ptot Total power dissipation W PCu Power dissipated in copper windings W PFe Power dissipated in iron core W Ku Winding fill factor β Core loss exponent Kfe Core loss coefficient W/cm3Tβ Ac Cross sectional core area cm2 WA Core window area cm2 MLT Mean length per turn cm ℓm Magnetic path length cm ∆B Peak ac flux density Tesla
Table 3.3: Transformer parameter definitions.
2. Evaluate peak ac flux density
Using the Kgfe value obtained above, a suitable ferrite core can be chosen. The data from that
core is then used to calculate the peak ac flux density.
2
1
3
221 1)(
2
+
=∆β
βρλ
femcAu
tot
KAW
MLT
K
IB
l (3.10)
3. Evaluate primary turns
From the above, the number of primary turns can be calculated.
cBAn
∆=
21
1
λ
(3.11)
From n1, the number of secondary turns, n2, can be calculated. The number of turns n1 and n2
must be integers for the implementation and are adjusted if they are not integers (e.g., if n2 < 1).
39
With the adjusted primary and secondary turns values, the peak flux density can be recalculated
per equation 3.3 and then total power loss can be calculated as follows to verify that the design
specifications are still satisfied.
mcfe
uA
totFeCutot ABK
KW
InMLTPPP l
βρ)(
)( 221 ∆+=+= (3.12)
Finally, the magnetizing inductance, referred to the primary side, can be obtained:
m
cm
AnL
l
21µ=
(3.13)
For an initial design, a Magnetics, Inc., P-type ferrite EE core will be used. The Magnetics Inc. P
material has the following parameters at 100kHz: Kfe = 44.3W/Tβcm3, β=2.6 and Ku = 0.25. A
copper resistivity of ρ=1.724e-6Ω-cm is assumed. Then, using the procedure outlined above, the
following parameters are obtained.
λ = 0.0014V-sec
Itot = 3.23Arms
Kgfe,min = 0.0195
n1 = 55
n2 = 1
∆B = 0.0573
For an initial design, a Magnetics, Inc., P-type ferrite EE50 core is selected with the following
parameters.
Kgfe = 28.4e-3cmx
Kg = 0.909cm5
40
Ac = 2.26cm2
WA = 1.78cm2
MLT = 10cm
lm = 9.58cm
The core schematic is shown in Figure 3.6. For the EE50 core, the dimensions are A=50mm,
B=21.3mm, C=14.6mm, D=14.6mm, E=34.2mm, F=12.75mm, H=7.5mm:
Figure 3.6: EE core schematic.
In calculating the magnetizing inductance, µ = µi = 2500 can be used, since this initial value of
permeability is valid for peak magnetic field values below 200 Gauss.
This gives a magnetizing inductance of Lm = 22.5mH.
3.3.3. Open Loop Transient Studies: Design of Q
The steady state converter gain as a function of switching frequency for varying Q values is
shown in Figure 3.5. For steady state operation, the Q factor can be designed for a desired
selectivity or operating frequency range. However, this steady state analysis does not provide
41
any guidelines for design of a pulsed resonant converter. In pulsing this converter with the
fastest possible rise time, different resonant modes can be excited compared to steady state
operation. These must be considered before converter parameters are chosen.
If the output filter capacitor is assumed to be large enough to hold the output voltage constant
and the transient response of the output filter is neglected, the equivalent circuit structure of
Figure 3.7 is obtained.
Figure 3.7: Equivalent circuit, neglecting the transient response of the output filter.
The input voltage-to-input current transfer function of this structure is:
( ) eqmmseqssms
eqms
in RsLLLRCsCLLs
RLCs
sZsG
++++==
23
2
)(
1)( (3.14)
This transfer function has one real pole and a pair of complex conjugate poles. These poles
plotted for different values of Q are shown in Figure 3.7. The resonant frequency is held
constant at f0 = 100kHz, the equivalent resistance constant at Req = (8/π2)N2Vout/Iout, and the
magnetizing inductance is Lm = 22.5mH. The resonant tank components can then be calculated
as follows:
Z0 = Q Req
Cs = 1 / (2 π f0 Z0)
Ls = Z0 / (2 π f0)
42
For increasing Q, the frequency of the complex poles approaches 1/(LsCs)0.5, the series resonant
frequency. For small Q (~0.5), the complex poles move onto the real axis.
Figure 3.8: Effect of Q on the SRC equivalent circuit transfer function poles.
The open loop step response of the SRC has been simulated using the PowerSIM simulation
package at Q = 0.1 and Q = 4 with the following parameters to illustrate the effect of Q on the
converter transient response: fs = 110kHz, f0 = 100kHz, N = 55, Lm = 22.5mH, Cf = 200µF, Lf =
300nH, Cdl = 250mF, Rinterfacial = 15mΩ, Relectrolyte = 20mΩ. Simulation results are shown in
Figure 3.9 and Figure 3.10.
43
Figure 3.9: SRC open loop transient response for Q = 4.
Figure 3.10: SRC open loop transient response for Q = 0.1.
44
For the Q = 4 case, it can be seen that the output voltage and current experience some overshoot
and ringing. However, the resonant current remains approximately sinusoidal throughout the
transient.
For the Q = 0.1 case, there is a much larger overshoot in the resonant current waveform at the
beginning of the transient, after which there is a dead time before the resonant current evolves
into a sinusoid. This dead time occurs because the large current spike in the beginning charges
the output filter capacitor to a voltage greater than the referred primary voltage, forcing the
rectifier diodes to be reverse biased. It then takes some time for the capacitor voltage to decay,
depending on the size of the output filter inductor. This occurs only for small Q because the tank
impedance is smaller and therefore a larger current can flow during the initial transient. Zero
voltage switching occurs over this discontinuous transient because there still exists a small
magnetizing current that lags the input voltage. However, during this discontinuous transient, a
converter model based on sinusoidal waveforms no longer applies so a controller designed for
continuous operation would not necessarily work. Moreover, because these discontinuities are
caused by overcharging of the output filter, essentially turning off the rectifier for a short time,
control action over the resonant waveforms would not be seen at the output.
The discontinuous transient mode can be avoided either by sizing the filter inductor and filter
capacitor such that a relatively small amount of current flows into the filter capacitor during a
transient or by increasing the resonant tank impedance to limit the transient current (putting a
lower limit on Q). In changing these parameters, however, some practical limitations exist.
There is an upper limit on the filter capacitor value due to the availability of polypropylene
capacitors, so the filter inductor has a lower limit. This means that a lower limit must be placed
45
on the resonant tank impedance. However, polypropylene capacitors smaller than 1nF are not
readily available on the market, so there is also an upper limit on the resonant tank impedance.
Moreover, if the impedance is chosen too large, a large voltage will show up across the capacitor.
Polypropylene capacitors rated for larger than 2kV are not readily available since dielectric
breakdown becomes an issue at very large voltages and capacitance tends to decrease at higher
voltages. Ceramic capacitors in the nanofarad range are not cost-effective and readily available
for this application due to the relatively frequency and voltage.
The resonant tank impedance Z0 should therefore be designed for a minimum Q value at the
worst case, minimum load case.
3.3.4. Design Summary
To design for continuous transient mode, the procedure is as follows:
1. Size the filter capacitor for a small capacitor voltage ripple to avoid distortion of the resonant
waveforms.
2. Size the filter inductor for a small output current ripple, subject to EMI regulations and to
avoid a negative impact on the load.
3. Select the resonant tank impedance for continuous transient operation with minimum loading
(the largest effective load resistance).
Designing for Q = 1 at minimum load gives Q = 1.6 at maximum load. This design is
summarized in Table 3.4. Open loop simulation results at maximum load are shown in Figure
3.11. Zero voltage switching is guaranteed throughout the transient due to this component
selection. An oscillation exists at the resonant frequency of the output filter, approximately
46
20kHz, but since this issue can be resolved through control action, this design appears to be a
good compromise.
Component Value
N 55 Q (full load) 1.6 Lm 22.5mH Ls 310µH Cs 8.1nF Cf 200µF Lf 300nH Table 3.4: SRC parameter and component values.
Figure 3.11: SRC open loop transient response for Q = 1.6.
3.3.5. Small signal model
To design a control loop for this converter, an accurate small signal model is required. A
common method used for modeling of switched mode power supplies is state-space averaging,
47
where waveforms of interest are assumed to be constant over one switching period (a small
ripple condition applies). This method does not apply for resonant converters, however, since
the resonant waveforms do not satisfy this small ripple approximation. Since the resonant
waveforms are approximately sinusoidal near resonance, a similar approximation can be applied
wherein each resonant waveform is approximated by its fundamental frequency component.
This method is called “generalized averaging” and was proposed by Sanders et al [28], who
applied it to the example of a series resonant converter with a filter capacitor. In this way, a large
signal, nonlinear model is derived, which can be linearized about an operating point to obtain a
transfer function. A comparable small signal modeling method based on state space averaging
was proposed by Witulski et al [29]. It yields the same results but is not as intuitive as the
Sanders model and will not be considered here.
3.3.5.1. State Model
The circuit under study is shown in Figure 3.5. In this equivalent circuit, the input voltage and 4
switches have been replaced by an equivalent square wave with amplitude Vs. Since only the
fundamental component of Vs affects the following model, any phase shift control can be
accounted for by defining Vs as follows:
=
2cos shift
gs VVϕ
(3.15)
A model for the series resonant converter (SRC) will be derived using generalized averaging. It
will be assumed that the load can be approximated by an equivalent resistance. Furthermore,
since the magnetizing current is very small compared to the resonant current (in this case 2
orders of magnitude smaller at 0.05A versus 5A resonant current), Lm can be neglected.
48
Figure 3.12: Equivalent converter circuit for model.
The differential equations for this system are as follows, where each quantity is implicitly
assumed to be a function of time:
RivL
idt
d
iiabsC
vdt
d
iC
vdt
d
tVivvL
idt
d
LfCf
f
Lf
LfLs
f
Cf
Ls
s
Cs
ssLsCfCs
s
Ls
−=
−=
=
+−−=
1
)(1
1
))sgn(sin()sgn(1
ω
(3.16)
By calculating the k-th coefficient of the Fourier series for each term, denoted <x>k(t), one can
use the following property for Fourier coefficients to arrive at a generalized average model:
)()()(
)(1
)(0
)(
txjktxdt
dtx
dt
d
dsesTtxT
tx
ks
kk
T
sTtjk
k
s
ω
ω
−=
+−= ∫ +−−
(3.17)
This gives the following complex-valued model:
49
RivL
idt
d
iiabsC
vdt
d
iC
vjvdt
d
tVivvL
ijidt
d
LfCf
f
Lf
LfLs
f
Cf
Ls
s
CssCs
ssLsCfCs
s
LssLs
000
000
111
11111
1
)(1
1
))sgn(sin()sgn(1
−=
−=
+−=
+−−+−=
ω
ωω
(3.18)
Since iLs and vCs are approximately sinusoidal over one switching period, each is represented by
its fundamental Fourier coefficient, whereas vCf and iLf are approximated by their dc components.
Next, the sgn and abs terms can be evaluated separately:
11
101
1
4)(
exp2
)sgn(
2))sgn(sin(
LsLs
LsCfLsCf
s
iiabs
ijviv
jt
π
π
πω
=
∠=
−=
Then the nonlinear system is as follows:
RivL
idt
d
iiC
vdt
d
iC
vjvdt
d
VjijvvL
ijidt
d
LfCf
f
Lf
LfLs
f
Cf
Ls
s
CssCs
sLsCfCs
s
LssLs
000
010
111
10111
1
41
1
2exp
21
−=
−=
+−=
−∠−−+−=
π
ω
ππω
(3.19)
Note that because the first 2 variables are complex Fourier coefficients, this system is actually 6th
order. In terms of the 6 real state variables, the model is as follows:
50
RivL
idt
d
iiiC
vdt
d
iC
vvdt
d
iC
vvdt
d
L
V
ii
i
L
v
L
vii
dt
d
ii
i
L
v
L
vii
dt
d
LfCf
f
Lf
LfLsLs
f
Cf
Ls
s
CssCs
Ls
s
CssCs
s
s
LsLs
Ls
s
Cf
s
Cs
LssLs
LsLs
Ls
s
Cf
s
Cs
LssLs
000
0
2Im
1
2Re
10
Im
1
Re
1
Im
1
Re
1
Im
1
Re
1
2Im
1
2Re
1
Im
10
Im
1Re
1
Im
1
2Im
1
2Re
1
Re
10
Re
1Im
1
Re
1
1
41
1
1
22
2
−=
−+=
+−=
+=
−+
−−−=
+−−=
π
ω
ω
ππω
πω
(3.20)
This model can then be simulated. SIMULINK is used here because it can model nonlinear and
linear systems without added complexity resulting in long run times. The step response of this
model for an input voltage step from 0 to 400V is shown in Figure 3.13. The model is simulated
for Q = 4 and a purely resistive load. This result is in good agreement with the result of the
circuit simulation, also shown in the figure, except for a small dc offset which is due to parasitics
embedded within the simulation software and neglected in the mathematical model.
51
Figure 3.13: Response of output voltage to an input voltage step, for the generalized average model versus
circuit simulation.
3.3.5.2. Steady State Model
To obtain a steady state model, the time derivatives in the above model are set to zero and the
complex system is solved. These results agree with those predicted by frequency domain
analysis for this converter, using a sinusoidal approximation for the resonant waveforms.
ss
Ls
ss
Cf
ss
o
ss
Ls
ss
ss
Cs
sssss
sssss
Ls
iR
vv
iCj
v
RCjCL
VC
i
100
11
2
21
4
1
81
2
π
ω
πωω
πω
==
=
+−=
(3.21)
52
2
2
2
0 81
8
πωω
πω
RCjCL
VR
C
v
sssss
sssss
o
+−=⇒ (3.22)
3.3.5.3. Linearization
The above nonlinear system is of the form x′ = f(x,u) where x is the states and u is the inputs.
( ) ( ) ( ) ( )[ ][ ]Tss
T
LfCfCsCsLsLs
vu
ivvviix
ω=
=001111
ImReImRe (3.23)
This system can be linearized about an operating point and expressed in the form x′ = Ax + Bu,
where A and B are the Jacobians of the system with respect to x and u, given by:
),( 00
),(
uxj
iij
x
uxfA
∂
∂=
),( 00
),(
uxj
iij
u
uxfB
∂
∂= (3.24)
These matrices are found to be the following:
53
−
−
−
−−−⋅
+−
−−⋅
+−
=
ff
fof
Ls
of
Ls
s
s
s
s
o
Ls
sso
Ls
so
LsLs
s
s
o
Ls
sso
LsLs
s
s
o
Ls
s
L
R
L
CVC
iR
VC
iR
C
C
V
i
L
R
LV
i
L
R
V
ii
L
R
V
i
L
R
LV
ii
L
R
V
i
L
R
A
10000
1000
1616
0001
0
00001
0181
011281128
018
0111281128
Im
12
Re
12
Im
122
2Re
14
3
2
Im
1
Re
14
3
Re
122
Im
1
Re
14
3
2
2Im
14
3
ππ
ω
ω
πππω
ππω
π
−
−−
=
00
00
0
0
120
Re
1
Im
1
Re
1
Im
1
Cs
Cs
s
Ls
Ls
v
v
Li
i
B
π (3.25)
3.3.5.4. Converter transfer function
For this linearized system, the control-to-output current transfer functions for the converter can
be obtained as follows:
[ ]
[ ]
−=
−=
−
−
1
0)(100000
)(ˆ
)(ˆ
0
1)(100000
)(ˆ)(ˆ
1
1
BAsIsv
si
BAsIs
si
s
o
s
o
ω (3.26)
The Bode plot for the frequency-to-output current transfer function is shown in Figure 3.14. The
poles of this transfer function, as a function of normalised switching frequency F = fs/f0 are
plotted in Figure 3.15. There are three pairs of complex conjugate poles. As the frequency
54
decreases toward resonant frequency, one pair of poles moves onto the real axis, one pair move
to a higher frequency, and one pair move to a lower frequency. The pair of poles that move apart
with increasing switching frequency correspond to the output filter resonance of about 20kHz.
Figure 3.14: SRC frequency-to-output current transfer function at full and half rated loading conditions.
Figure 3.15: Poles of the frequency-to-output current transfer function.
55
3.4. Series-Parallel Resonant Converter Design
The series-parallel resonant converter of Figure 2.2 will be designed for:
Vinput = 400V
Vout = 5V
Iout = 100A
Again, the converter will be rated for Vout = 5.7V to account for a diode rectifier so that a head-
to-head comparison can be made with the SRC.
3.4.1. Output filter
For the SPRC, the output filter consists only of a filter inductor Lf. Its value will depend on the
output ripple current specification. In this analysis, it is assumed that an ideal rectified
sinusoidal voltage is produced at the output of the rectifier and that the inductor absorbs only the
ac component of that waveform. Then, the following equation is derived from a volt-seconds
balance on the inductor (similar to the capacitor charge analysis done for the SRC case):
fs
outpkpkout
Lf
VI
105.0, =− (3.27)
Then the inductor can be sized as follows:
( ) outs
outf
Ifripple
VL
min,%max
105.0> (3.28)
For a specification of less than 1% peak ripple current, Lf > 2.6µH is obtained. Lf = 5µH will be
used.
56
3.4.2. Transformer Design
As for the SRC, a resonant frequency of f0 = 100kHz is selected. Next, a preliminary
transformer design must be performed and a Q factor selected. One significant difference
between the SRC and SPRC converters is that for the SPRC, the maximum gain depends on the
Q factor of the converter, whereas for the SRC case the maximum gain is always 1. Since the Q
factor selection depends on the transformer design (through the choice of magnetizing
inductance), there is a two-way coupling between the Q factor selection and transformer design.
The proposed design strategy is as follows:
1. Let Lm = 22.5mH for a transformer turns ratio of 55:1, as used for the SRC.
2. Design Q for desired transient response and steady state operation.
3. Check whether the turns ratio of the transformer needs to be modified and redo the above
steps as needed.
The transformer design procedure is the same as that for the SRC case; however, the current seen
on the primary side is a square wave and the voltage is sinusoidal for the SPRC case. The
resulting volt-seconds is the same but the total rms current is slightly smaller, as shown below.
2
2)2sin(
2)(
,
)2/(1
0
1
⋅=
=== ∫∫
N
II
f
NVdtfNVdttv
outSPRCtot
s
dc
f
sdc
cycleofportionpositive
SPRC
s
ππ
λ
(3.29)
3.4.3. Open Loop Transient Studies: Design of Q
For an initial investigation into the poles of this system and effect of Lm, the simplified model of
57
Figure 4.1 can be used, which neglects the effect of the rectifier and output filter inductor.
Figure 3.16: Equivalent circuit, neglecting the transient response of the output filter.
The transfer function of this structure is:
( ) eqmmeqpmeqsseqssmseqpsms
eqms
RsLLRCLRCLRCsCLLsRCCLLs
RLCssG
++++++= 234
2
)( (3.30)
This transfer function has 4 poles. These poles plotted for different values of Q are shown in
Figure 4.2. The resonant frequency is held constant at f0 = 100kHz, the equivalent resistance
constant at Req = (8/π2)N2Vout/Iout, and the magnetizing inductance is Lm = 22.5mH. For Cp = Cs,
the resonant tank components can then be calculated as follows:
Z0 = Q Req
CT = 1 / (2 π f0 Z0)
Cs = Cp = 2 CT
Ls = Z0 / (2 π f0)
For very low Q (~0.1), there are two complex conjugate pairs of poles. For increasing Q, the
frequency of one pair decreases, and the other pair of poles moves onto the real axis where one
pole moves negatively along the real axis (greater damping) and the other remains close to the
imaginary axis. It can be seen that changing Q has the opposite effect as for the series resonant
structure.
58
Figure 3.17: Effect of Q on the poles of the SPRC equivalent circuit transfer function.
The open loop step response of the SRC with an electrochemical load model has been simulated
at Q = 0.1 and Q = 4 with the following parameters: fs = 110kHz, f0 = 100kHz, Lm = 22.5mH, Lf
= 5µH, Cdl = 250mF, Rinterfacial = 15mΩ, Relectrolyte = 20mΩ. The simulation results are shown in
Figure 3.18 and Figure 3.19.
For the SPRC, the discontinuous transient case occurs for large Q. This is due to the definition
of Q for the SPRC (where low Q gives greater selectivity). However, moving to an extremely
small Q (as in Figure 4.4) for a constant load, resonant tank frequency and switching frequency
causes the steady state resonant current to be unacceptably large (~700A). Since the gain curve
changes significantly for different Q, the output voltage for this case is also much larger. To
operate at an output voltage of 5V, either the transformer turns ratio or switching frequency
needs to be increased. Changing the transformer turns ratio would not change the resonant
current significantly. Therefore, Q should be designed for the worst case maximum loading
59
(smallest effective load resistance) to avoid the discontinuous transient mode, but should be kept
as large as possible to maintain low current ratings on the resonant tank components.
Figure 3.20 shows that the converter operates in a continuous transient mode if Q is moderate,
e.g., Q = 1.
Figure 3.18: SPRC open loop transient response for Q = 4.
60
Figure 3.19: SPRC open loop transient response for Q = 0.1.
Figure 3.20: SPRC open loop transient response for Q = 1.
61
3.4.4. Design Summary
To design for continuous transient mode, the procedure is as follows:
1. Size the filter inductor for small output current ripple.
2. Select the resonant tank impedance for continuous transient operation with worst case
maximum load (smallest effective load resistance).
3. Redesign the transformer as needed to give the necessary voltage gain for the maximum load
case.
Q = 1 at maximum load (as specified in the previous section) corresponds to Q = 0.625 for
minimum load. The conversion ratio for each case is plotted in Figure 3.21.
Figure 3.21: Conversion ratio curves for minimum and maximum Q, at Cp/Cs = 1.
The transformer turns ratio must be chosen to provide the necessary voltage at Q = 1. If the
minimum frequency of operation is selected to be 5% above the resonant frequency, as for the
SRC case, then a gain of 1.64 would produce 5.7V, so Vg/N = 5.7/1.64 = 3.47. With a 20%
62
safety margin to account for loss, a turns ratio of 96:1 is chosen. Redesigning for N = 96 gives
Ls = 594µH and Cs = Cp = 8.5nF. To account for the availability of polypropylene capacitors on
the market, Cs = Cp = 10nF will be used, giving Ls = 500µH.
This design is summarized in Table 3.5. Open loop simulation results are shown in Figure 3.22.
Component Value
N 96 Q (full load) 1 Ls 500µH Cs = Cp 10nF Lf 5µH Table 3.5: SPRC parameter and component values.
Figure 3.22: SPRC open loop transient response for Q = 1 at N = 96.
63
3.4.5. Small signal model
The generalized averaging method can be applied to this converter as it was for the SRC.
3.4.5.1. State model
The circuit under study is shown in Figure 4.7. As for the SRC case, the nonlinear load will be
represented by an equivalent resistance and the magnetizing current will be neglected since it is
much smaller than the resonant tank current (2 orders of magnitude).
Figure 3.23: Equivalent converter circuit for model.
The differential equations for this system are as follows:
RivabsL
idt
d
viiC
vdt
d
iC
vdt
d
tVvvL
idt
d
oCp
f
o
CpoLs
p
Cp
Ls
s
Cs
ssCpCs
s
Ls
−=
−=
=
+−−=
)(1
)sgn(1
1
))sgn(sin(1
ω
(3.31)
Approximating each quantity by its fundamental Fourier component or dc value gives the
following complex model:
64
RivabsL
idt
d
viiC
vjvdt
d
iC
vjvdt
d
tVvvL
ijidt
d
oCp
f
o
CpoLs
p
CpsCp
Ls
s
CssCs
ssCpCs
s
LssLs
000
1111
111
11111
)(1
)sgn(1
1
))sgn(sin(1
−=
−+−=
+−=
+−−+−=
ω
ω
ωω
(3.32)
Next, the sgn and abs terms can be evaluated separately:
10
101
1
4)(
exp2
)sgn(
2))sgn(sin(
CpCp
CpoCpo
s
vvabs
vjivi
jt
π
π
πω
=
∠=
−=
(3.33)
Then the nonlinear system is as follows:
−=
∠−+−=
+−=
−−−−=
RivL
idt
d
vjC
i
C
ivjv
dt
d
iC
vjvdt
d
L
Vj
L
v
L
viji
dt
d
oCp
f
o
Cp
p
o
p
Ls
CpsCp
Ls
s
CssCs
s
s
s
Cp
s
Cs
LssLs
010
1
01
11
111
1111
41
exp2
1
2
π
πω
ω
πω
(3.34)
In terms of the 7 real state variables, the model is as follows:
65
−+=
+
−+−=
+
−+=
+−=
+=
−−−−=
−−=
RivvL
idt
d
vv
v
C
i
C
ivv
dt
d
vv
v
C
i
C
ivv
dt
d
iC
vvdt
d
iC
vvdt
d
L
V
L
v
L
vii
dt
d
L
v
L
vii
dt
d
oCpCp
f
o
CpCp
Cp
p
o
p
Ls
CpsCp
CpCp
Cp
p
o
p
Ls
CpsCp
Ls
s
CssCs
Ls
s
CssCs
s
s
s
Cp
s
Cs
LssLs
s
Cp
s
Cs
LssLs
0
2Im
1
2Re
10
2Im
1
2Re
1
Im
10
Im
1Re
1
Im
1
2Im
1
2Re
1
Re
10
Re
1Im
1
Re
1
Im
1
Re
1
Im
1
Re
1
Im
1
Re
1
Im
1
Im
1Re
1
Im
1
Re
1
Re
1Im
1
Re
1
41
2
2
1
1
2
π
πω
πω
ω
ω
πω
ω
(3.35)
The step response of this model is shown in Figure 4.8 for Q = 1 and a purely resistive load. At
this Q value, the SPRC step response is quite similar to the SRC. The Simulink and circuit
simulations are in good agreement. Again, there is a dc offset due to parasitics embedded in the
simulation software.
66
Figure 3.24: Response of output voltage to an input voltage step, for the generalized average model versus
circuit simulation.
3.4.5.2. Steady State Model
To obtain a steady state model, the time derivatives in the above model can be set to zero and the
complex system can be solved. This solution agrees with that derived from ac circuit analysis.
( )
ss
Cp
ss
o
ss
Cpps
ss
Ls
ss
Cp
s
p
ss
ss
Cs
sss
p
sss
sss
Cp
vR
i
vCjR
i
vC
C
RCjv
RCj
C
CCL
Vj
v
10
121
121
2
21
4
8
8
811
2
π
ωπ
πω
πωω
π
=
+=
+−=
−−+
−=
(3.36)
67
( )
−−+
=⇒
RCj
C
CCL
VRi
sss
p
sss
sss
o
2
2
2
08
11
8
πωω
π (3.37)
3.4.5.3. Linearization
As for the SRC case, the system can be linearized and expressed in the form x′ = Ax + Bu where:
( ) ( ) ( ) ( ) ( ) ( )[ ][ ]Tss
T
oCpCpCsCsLsLs
vu
ivvvviix
ω=
=0111111
ImReImReImRe (3.38)
−
−−+−
−+−
−
−−−
−−
=
fo
Cp
fo
Cp
f
o
Cp
po
Cp
po
CpCp
p
s
p
o
Cp
po
CpCp
p
s
o
Cp
pp
s
s
s
s
ss
s
ss
s
L
R
I
v
RLI
v
RL
I
v
RCI
v
CRI
vv
CRC
I
v
RCI
vv
CRI
v
CRC
C
C
LL
LL
A
Im
12
Re
12
Im
122
2Re
1342
Im
1
Re
134
Re
122
Im
1
Re
1342
2Im
134
16160000
181128112800
10
1811281128000
1
00001
0
000001
01
01
00
001
01
0
ππ
πππω
ππω
π
ω
ω
ω
ω
−
−
−−
=
00
0
0
0
0
120
Re
1
Im
1
Re
1
Im
1
Re
1
Im
1
Cp
Cp
Cs
Cs
s
Ls
Ls
v
v
v
v
Li
i
B
π
(3.39)
68
3.4.5.4. Converter transfer function
For this linearized system, the control-to-output transfer functions for the converter can be
obtained as follows:
[ ]
[ ]
−=
−=
−
−
1
0)(1000000
)(ˆ
)(ˆ
0
1)(1000000
)(ˆ)(ˆ
1
1
BAsIsv
si
BAsIs
si
s
o
s
o
ω (3.40)
A Bode plot of the frequency-to-output current transfer function is shown in Figure 3.25.
Figure 3.25: SPRC frequency-to-output current transfer function at full and half rated loading conditions.
69
3.5. Rectifier
As mentioned in Table 3.1, one benefit of the SPRC converter over the SRC is that the topology
lends itself to both synchronous rectification and the current doubler rectifier. This section will
describe these rectifiers in more detail.
3.5.1. Schottky versus synchronous rectification
Schottky diodes are required in high current and low voltage, high frequency diode rectifier
applications in order to eliminate the reverse recovery losses associated with minority carrier
injection in junction type diodes. A Schottky diode rectifier presents a problem, however, due to
the high cost of Schottkys and the large on-state voltage drop across the diodes (~0.7V), which
leads to a significant power loss and requires overdesign in the converter gain to account for the
lost voltage. In a synchronous rectifier, MOSFETs are used instead of the diodes. The on-state
voltage drop is related to the drain-to-source resistance of the MOSFET, Rds,on. This on-state
voltage drop scales with current and tends to be much lower than the voltage drop across a diode.
Moreover, MOSFETs are more cost effective at these current levels than Schottky diodes. The
tradeoff is that the MOSFETs must be controlled precisely to achieve the same behaviour as a
diode rectifier.
Synchronous rectification applied to resonant topologies has been demonstrated in [21] and [22].
Cobos et al [21] provide the following criteria for a resonant converter topology to employ
synchronous rectification:
1. The junction capacitances of the rectifier switches should be included in the resonant tank, and
2. The voltage waveform in the resonant capacitor should be able to turn the synchronous
70
rectifier switches on and off.
These criteria make synchronous rectification well-suited to any parallel resonant topology
because the parallel capacitor forces a sinusoidal voltage profile across the rectifier.
Synchronous rectification is more difficult to implement with the series resonant topology in
which a square wave voltage is forced across the rectifier due to the action of the diodes.
3.5.2. Standard full wave rectifier versus current doubler rectifier
Figure 3.26: SPRC with standard full wave rectifier (top) and current doubler rectifier (bottom).
The standard full wave and current doubler rectifier topologies are shown in Figure 3.26, as
applied to the SPRC. The two topologies are shown with diodes but if a synchronous rectifier is
used, the diodes are replaced with MOSFETs.
The current doubler is described in detail in [23]. It has gained popularity in high frequency and
high output current dc-dc supplies because (i) the secondary transformer winding takes only half
the current compared to other rectifiers and (ii) the transformer design is simpler since no centre
tap is required. This results in a reduced leakage inductance and reduced losses for the
71
transformer. The only drawback of this approach is that an additional filter inductor is required.
Steady state operation of the current doubler is illustrated in Figure 3.27. It is assumed that the
output filter inductors Lf1 and Lf2 are large enough that the current through each is approximately
constant. When a positive voltage is applied across the primary transformer winding (operating
mode 1), switch SR1 is turned on and a current Io/2 conducts through Lf1. A freewheeling
current of I0/2 circulates between Lf2 and the load through switch SR1. Thus, the total current
seen by the load and by SR1 is Io. The total current supplied by the secondary transformer
winding is I0/2 and therefore the current into the primary winding is Iprim = Io/2N. The voltage
drop across Lf1 is vLf1 = vsec – vo and the voltage drop across Lf2 is vLf2 = -vo. When vprim < 0
(operating mode 2), the opposite occurs, with current from the transformer transferring to the
load through Lf2 and SR2 while Lf1 carries the freewheeling current. The result is that to achieve
the same output current, the transformer turns ratio N must be decreased by a factor of 2
Figure 3.27: Current doubler circuit (top) with modes of operation for Vprim > 0 (bottom left) and Vprim < 0
(bottom right) .
72
V_prim / kV
-1
-0.5
0
0.5
1
Is2 / A
-0
40
80
120
Is1 / A
20
60
100
Iprim / A
-1
-0.5
0
0.5
1
Time/mSecs 5uSecs/div
12.15 12.155 12.16 12.165 12.17 12.175 12.18 12.185
Output I / A
95
97
98
Figure 3.28: Primary and secondary waveforms for the SPRC with full wave rectifier.
ILf1 / A
46
50
54
Output I / A
97
99
101
V_prim / kV
-1
-0.5
0
0.5
1
Iprim / A
-1.5
-0.5
0.5
1.5
Time/mSecs 5uSecs/div
12.15 12.155 12.16 12.165 12.17 12.175 12.18 12.185
ILf2 / A
46
48
50
52
54
Figure 3.29: Primary and secondary waveforms for the SPRC with current doubler rectifier.
73
Simulation results of the waveforms for the standard full wave and current doubler rectifiers are
shown in Figure 3.29. The circuits are otherwise identical except that the current doubler case
uses a transformer with half the turns ratio. This produces the same equivalent resistance as seen
from the primary for both cases.
Comparing the benefits (simpler transformer design due to the half the turns ratio required and
no centre tap, half the current flowing in each rectifier switch, and half the current flowing in
each filter inductor) to the drawbacks (one additional filter inductor required), it is clear that the
current doubler is a better option for the SPRC.
Output filter
Assuming an ideal half-wave rectified sinusoidal voltage appears across each switch, this voltage
will have an average value of Vout/2 with a peak voltage of (π/2)Vout. Then, the number of volt-
seconds applied to the inductor over one half cycle is calculated as follows:
552.0
1sin
1
2
11sincos
12
sin
11
2
1sin
2
1sin
1
1
s
out
s
out
Ts
Ts s
out
f
V
f
V
dttT
VsV
=
+−
=
−
=⋅
−−
−
∫
−
−
πππ
ππ
πππ
ππ
(3.41)
This is approximately 5 times the applied volt-seconds which were calculated for a single output
filter inductor, 105.0s
out
f
VsV =⋅ . Thus, for the same current ripple in each inductor as for the
74
centre tap full wave rectifier, the two filter inductors must be approximately 5 times greater than
the original. However, approximately 70% cancellation occurs between the two ripple currents
for operation slightly above resonance. This means the inductors need to be approximately twice
the value of the single output filter inductor, as follows.
( ) outs
outff
Ifripple
VLL
min,21 %max
17.0>= (3.42)
The result is that each inductor carries half the current but must have about twice the inductance
compared to the single output inductor case. Since the physical size of an inductor scales as LI2,
each inductor in a current doubler rectifier will be about half the physical size of a single output
inductor.
The addition of the current doubler also changes the dynamics of the converter. The initial
dynamic model was:
RivabsL
idt
d
viiC
vdt
d
iC
vdt
d
tVvvL
idt
d
oCp
f
o
CpoLs
p
Cp
Ls
s
Cs
ssCpCs
s
Ls
−=
−=
=
+−−=
)(1
)sgn(1
1
))sgn(sin(1
ω
` (3.43)
With a current doubler, the last state variable io is replaced with iLf1, which is equal to iLf2 to first
order. Then the model becomes:
75
−=
−=
=
+−−=
RivabsL
idt
d
viiC
vdt
d
iC
vdt
d
tVvvL
idt
d
LfCp
f
Lf
CpoLs
p
Cp
Ls
s
Cs
ssCpCs
s
Ls
2)(2
11
)sgn(1
1
))sgn(sin(1
ω
(3.44)
Simulation results for these models are shown in Figure 3.30. With two inductors of the same
value as the output inductor for the original full wave rectifier, the converter with current doubler
shows a significant overshoot in the output current. This response can be damped by increasing
the value of those inductors. In each case, the final current approaches the same steady state
value.
Figure 3.30: Step response for the SPRC with current doubler versus standard full wave rectifier.
76
3.6. Choice of Converter Topology
The device ratings for the given SRC and SPRC designs are shown in the table below.
SRC SPRC Device Current Voltage kVA Current Voltage kVA Series Resonant Capacitor Cs 2Arms 303Vrms 0.61 3.8Arms 620Vrms 2.4 Series Resonant Inductor Ls 2Arms 585Vrms 1.2 3.8Arms 1.5kVrms 5.7 Parallel Resonant Capacitor Cp NA NA NA 3.8Arms 620Vrms 2.4 Output Filter Capacitor Cf 40Arms 5V 0.2 NA NA NA Output Filter Inductor Lf 100A 0.11Vrms 0.011 100A 2.8Vrms 0.28 Rectifier Diodes 157A pk 5V pk 100A pk 4.2V pk MOSFETs 2.5A pk 200V pk 5.4A pk 200V pk Transformer EE50 core (see design) EE50 core (see design)
Table 3.6: Comparison between SRC and SPRC device ratings.
It is known that the SPRC has a problem with circulating current due to the parallel capacitor.
The effect of this circulating current on device ratings can be seen in the table above, as the
SPRC requires resonant tank components and input MOSFETs with higher current ratings
compared to the SRC case.
Advantages of the SPRC can mainly be seen in the output stage:
• The peak rectifier diode current is reduced by a factor of √2 for the SPRC due to the square
transformer current profile.
• Because the transformer voltage is sinusoidal in the SPRC case, it is simple to implement a
synchronous rectifier, which is challenging for the SRC case.
• The output filter capacitor is difficult to source for the SRC due to its high current, high
frequency rating. Polypropylene capacitors are widely available for high voltage, low
current applications, but there is a limited selection at low voltage and high current. This
77
capacitor is physically quite large and also very expensive compared to the other circuit
components and to achieve the required capacitance, it may be necessary to parallel multiple
capacitors. This should be avoided if possible due to possible resonances between capacitors
and parasitic inductances, as well as layout issues due to parasitic inductance at high current
and high frequency.
• Because of the output capacitor, the SRC cannot be implemented with a current doubler
rectifier, which is advantageous for this type of high output current application.
In conclusion, the series-parallel resonant converter is a better option for this application because
it has no problematic high frequency, high current capacitor at the output and it can be
implemented with a current doubler synchronous rectifier. The control design, simulations and
experimental results for this converter are described in the next two chapters.
78
Chapter 4 Closed Loop Design
This chapter includes the design details for the control loop of a SPRC. The estimation of the
output voltage and current from quantities sensed on the primary side is described in section 4.1.
Sections 4.2 and 4.3 present the small signal models for the gating signal generator and converter,
respectively. Finally, the design of the current and voltage compensators accompanied by
simulation results are presented in sections 4.4 and 4.5, respectively.
The closed loop design for the SPRC employs a cascade control system consisting of an inner
current control loop and outer voltage control loop as in Figure 4.1. The inner current loop
ensures inherent protection and modularity of the design, as specified in the project objectives.
The output voltage and output current are estimated using quantities sensed on the high voltage
side. Initially, only frequency control will be treated. Phase shift control can be added to the
system later if frequency control alone is insufficient to cover the entire operating range (e.g., if
light loading conditions would require a frequency greater than the maximum rated frequency).
Figure 4.1: Cascade control system with inner current control and outer voltage control loop.
79
Since the output voltage vo is equal to the output current io multiplied by some equivalent load
impedance ZL, this control problem can be expressed as in Figure 4.1, where the voltage is
“estimated” based on the impedance (this estimation occurs through the transfer function
derivation). Since the cell impedance was approximated as a pure resistance in the small signal
model derivation, it will be assumed in the controller design that ZL = Req, the sum of the
interfacial resistance and electrolyte resistance. In fact, the frequency characteristic of the load is
shown in Figure 4.2. At high frequencies, the double layer capacitors act as short circuits so that
ZL approaches the electrolyte resistance, Relec. At approximately 50Hz, the load contributes
nearly -12° phase. Without a more accurate dynamic load model, however, little advantage is
gained by incorporating the full load impedance into the controller design.
Figure 4.2: Equivalent cell circuit model load impedance.
The transfer function of the inner loop is given in equation 4.1. Equation 4.2 gives the overall
closed loop transfer function.
80
icifcif
cifcif
ref
o
HGGG
GGG
i
i
+=
1ˆ
ˆ (4.1)
OFLPFHGGGGRHGGG
GGGGR
v
v
vcvcifcifeqicifcif
cvcifcifeq
ref
o
⋅⋅++=
1ˆ
ˆ (4.2)
Stability of the inner loop ensures stability of the closed loop system as long as the outer loop is
designed properly. The design procedure is as follows. The transfer functions of the converter
and VCO are fixed. Therefore, Gci must first be designed so that GifGfcGciHi has a sufficiently
low crossover frequency (less than 1/10th of the Nyquist frequency, i.e., less than 1/20th of the
switching frequency) and sufficient phase margin. Then, Gvc is designed for sufficiently low
crossover frequency and infinite gain at dc, for tracking of the reference signal.
4.1. Voltage and Current Estimation
For cascade control, load voltage and current sensing is required; however, placing sensors on
the secondary side at the electrochemical cell and feeding that information back to the control
loop presents a challenge for two reasons. First, a high current sensor with good dynamics is
required, which would be costly and take up a significant amount of space on the board. Second,
the high current output requires a large surface area of copper on the PCB around which it would
be difficult to route signal traces. It is preferable to sense these quantities on the primary side.
This can be done as shown in Figure 4.3. The current is sensed using a small ac current sense
transformer on the primary and the voltage is sensed from an auxiliary winding built into the
transformer. Rectifying and filtering both signals then produces scaled estimates of the actual dc
quantities.
81
The resulting iest is related to the actual current output current iout as follows:
oiest iHi ˆˆ =
where Hi is a scaling factor which includes the turns ratio of the main step down transformer
(Np:Ns = 48:1) and the current sense transformer (1:1), and a factor of 2 due to the current
doubler at the output. The primary side current is equal to 1/96th of the output current, so rated
current (100A) corresponds to a 1.04V feedback. This signal will also be amplified by a factor
of 5 in the operational amplifier circuit to bring the control signal to 5.2V to increase the signal-
to-noise ratio. Therefore, Hi = 5/96.
Since the primary side current is a square wave, its rectified version will be equal to some scaled
version of the output current with some spikes due to the commutation time of the switches and
precision rectifier. However, additional filtering is not required since noise rejection is supplied
by the current compensator Gci.
Figure 4.3: SPRC with high side voltage and current sensing.
82
In the case of the voltage estimate, low pass filtering of the rectified signal is required because
the voltage compensator (a PI compensator) does not provide high frequency noise rejection.
Moreover, the voltage sensed on the transformer is not a scaled version of the output voltage due
to the dynamics of the current doubler. The Thèvenin equivalent circuit for the output is shown
in Figure 4.4. From this circuit, the output voltage-to-secondary voltage transfer function, OF,
can be derived (see equation 4.3).
Figure 4.4: Thevenin equivalent circuit of the output filter.
+==
L
f
o Z
Ls
v
vOF
212
ˆ
ˆsec (4.3)
Hv is a scaling factor including the number of turns of the secondary transformer winding Ns = 1
and auxiliary transformer winding Naux = 1 and the gain of a resistor divider (1/2), which is
required at the input to the precision rectifier to prevent saturation of the operational amplifiers.
s
aux
vN
NH
2
1= (4.4)
Then the estimated voltage is related to the output voltage by the following transfer function,
which includes the low pass filter (LPF) described in section 4.5.
+⋅⋅=
L
f
s
aux
o
est
Z
Ls
N
NLPF
v
v
212
2
1ˆ
ˆ (4.5)
83
The design of a high speed precision rectifier is described in [27]. The precision rectifier can be
implemented as in Figure 4.5 where, to operate at 100kHz, this circuit must be implemented
using high bandwidth operational amplifierss and Schottky diodes. Simulation results are shown
in Figure 4.6 for a 100kHz, 2V peak-to-peak square wave input with CF = 30pF and R = 100Ω.
This simulation was performed in SIMeTrix using the SPICE models for the op amps, each an
AD8065 model with 145MHz bandwidth. The average value of the output of the circuit is
0.992V so there is less than a 1% discrepancy.
Figure 4.5: Precision rectifier circuit.
Time/uSecs 2uSecs/div
0 2 4 6 8 10 12 14 16 18
Irect / V
-0
0.2
0.4
0.6
0.8
1
Figure 4.6: Sample waveform for the precision rectifier circuit fed with 2Vpk-pk square wave at 100kHz.
84
4.2. Gating signal generator
The frequency control signal vc is converted to a clock signal using a voltage controlled oscillator
(VCO). The VCO is implemented using the CD4046 chip. Its transfer function is shown in
Figure 4.7. For a frequency range fmax = 145kHz and fmin = 100kHz and for VDD = 15V, the small
signal gain of the VCO is as follows:
( )π
π6000
2 minmax =−
=DD
fcV
ffG (4.6)
Figure 4.7: Voltage controlled oscillator transfer function.
4.3. Small Signal Model
Development of the small signal model for the SPRC has been described in section 3.3.5. As
shown in section 3.5.2, this model changes only slightly with the addition of the current doubler
rectifier. The system equations are reproduced here for convenience.
85
−=
−=
=
+−−=
RivabsL
idt
d
viiC
vdt
d
iC
vdt
d
tVvvL
idt
d
LfCp
f
Lf
CpoLs
p
Cp
Ls
s
Cs
ssCpCs
s
Ls
2)(2
11
)sgn(1
1
))sgn(sin(1
ω
(4.7)
After this system is linearized about the operating point, the control-to-output transfer functions
for the converter can be obtained as follows, where a factor of 2 is added to obtain the output
current from the current flowing through one of the two current doubler inductors:
[ ]
[ ]
−=
−=
−
−
1
0)(2000000
)(ˆ)(ˆ
0
1)(2000000
)(ˆ)(ˆ
1
1
BAsIsv
si
BAsIs
si
s
o
s
o
ω (4.8)
Bode plots of the frequency-to-output current transfer functions at rated and half rated load are
shown in Figure 4.8.
86
Figure 4.8: Bode plots of the frequency-to-output current transfer functions at rated and half rated load.
4.4. Current sensor and compensator
It can be seen from Figure 4.8 that the -3dB frequency (with respect to the dc gain) for each
curve is greater than the switching frequency of the converter. Therefore, a pole is required in
the current loop to bring the crossover frequency to a value less than 1/10th the Nyquist
frequency (50kHz) of the converter. The current compensator transfer function will have the
following form:
+=
1
1
ci
cicis
KGτ
(4.9)
From the above Bode plots, the dc gain of Gif is -85.3dB. Multiplying this by Gfc and Hi gives a
loop gain of 0.05. To minimize the error between the output current and reference current, Kci
87
should be designed for a gain greater than unity. Then, τci can be designed to obtain the desired
crossover frequency less than 5kHz. Bode plots for the closed loop system with Kci = -1000 and
τci = 0.2 are shown in Figure 4.9. For rated load, the crossover frequency is approximately
220Hz with a phase margin of 93°. For half rated load, the crossover frequency is 50Hz with a
phase margin of 90°. Since the crossover frequency is low for each case, it can be seen that the
current compensator provides sufficient noise rejection so that additional low pass filtering of the
rectified current signal is not required.
The current waveform for each case is shown in Figure 4.10. Fast rise time is accomplished with
no overshoot in the full load case (100A) and very little overshoot at half rated load (50A).
Figure 4.9: Bode plots of current loop HiGifGfc.
88
Figure 4.10: Simulated output current for current loop control at rated load (top) and half rated load
(bottom).
4.5. Voltage sensor and compensator
With the above inner current loop compensation, the voltage controller can be designed around a
new plant with transfer function given by:
icifcif
cifcifeq
ref
out
HGGG
GGGR
ti
tv
+=
1)(ˆ)(ˆ
(4.10)
The voltage compensator will be designed as a PI compensator with the following transfer
function:
+=
s
sKG cv
cvcv
τ1 (4.11)
This compensator produces infinite gain at dc so the output voltage will track the reference
89
voltage. The output of this compensator is then the reference current signal.
Bode plots of the reference current-to-secondary voltage transfer function for rated and half rated
loads are shown in Figure 4.11. The zero of the compensator should be placed at a frequency
less than 1/10th of the crossover frequency so as not to introduce phase margin at the crossover
frequency. Placing the zero at 25Hz gives τcv = 1/(50π). Plotting equation 4.10 multiplied with
Hv allows for the calculation of the required PI compensator gain. The plots of the closed loop
transfer function are shown in Figure 4.11. A gain of Kcv = 700 gives a crossover frequency of
1.2kHz and a phase margin of 60° at nominal load. At half load, the crossover frequency is
380Hz and the phase margin is 80°.
Finally, the pole of the low pass filter (LPF) can be placed. A second order Butterworth filter
will be used with a corner frequency of 11kHz. This places the corner frequency one order of
magnitude above the crossover frequency of the system so that the phase margin is not affected,
but one order of magnitude below the switching frequency to attenuate the harmonics at twice
the switching frequency. The transfer function of this low pass filter is as follows:
110)1050(
15212 ++×
=−− ss
LPF
The Bode plot for the closed loop transfer function with compensator and low pass filter is
shown in Figure 4.13. It can be observed from this plot that the double pole adds an extra -180°
phase only after the crossover frequency so it affects only the high frequency noise rejection of
the system. Closed loop simulation results are shown in Figure 4.14 and Figure 4.15.
For the nominal load case, the output current reaches 100A quickly while the output voltage
90
ramps up slowly due to the charging of the double layer capacitors. For the half rated case, the
current ramps up to 100A to charge the capacitors and then decays to 50A. As a result, the
output voltage reaches rated voltage relatively quickly.
At the beginning of each pulse, the controller operation is nonlinear as the current command is
clamped at an upper limit until the output voltage reaches a threshold (3 to 4V, depending on the
loading) to move the controller into the linear regime. The current compensator is initialised to
+15V at the beginning of each pulse to guarantee that the converter begins gating at the
maximum rated switching frequency of 145kHz. While the voltage compensator demands
maximum rated current to bring the voltage up as quickly as possible, the response is limited by
the dynamics of the current compensator, which is designed in such a way to prevent an
overshoot as the switching frequency decreases toward the resonant frequency.
Figure 4.11: Reference-to-secondary voltage transfer functions.
91
Figure 4.12: Closed loop transfer function for the system with PI compensator.
Figure 4.13: Closed loop transfer function with 2nd order LPF for noise rejection.
92
Figure 4.14: Closed loop simulation results at nominal load.
Figure 4.15: Closed loop simulation results at half rated load.
93
The first pulse in each simulation corresponds to the system initialized to zero voltage. The
second pulse corresponds to the response after the system has been off for only a 10ms off pulse.
The response is slightly different because the double layer capacitor has not totally discharged by
the time the second pulse begins, as predicted in models presented in section 2.4.1.
94
Chapter 5 Experimental Results
This chapter presents open loop, low voltage results for the SPRC. Low voltage experiments are
performed on a proof of concept circuit in order to verify the basic operation of the converter.
Section 5.1 contains a description of the prototype circuit board. Section 5.2 presents
experimental steady state waveforms extracted from the prototype circuit. Pulsed operation of
the converter is experimentally verified in section 5.3 and the voltage estimation hardware is
verified in section 5.4. Section 5.5 contains a discussion of the results and experimental
limitations.
5.1. Prototype circuit board
The SPRC is implemented on a prototype 2 layer printed circuit board (PCB), shown in Figure
5.1. The size of the board is 8”x11”. In addition to the power train and logic circuitry, it
includes 2 independent power supplies, ±15V to power the logic circuitry and gate drivers and
+15V for the synchronous rectifier. At the input is a power factor correction module, the
PF1000A-360 made by Lambda Power, which supplies 1008W at 360V with 100VAC input for
use in future high voltage tests.
The parts list is given in Appendix B and the schematics for the PCB are provided in Appendix C.
95
Figure 5.1: Prototype circuit.
5.2. Steady state circuit verification
The prototype circuit is run at low power with an input voltage Vg = 50V. The converter is
loaded with a 50mΩ resistor corresponding to the total equivalent resistance of the cell under
question so that the Q factor is in agreement with the designed value. The converter is operated
at a constant switching frequency of 103kHz, giving a 1.25V, 25A output.
5.2.1. Gating waveforms
The gating signals input to the gate drivers are shown in Figure 5.2. The switches are gated in a
complimentary fashion at 103kHz with no phase shift between the two legs of the full bridge.
There is a delay between gating switches on the same leg to prevent a short circuit. This delay is
measured to be between 156ns and 170ns, as shown in Figure 5.3.
96
Figure 5.2: Full bridge gating waveforms at 103kHz.
Figure 5.3: Gating delays between switches on the same leg of the full bridge.
The resulting output of the full bridge, Vs, is shown in Figure 5.4. Vs is a 103kHz square wave
between -50V and +50V. The square wave is not entirely flat because the IR drop across the full
bridge MOSFETs scales with the sinusoidal resonant current. The maximum IR drop occurs at
peak current, which corresponds to the centre part of the negative and positive half cycles since
the converter is operated near resonance.
97
Figure 5.4: Input voltage to the resonant tank, Vs, at Vg = 50V.
5.2.2. Resonant tank waveforms
Figure 5.5 shows the the voltage across the series resonant inductor, vLs, and its integral, which is
used to compute the resonant current as follows:
[ ]pkpk
Ls
s
pkpkLs dtvL
i−− ∫=
1, (5.1)
The peak-to-peak amplitude of vLs is 1.01kV. The peak-to-peak voltage of ∫ dtvLs is 1.44mVs
and the resonant inductor Ls is 500µH. Therefore, the peak-to-peak resonant current is 2.88A.
98
Figure 5.5: Series resonant inductor voltage, vLs, and its integral, which is used to estimate the series resonant
current, iLs.
As shown in Figure 5.6, the resonant current lags the input voltage (which is in phase with the
gating of Q1) by 900ns. Therefore, zero voltage switching is achieved.
Figure 5.6: Magnification of vLs and its integral showing the extent to which resonant current lags the input
voltage.
99
The voltages across the series and parallel resonant capacitors are shown in Figure 5.7. As
expected, both voltages are sinusoidal with a similar amplitude where vCs,pk-pk = 454V and vCp,pk-
pk = 459V. The slight difference can be attributed to the tolerance of the capacitors.
Figure 5.7: Steady state voltage across the series resonant capacitor, vCs, (left) and voltage across the parallel
resonant capacitor, vCp, (right).
5.2.3. Output waveforms
The measured voltage across the secondary winding of the transformer is shown in Figure 5.8.
Its peak-to-peak voltage is vsec,pk-pk = 9.7V. This voltage should be related to vCp,pk-pk, the voltage
across the transformer primary winding, by the turns ratio 48:1. Thus, it should be given by
vCp,pk-pk / 48 = 9.6V, which is in good agreement with the measured value. The secondary
voltage waveform is sinusoidal but slightly distorted due to latency associated with the gating of
the synchronous rectifier.
100
Figure 5.8: Voltage across the transformer secondary winding, vsec.
The operation of the synchronous rectifier is verified in Figure 5.9. This figure shows the sensed
drain-to-source voltage across one of the synchronous rectifier switches, vds1, and the gating
signal for that switch SR1,gate. The drain-to-source voltage of the switch is a half wave rectified
version of the secondary side voltage. This signal is sensed by the IR1167 synchronous rectifier
chip and the output of the chip is a 15V gating signal which turns the FET on when vds1 goes
below zero. In this way, the FET acts as a diode with only an iR voltage drop across it, where R
represents Rds, the on-state resistance of the drain-to-source channel.
101
Figure 5.9: Drain-to-source voltage, vds1, and gating signal, SR1,gate, for one sychronous rectifier MOSFET.
Figure 5.10: The sum of the drain-to-source voltage across each synchronous rectifier switch, giving the
rectified secondary side voltage.
Figure 5.10 shows the sum of the drain-to-source voltages across both switches. These voltages
are half wave rectified voltages shifted by 180º with respect to one another. By summing them,
the rectified secondary side voltage can be obtained. The average of this voltage, 1.34V,
102
provides an estimate of the output voltage.
Figure 5.11 shows the converter output voltage. The average value of this voltage is vout = 1.27V,
which is reasonably close to the 1.34V estimate. The voltage has a 20% ripple which is very
high compared to the 1% specification. This may be due in part to noise, a delay in the
synchronous rectifier gating which changes the nature of the waveform, and any asynchronous
behaviour in the circuit, which can introduce a fundamental harmonic into the waveform. Future
work is needed to investigate this further. The issue may disappear in high power tests.
Figure 5.11: Converter output voltage.
5.3. Pulsed circuit verification under open loop conditions
With the same operating point of Vg = 50V and fs = 103kHz, the converter output is pulsed at
10Hz. This pulsing is accomplished by enabling and disabling the full bridge gate drivers using
an external signal with a peak voltage of 15V. Figure 5.12 shows the output waveform. Figure
103
5.13 and Figure 5.14 show the evolution of the output voltage and parallel capacitor voltage at
the beginning of each transient. It can be seen that continuous voltage transient is accomplished
as expected due to the choice of Q for this converter.
Figure 5.12: 10Hz pulsed output voltage.
Figure 5.13: Evolution of vout and vCp at the beginning of a pulse.
104
Figure 5.14: Magnification of the turn on transient for vout and vCp.
5.4. Voltage estimation verification
Figure 5.15 shows the actual output voltage, vout, and the estimated output voltage, vest. The
estimated voltage, obtained from rectifying, filtering and amplifying the auxiliary transformer
voltage, has a steady state amplitude of 2.5V. The voltage is amplified by a factor of 2 in the
logic circuit to reduce the signal-to-noise ratio, so the actual estimated voltage is 1.25V. This is
in good agreement with the actual output voltage, which was measured to be 1.27V.
The main difference between these waveforms is that on turn on, there is a spike in the estimated
voltage, which can be seen in Figure 5.16. This spike corresponds to the dynamics of the output
filter inductors and is accounted for in the controller design, as discussed in chapter 4.
This verifies the performance of the estimation circuitry. The same estimation technique was
used for the current estimator. Although the current estimator should therefore work in principle,
it cannot be experimentally verified at these low power levels because the signal is too low so
105
noise becomes a problem. This is left for future work.
Figure 5.15: Actual and estimated output voltage.
Figure 5.16: Magnification of actual and estimated output voltage.
5.5. Discussion
The above results provide experimental verification of the steady state and open loop pulsed
operation of the SPRC and the voltage estimation technique. At low voltage levels, it was not
possible to test for the full range of operating points for this converter since the operation of the
106
synchronous rectifier requires a minimum drain-to-source voltage across the rectifier MOSFETs.
However, the low voltage results do agree with the expected operation and the continuous pulsed
transient behaviour of the converter has been proved. Full voltage testing to verify operation of
the converter over the full design range is left for future work.
107
Chapter 6 Conclusions, Contributions and Future Work
A 500W power supply has been designed for an electrochemical wastewater treatment cell stack.
This power supply would be packaged with a cell stack in one assembly, allowing for distributed
control of water treatment modules and taking advantage of economies of scale due to the
modular design. This thesis dealt with the design of the supply from initial modeling studies of
the electrochemical load to a detailed control strategy and experimental open loop studies on a
prototype converter circuit.
Both the series resonant converter and series parallel resonant converter were considered for this
application due to their potential to satisfy the design objectives of galvanic isolation, high power
density, high efficiency, low energy storage, inherent self protection, modularity, satisfaction of
EMI and safety regulations, and variable frequency pulsed output capabilities. It was shown
through a design of each converter topology that the transient, steady state and small signal
behaviours of the converters are comparable. The generalized averaging model using a
fundamental approximation provides good agreement with the simulated operation of each
topology. With the additional factor of pulsing being considered, placing restrictions on the Q
factor in each case allows for a continuous open loop transient to be achieved, which is desirable
for controllability. The main deciding factor was the output stage, for which the SPRC is
superior due to the lack of a high frequency, high current filter capacitor and the ability to
implement a current doubler synchronous rectifier, which gives a significant improvement in
efficiency over a simple diode rectifier.
It was shown through simulations that the SPRC can be controlled over a range of loads (50-
100A) using an inner current control loop and outer voltage control loop. The inner current loop
108
provides inherent protection and allows for paralleling of modules while the voltage control loop
contains a proportional integral controller to track a desired reference voltage. The current and
voltage feedback quantities are sensed from the primary side using an estimation scheme which
eliminates the need for secondary side sensing, thus simplifying the board layout and reducing
board cost.
Low voltage tests of a prototype SPRC verified the functionality of the power train in open loop
steady state and pulsed operation. The converter was shown to operate in a continuous transient
mode in pulsing and the voltage estimation technique was shown experimentally to be effective
in estimating the output voltage. The current estimation technique could not be evaluated in the
low voltage functionality tests because the current estimation needs to be tested at full load to
achieve a reasonable signal-to-noise ratio. Testing of the control loop needs to be done on a full
cell stack, which is under development.
6.1. Contributions
The primary contributions of this work are:
• Design guidelines and criteria for the series and series-parallel resonant converters with a
pulsed, electrochemical load.
• A high side voltage and current sensing and estimation scheme for control of a resonant
converter.
6.2. Future Work
To optimize this system requires work not only on the development of the power converter but
also on developing a deeper understanding of the load in question. A full dynamic model of the
109
electrochemical load would allow a controller to select an operating point in real time, according
to cell conditions. Whether each item detailed below is strictly necessary to optimize this system
is unknown at this point. Future work includes:
• Development of a dynamic electric circuit model for the electrochemical cell stack that
includes the effect of different reaction kinetics involved in wastewater treatment, oxide
formation on the anode, degradation of both electrodes, temperature and flow rates.
• Development of system identification algorithms that can extract, from the cell model, the
half cell potential of interest and control that potential rather than the voltage across the
entire cell. These algorithms would be incorporated into the power converter control loop.
• Optimization of the SPRC power stage subject to operating efficiency, size and cost per
module.
• Experimental closed loop verification of the full converter operation with an electrochemical
cell stack at full power.
• Experimental verification of paralleling converter modules to scale the output to various
power levels.
110
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[9] J.C. Puippe and N. Ibl, “Influence of charge and discharge of electric double layer in pulse
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[10] K. Viswanathan et al, “The application of pulsed current electrolysis to a rotating-disk
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[12] K. Viswanathan and H.Y. Cheh, “Mass transfer aspects of electrolysis by periodic currents,”
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[13] N.V. Mandich, “Pulse and pulse-reverse electroplating,” Metal Finishing (USA), vol. 100,
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[17] R. Oruganti and F.C. Lee, “Resonant power processors, Part I – State plane analysis,” IEEE
Trans. Ind. App., vol. IA-21, no. 6, Nov./Dec. 1985.
[18] I. Batarseh et al, “Theoretical and experimental studies of the LCC-type parallel resonant
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converter,” IEEE Trans. Power Electron., vol. 5, no. 2, April 1990.
[19] R.W. Erickson and D. Maksimovic, Fundamentals of Power Electronics 2nd Ed., Springer
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[30] Magnetics Inc., Powder cores catalogue, 2008.
114
Appendix A Magnetics
All inductors are designed based on the Magnetics Inc. powder cores catalogue [30].
A.1. Output Filter Inductors
The output filter inductors Lf1 and Lf2 are rated as follows:
Lf1 = Lf2 = 10µH
Idc = 50A
Iripple = 0.5Apk-pk
The design procedure is as follows.
1. Select core from core selector charts based on the LI2 product
The core selector chart for MPP toroid cores is shown in Figure A.1. For LI2 = 25mH·A2, the
55071 core is the smallest one satisfying the energy requirement.
115
Figure A.1: Magnetics Inc. MPP toroid core selection chart [30].
2. Calculated the number of turns to achieve the minimum required inductance.
The 55071 core has an effective inductance AL = 61nH/Turn2 ± 8%. Using the minimum
inductance AL,min = 56.1nH/Turn2, the number of turns can be calculated.
13/101.56
101029
6
=××
= −
−
TurnH
HN
3. Adjust number of turns based on the material permeability at the DC bias.
The DC bias due to the DC current is given by the following equation.
cmAcm
ANIH
e
dc /5173.12
5013=
⋅==
l
116
Locating this value on the MPP permeability versus DC bias curve of Figure A.2 gives a
permeability of 0.72 per unit, normalized with the permeability at 0 DC bias. Then the number
of turns is adjusted accordingly.
1872.0
13==′N
Figure A.2: Magnetics Inc. MPP permeability versus DC bias curves [30].
3. Choose wire.
For 50A rated, 9 AWG wire gives approximately 800A/cm2. The resistance is 0.00259 Ω/m and
the cross sectional area is 7.27 mm2. This gives a winding factor of 45%, based on a window
area for this core of 293mm2. At this winding factor, the mean length per turn is 4.27cm.
Therefore, the total resistance of the wire is 2mΩ, giving a power loss of 5W. For the two output
filter inductors, the total power loss is therefore 10W, or 2% of the total output power.
117
A.2. Series Resonant Inductor
The resonant inductor is rated as follows:
Ls = 506µH
vLs = 1875Vpk (sinusoidal)
iLs = 5.7Apk (sinusoidal)
fmax = 140kHz
The choices for the ac inductor design include an MPP toroid, a Kool Mu toroid and a Kool Mu
E or U core. These designs will be compared in this section to determine which material and
geometry is optimal for the application.
MPP Toroid
The largest MPP toroid core available from Magnetics Inc. is the 55909. This core has 14u
permeability, the lowest available for the MPP core. The effective inductance is AL =
20nH/Turn2 ± 8%. The middle value in the error range is used since the resonant tank inductor is
designed for a specific inductance rather than a minimum. The number of turns can be
calculated as follows.
159/1020
1050629
6
=××
= −
−
TurnH
HN
The peak magnetizing field in Oersteds is found as follows. For this core, ℓe = 20cm. A factor of
118
0.795 is included to convert from Amp-turns/cm to Oersteds.
Oecm
ANIH
e
pk 0.36795.020
7.5159795.0 =×
⋅=×=
l
Locating this value on the magnetization curve of Figure A.3 gives a peak flux density of 451
Gauss.
Figure A.3: MPP magnetization curve [30].
At 451 Gauss there is less than a 1% change in permeability for the MPP 14u material. The
typical core loss is given by the following formula.
( ) ( ) 331.121.231.121.2 /190110451.0341.2341.2 cmmWkHzkGfBPFe ===
The volume of the core is 45.3cm3 so the total power loss is 8.6W.
The temperature rise can be calculated as follows, where the surface area of this core assuming a
119
40% winding factor is given in the data sheet as SA = 225.2cm2.
CcmSA
mWPCT L °=
=° 1.20
)(
)()(
833.0
2
Kool Mu Toroid
The largest Kool Mu toroid core available is the 77908. This core has an effective inductance AL
= 37nH/Turn2 ± 8%. The middle value in the error range is used since the resonant tank inductor
is designed for a specific inductance rather than a minimum. The number of turns can be
calculated as follows.
115/1037
1050629
6
=××
= −
−
TurnH
HN
The peak magnetizing field in Oersteds is found as follows. For this core, ℓe = 20cm. A factor of
0.795 is included to convert to Oersteds.
Oecm
ANIH
e
pk 26795.020
7.5115795.0 =×
⋅=×=
l
Locating this value on the magnetization curve of Figure A.4 gives a peak flux density of
approximately 770 Gauss.
120
Figure A.4: KoolMu magnetization curve [30].
At 770 Gauss there is less than a 1% change in permeability for the KoolMu 26u material. The
typical core loss is given by the following formula.
( ) ( ) 36.100.26.100.2 /110011077.0 cmmWkHzkGfBPFe ===
The volume of the core is 45.3cm3 so the total power loss is 50W. This is unacceptably high so
this design must be ruled out.
Kool Mu E and U Core Design
The power loss calculations follow the same procedure as for the toroid and are summarized in
Table A.1 for the 5 largest E cores and 4 largest U cores with 26u permeability (the lowest
available).
121
Core AL
(nH/Turn2)
N le (mm) H (Oe) B
(kilogauss)
ve
(cm3)
PFe (W)
00K5530E 138 60.6 123 22.3 0.68 51.4 43.4
00K6527E 162 55.9 147 17.2 0.55 79.4 44.6
00K7228E 130 62.4 137 20.6 0.64 50.3 37.5
00K8020E 103 70.1 185 17.2 0.55 72.1 40.3
00K8044E 91 74.6 208 16.2 0.53 80.91 41.6
00K130LE 254 44.6 219 9.2 0.35 237 54.1
00K145LE 190 51.6 210 11.1 0.40 155 45.8
00K160LE 180 53.0 273 8.8 0.34 212 45.3
00K6533U 82 78.6 199 17.9 0.57 49.75 29.6
00K7236U 87 76.3 219 15.8 0.52 63.51 31.2
00K8020U 64 88.9 273 14.8 0.49 53.2 23.7
00K8038U 97 72.2 237 13.8 0.47 83.898 33.8
Table A.1: Comparison of power loss for the largest Kool Mu E and U cores.
The core with the lowest power loss is the 00K8020U, which has 23.7W power loss at 110kHz.
The surface area of this unwound core is 135cm2. The temperature rise can be calculated as
follows.
CcmSA
mWPCT L °=
=° 74
)(
)()(
833.0
2
Although the wound core will have a slightly larger surface area so the actual temperature rise
will be slightly lower than this figure, this temperature rise is still unacceptably high. Therefore,
122
this core is not a feasible option for this application.
Final Design
The MPP 14u toroid has the lowest power loss and temperature rise for this application. The
final step in the design is choosing the wire.
If a winding factor of approximately 40% is selected for a window area of 1799mm2, 11 AWG
wire can be used, which has a cross sectional area of 4.64mm2. The resistance of the wire is
0.00413 Ω/m. For this winding factor, the mean length per turn is 7.53cm. Therefore, the total
resistance of the wire is RCu = 0.5Ω, giving a power loss of PCu = ½ Irms2 RCu = 4.1W.
The total power loss for this inductor is PL = PFe + PCu = 12.7W. The total temperature rise is
29ºC, which is acceptable.
123
Appendix B Prototype Circuit Parts List
Designation Device Part Number Description
PF1 Power Factor Correction PF1000A-360 • 360V output • 1008W at 100Vac
KMS1 +15V Synchronous rectifier drive supply
KMS15-15 • Single 15V supply with maximum 1A output • The separate isolated supply is required for the output stage
KMD1 +/-15V Logic and gate driver supply
KMD15-1515 • Dual +/-15V supplies wit maximum 0.5A output
Q1,Q2,Q3,Q4 Full bridge MOSFETs STP11NM60N • Rated for 10A, 600V U1,U2 Full bridge MOSFET
drivers IRS2113PBF • Has a boot strap up to 600V
• It is the fastest HS/LS driver available from International Rectifier
Q5,Q6 Rectifier MOSFETS IRF1324S-7PPBF • Has a very low Rds,on M1,M2 Synchronous Rectifier
Driver IR1167ASPBF • The only SR IC on the
market for resonant converters Cs1, Cs2, Cp1, Cp2,
Resonant tank capacitors 940C30S1K-F • 10nF polypropylene, rated for 750Vac, 2A • 4 are connected in a series-parallel configuration
O1-O10 Control circuit op amps AD8065 • High speed (145MHz) and relatively low cost • Operates off +/-15V
D3-D11 Small signal control circuit diodes
RB521S30T1 • Schottky diode with 0.5V drop at 200mA
CT1 Resonant tank current transformer (sensor)
CST2-020L • 20:1 current transformer in a small package with a high current rating (10A)
U3 Phase Shift Controller UC3875N • 4 outputs • External frequency control is possible
VCO1 Voltage Controlled Oscillator
CD4046B • 15V supply • Up to 1.4MHz operation • Includes a frequency limiter
LT1 Level translator MC14504B • 15V to 5V level translator to interface the CD4046B and UC3875
124
Appendix C Prototype Circuit Schematics
The following schematics are divided into modules corresponding to the power stage, voltage
and current estimators, and controller. Figure C.1 shows the master schematic containing the 3
subcircuits, the master switch, the independent power supplies, the power factor correction
device and the external connections. The power stage, voltage and current estimator and
controller subcircuits follow in Figures C.2, C.3, and C.4.
125
Figure C
.1: M
aster sch
ematic o
f the p
rototype circu
it board.
Q4_ctrl
Q1_ctrl
Q3_ctrl
Q2_ctrl
VO
UT+
NO
T_V_CM
D
Isense
Vsense
Pow
er StageP
ower_Stage.SchD
oc
Q1_ctrl
Q2_ctrl
Q3_ctrl
Q4_ctrl +1
--2
J1CO
NN
+400V
PWR
_GN
D
+1
--2
J6CO
NN
GN
D
+1
--2
J5CO
NN
Q1_ctrl
GN
D
Q2_ctrl
+1
--2
J8CO
NN
GN
D
+1
--2
J7CO
NN
Q3_ctrl
GN
D
Q4_ctrl
Isense
V_EST
Vsense
-I_EST
Voltage &
Current E
stimation
VIest.SchD
oc
V_EST
Q1_ctrl
Q4_ctrl
Q2_ctrl
Q3_ctrl
-I_EST
V_CM
DN
OT_V
_CMD
SystemE
nable
Controller
Controller.SchD
oc
C30
C31C
32
C34
C33
+1--2J2C
ON
N
LO
AD
_GN
D+
15_SR
GN
D
-15
+15
+1
--2
J3CO
NN
+1--2J4CO
NN
+1
--2
J9CON
N
100VA
C
AC
_GN
D
1K Rinr
C35C
36
C37
C40Cap Sem
i
GN
D Rs1
Res3
+15
+15
GN
D
System
Enable
+1
--2
J10
CO
NN
GN
D
VSS3
Output
4V
DD
5
Input2
U6 A
C(L
)-V
1
+V
1A
C(N
)
KM
S1
KM
S15
AC
(L)
-V2
+V
1A
C(N
)
CO
MM
KM
D1
KM
D15
S2Switch
+1
--2
J11
CO
NN
LO
AD
_GN
D
+1--2
J12
CO
NN
GN
D
+1
--2
J13
CON
NG
ND
+1
--2
J14
CO
NN
GN
D+
1--2
J15
CON
NG
ND
AC
(L)
AC
(N)
+VR-VSG
EN
APC
IOG
AU
X
BP
PF1
PFC
C45
Master Sw
itch
126
Figure C
.2: P
ower sta
ge sch
ematic.
10nF Cs3
500uH
Ls1
10nFC
p1
10uH
Lf1
Q1_ctrl
Q4_ctrl
Q2_ctrl
Q3_ctrl
VO
UT
+1
H9
1
H5
1
H6
1
H7
1
H8
LO
AD
_GN
D
10uH
Lf2
VD
5
VS
6
GN
D7
VG
AT
E8
VC
C1
OV
T2
MO
T3
EN
4M
1
IR1167
VD
5
VS
6
GN
D7
VG
AT
E8
VC
C1
OV
T2
MO
T3
EN
4M
2
IR1167
5R
g1
75KR
mot1
75KR
mot2
PW
R_G
ND
RQ
1R
es1R
Q4
Res1
RQ
2R
es1
RQ
3R
es1
GN
D
C1
D1
C2
C4
D2
C5
RC
T1
Res1Isense
Vsense
+1
--2
LO
AD
RA
DSO
K
+15_SR
5R
g2
+15
+400V
NO
T_V
_CM
D
GN
D
GN
D
8
VD
D9
HIN
10
SD11
LIN
12
VSS
1314L
O1
CO
M2
VC
C3 4
VS
5V
B6
HO
7U
1
IR2113
8
VD
D9
HIN
10
SD11
LIN
12
VSS
1314L
O1
CO
M2
VC
C3 4
VS
5V
B6
HO
7U
2
IR2113
+15_SR
10nFC
p2
10nFC
p310nFC
p4
10nF Cs4
10nFCs1
10nFCs2
Iin8
Iout7
Isec+6
Isec-4
CT
1C
ST
57810 34
1269
TFM
R
Transform
er
D S
GQ
6IR
F1324S
DS
GQ
5
IRF1324S
Q1
STP
11NM
Q3
STP
11NM
Q4
STP
11NM
Q2
STP
11NM
VIN
+
VIN
-
RQ
1_2R
es1D
13
RQ
3_2R
es1D
14R
Q2_2
Res1
D15
RQ
4_2R
es1D
16
500uH
Ls3
C55
C56
C57
C58
1
H13
127
Figure C
.3: S
chem
atic o
f voltage a
nd cu
rrent estim
atio
n circu
its.
Isense-I_E
ST
10KR
7
GN
D
Vsense
GN
D
GN
D
V_E
ST
D9
Schottky
2K R16
1K R11
1K R12
100nF
C14
50nFC
15
10KR
8
+15
-15
+15
-15
+15
-15
6
+7
-4 +
3
-2
O4
6
+ 7-4 +3
-2
O5
6
+7
-4 +
3
-2
O6
GN
D
1K R9
1K R10
1K R13
1K R14
D10
Schottky
1K R15
30pF
C13
GN
D
D12
Schottky
2K R22
+15
-15
+15
-15
6
+7
-4 +
3
-2
O7
6
+ 7-4 +3
-2
O8
GN
D
1K R17
1K R18
1K R19
1K R20
D11
Schottky
1K R21
30pF
C16
1
H14
Precision R
ectifier
2nd Order B
utterworth Filter
Precision R
ectifier
128
Figure C
.4: C
ontro
ller schem
atic.
-I_EST
V_EST
Q1_ctrl
Q4_ctrlQ2_ctrl
Q3_ctrl
VRE
F1
E/AO
UT
2
E/A-
3
E/A+
4
CS+5
SOFT
STA
RT6
DEL
AY
SET_C-D
7
OU
TD8
OU
TC9
VC
10V
IN11
PWR
GN
D12
OU
TB13
OU
TA
14D
ELAY
SET_A
-B15
FREQSET
16CLO
CK
SYN
C17
SLOPE
18R
AM
P19
GN
D20
U3
UC3875
+15
PWR_G
ND
GN
D
43KR23
470pFC
18GN
D
V_CMD
4.5KR
261.4uFC19
100KR
27
2uFC20
Freq_setI_set
+15
-15
+15
-15
400pFC21
GN
D
75KR
25
75KR
24
GN
D
+15
6
+7
-4 +
3
-2
O9
6
+ 7-4 +3
-2
O11
1KR
30
500R31
GN
DG
ND
20R28
+15
D5
Diode
D3
Diode
+15
GN
D
R32
+15D
6D
iode
D7
Diode
GN
D
C22
GN
D
V_G
AT
E
+15
-15
GN
D
6
+ 7-4 +3
-2
O12
R33
21
3
PO
T1
6
+7
-4 + 3
- 2
O13
+15-15
GN
D
2KR
34
2K R35
NO
T_V_CM
D
System
Enable
1
H11
5 R40
5R
41
1
H12
VSS3
Output
4V
DD
5
Input2
U5
VSS3
Output
4V
DD
5
Input2
U4
PP1
Out1
2
CompIn
3
VCO
_Out
4
Inhib5
C1(1)6
C1(2)7
VSS
8V
CO
_In9
Dem
_Out
10R1
11R2
12O
ut213
SigIn14
Zener15
VD
D16
VC
O1
CD
4046
VCC
1
Aout
2
Ain
3
Bout4
Bin5
Cout6
Cin7
VSS
8D
in9
Dout
10Ein
11Eout
12M
OD
E13
Fin14
Fout15
VD
D16
LT1
MC14504
+15
GN
D
GN
D6.8KR42
GN
D
10nFC23
6.8KR
43
GN
D
10nFC24
1uFC25
100R29
Q7
STP11N
M
Q8
STP11N
M
R48 C41
R51
R49R50
R46R47
C43
GN
D
C42
GN
D
21
3P
OT2
R44
R45
1K R53 1K R52
1K R54
21
3
PO
T3
2
13
Z1
10mH
L1Inductor
Voltage PI Com
pensatorC
urrent Com
pensator (1 pole)
VCO
Phase shift controller
Buffer
Variable gain inverter
Schmitt Triggers