1 the b a b ar silicon vertex trackerdouglas roberts, ucsb vertex ‘97, mangaratiba, brazil the b a...

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The BABAR Silicon Vertex Tracker Douglas Roberts, UCSB

Vertex ‘97, Mangaratiba, Brazil

The BABAR Silicon Vertex Tracker

Douglas Roberts

University of California, Santa Barbara

BABAR Collaboration

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Outline

BABAR and PEP-II Design and Physics Goals Silicon Vertex Tracker (SVT) Design

Considerations SVT Description

– Layout

– Silicon Wafers

– Upilex Fanouts

– Readout Electronics» Front End IC (AToM Chip)

» Hybrid and Tails

– Mechanical Support Assembly and Testing Prelim. Results From Recent System Test and

Beam Test Project Status

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BABAR SVT Collaborators

Italy– INFN, Ferrara

– INFN, Milano

– INFN, Pavia

– INFN, Pisa

– INFN, Torino

– INFN, Trieste

U.S.A.– U.C., San Diego

– U.C., Santa Barbara

– U.C., Santa Cruz

– Lawrence Berkeley National Laboratory

– Stanford University

– U of Wisconsin

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BABAR Physics Goals

International collaboration of ~530 physicists and engineers from 10 countries

Primary physics goal of the BABAR experiment is the systematic study of CP asymmetries in the decays of B0 and B0 mesons.– Reconstruct one of the B0 mesons in an exclusive

CP-study final state

– Tag the flavor of the other B meson in the event

– Measure the relative decay time of the two B mesons.

e+e- (4s), = 0.56

B0,zCP B0,

ztag

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BABAR Physics Goals (cont.)

Standard Model predicts a time-dependent CP asymmetry:

Time integral of Af(t) = 0 at (4s), which makes a measurement of the time dependence essential– Reason for asymmetric collider

– Good vertex determination extremely important

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PEP-II at SLAC

Asymmetric e+e- collider– E- = 9.000GeV, E+ = 3.109GeV

L = 3.0 x 1033 cm-2 s-1 , ultimately 1034.– ~30M BB/107s

Time between beam crossings = 4.2ns 0 crossing angle

– Final focus dipoles ~20cm from IP

– Very little space for SVT readout electronics

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SVT Design Considerations

Vertexing Requirements– Mean vertex separation of 250m want single vertex

resolution better than ~80m.

– Readily achieved with silicon strip detectors Acceptance

– Want as close to 4 as possible

– Magnets at 17.2, both forward and backward

– Boost makes forward region very important» Move most manifolds and flanges to the rear

– Coverage from 20 < < 150.» In center-of-mass, 0.84 > coscm >-0.95

– All electronics outside of active tracking volume Stand-alone tracking

– Drift chamber begins at 22.5cm, so need to reconstruct particles with pt < 100MeV in SVT alone.

Radiation Tolerance– Layer 1 averages ~33 krad/yr

» Non-uniform in » Local max of 240 krad/yr for ~6

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SVT Layout

5 Layers of double sided AC coupled silicon microstrip detectors

Inner 3 layers have six modules arranged azimuthally around the beampipe

Outer 2 layers have 16 and 18 modules, respectively.

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SVT Layout (cont.)

Each layer has strips oriented parallel ( strips) and perpendicular (z strips) to the beam line

Total of 340 silicon wafers of 6 different types

About 0.94m2 of silicon ~150,000 readout channels

350mr30

Kevlar/Carbon Fiber Support Structure

Carbon Fiber Support Cone

Hybrid

Silicon

Beam Pipe(~1% X0)

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SVT Layout (cont.)

End View of BaBar Silicon Vertex Detector

LayerRadius (mm)

Modules / Layer

Wafers / Module

Phi Pitch (um)

Z Pitch (um)

1 32 6 4 50 1002 40 6 4 55 1003 54 6 6 55 1004a 124 8 7 100 2104b 127 8 7 100 2105a 140 9 8 100 2105b 144 9 8 100 210

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Silicon Wafers

6 different wafer models Wafers manufactured by Micron Made of 300m thick high resistivity

silicon with a [111] orientation

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Silicon Wafers:Mechanical Specifications

Wafer Type I II III IV V VI (wedge)Dimensions (mm)

z 42.40 45.40 43.90 67.55 53.90 67.97 41.30 49.42 71.47 52.50 52.50 52.80 -> 43.30

Readout Pitch (um)z 100 100 100 210 210 210 50 55 55 100 100 100 -> 82

Number of Stripsz 411 441 426 316 251 318 799 874 1275 512 512 512

Phys. Strip Pitch (um)z 50 50 50 105 105 105 50 55 55 50 50 50 -> 41

‘Physical Strip Pitch’ includes floating strip (strips not connected to readout electronics)

Models I, II and III have strips on the side; Models IV, V and VI have strips on the J side

strips on wedge detector vary such that the ratio between width and pitch is a constant

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Model II Wafer, -Side ()

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Model II Wafer, J-Side (z)

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Model VI Wafer (wedge),J-Side ()

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Summary of Measured Wafer Parameters

Quantity

Rbias

Vdepl

Ibias

CIS

CAC

Cback

Rs (implant)

Rs (metal)

Radiation Damage

Value

~5 M (varies)

15-40 V

<100nA/cm2

1 pF/cm

20-40 pF/cm *

0.2, 0.4 pF/cm *

27, 55 k/cm *

7, 13 /cm

~ 300 nA/cm2/Mrad

* Depends on model number

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Upilex Fanouts

Provide an electrical connection between the metal strips on the silicon wafers and the front-end chip

Gang together z strips on outer 2 layers (2 strips read out by same electronics channel)

Testing area allows for testing before readout electronics are attached

Layer 2 FanoutsZ Fanout

Fanout

Testing Area

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Upilex Details

50m thick Upilex ™ substrate– UBE Industries Ltd, Japan.

4.5m Cu layer deposited on an adhesive 150nm Cr layer

Cu and Cr are etched to create circuit 150nm of Cr followed by 1m Au

(for wire bonding) are then electrolithically deposited

Trace resistance is typ. 2/cm Inter-trace capacitance = 0.52pF/cm

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Front-end IC(AToM Chip)

Must amplify, shape and digitize input in parallel for all channels

Buffer for duration of Level 1 trigger latency Sparsify data for readout High rates and small time between beam crossings

(4.2ns) implies data acquisition, digitization, buffering and readout must occur simultaneously

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Photo of Rad-Soft AToM

128 channels

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Shaper Output

Shaping time set to 100ns (setable to 100, 200, 300 or 400ns)

Charge injected via on-chip calibration circuitry

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Time-Over-Threshold Output

Comparison of analog ToT measured at comparator output and digitized ToT

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Expected Noise Performance

LayerShaping

Time (ns) Side ENC (e-)

1 100 Z 600 880

2 100 Z 660 810

3 200 Z 730 940

5 400 Z 910 1310

Based on full SPICE simulation– Front-end circuit

– Detector network based on measured detector parameters

– Upilex fanout

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Test Bench ResultsLayer 2 Module

Test bench consists of prototype of full SVT readout system:– Silicon + Upilex

– Rad-Soft AToM chip and Hybrid

– Prototype data transmission and DAQ

Decreasing Threshold

# F

irin

gs/(

50 e

vent

s)#

Fir

ings

/(50

eve

nts)

Threshold (DAC cnts)

Threshold (DAC cnts)

Threshold Scan

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Measured Offsets and Gains for 2 ICs

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Noise (in DAC counts) Measured from Threshold Scan

SideENC1070 e-

(calc = 880 e-)

J SideENC860 e-

(calc = 600 e-)

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Hybrid

Double sided, multi-layer, thick-film circuit fabricated on 1.2mm thick AlN

3 Different Models– H1 (Layers 1 and 2) has 7 ICs/side

– H2 (Layer 3) has 10 ICs/side

– H3 (Layers 4 and 5) has 4 ICs on side, 5 on z side

Connects to power and data transmission system via flexible multi-layer kapton/copper tail (2 per hybrid)

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Hybrid Pictures

Component Layout of H1 (Layers 1 and 2) with 7 ICs per side

Photograph of H3 prototype (Layers 4 and 5)

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Mechanical Support:Ribs and ‘Foot’

Kevlar / Carbon Fiber Support Rib

Molded Carbon Fiber Endpieces

Layer 2 Rib and Endpiece Assembly

Exploded View of ‘Foot’ Region

Kevlar/CF Ribs

CF Endpiece

Cooling RingSilicon Upilex

FanoutsAlN Hybrid

AToM IC

Berg connector and tails

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Mechanical Support

Modules mounted on brass cooling rings, which are mounted on carbon fiber support cones

Forward and Backward cones held together with carbon fiber space frame

Entire assembly mounted on B1 magnets (final focus RE dipoles)

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Finished Space Frame

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Module Assembly and Testing

Layer 2 Half-Module in ‘Ringframe’ fixture.

Upilex testing area still attached.

Side

z Side

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Testing Probe

Automated probe for testing modules before readout IC is attached

Uses 256-pin probe array to contact testing area on Upilex fanout

Connects to pA meter / Voltage source, LCR meter, single channel Q-amp

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Attachment of Hybrid

Upilex testing area is removed Hybrid is attached to Upilex Still utilizes same ringframe fixture

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Module Stiffening

Gluing carbon fiber / Kevlar ribs to a Layer 2 Module

Finished Module after rib attachment(upside-down)

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Arch Module Assembly

Module is assembled flat– Wafer-to-wafer gluing (except at bend)

– Upilex fanout glued to silicon

– Wirebonding and testing

– Attachment to hybrid

Bend angles vary from 21 to 28

Bending operation done on three fixtures that simulate the positions of the support cone mounting buttons– Defines rotation angle and axis

Stiffening ribs attached after bending is complete.

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PRELIM

PRELIM

Prelim. Testbeam Results

CERN testbeam run with prototype layer 2 and layer 5 modules

Just finished data taking Monday, Aug. 25 All results are VERY PRELIMINARY

– Chip calibration not done.

– No alignment corrections made

Correlation between projected track position and hits in the SVT module

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PRELIM

PRELIM

Prelim. Testbeam Results

Position correlation vs. angle of incident track.

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Project Status

Many mechanical parts fabricated: support cones, space frame, ribs, endpieces...

Silicon wafer production underway; all 6 models perform as expected– ~60% of wafers already delivered from Micron

System test has verified a working readout system with reasonable noise performance

Final version of AToM IC has been submitted for rad-hard fabrication; expect chips in Dec.

First Layer 2 and Layer 5 modules have been constructed

Goal for installation: End of 1998

1 the b a b ar silicon vertex trackerdouglas roberts, ucsb vertex ‘97, mangaratiba, brazil the b a...

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