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CMOS Technology

IC Fabrication

Presented by

Saikat Bandyopadhyay

ISL-MOD1(H)PR1


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Interra Systems 2

Sub-module Description

Schedule:

Presentation: 2 sessions

Objectives:

To familiarize SpecToLayout trainees with the components of IC

fabrication

Aim:

Enable S2L trainees to understand and appreciate aspects of ICfabrication


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Contents

1. Introduction

2. Physical and chemicalproperties used in ICfabrication

3. Silicon crystal growth

4. Wafer preparation5. Photolithography

Oxidation

Doping - Diffusion

Doping - Ion implant

Metalization

Epitaxial growth Isolation

6. Cutting and packaging

7. Nmos fabrication

8. Cmos fabrication

9. Other devices

BJT Diode

Schottky diode

Resistance

Capacitance

10. Summary

11. Reference


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Introduction

Todays session covers:

Components of IC fabrication

Types of fabrication


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Chemical and Physical Properties

Silicon can be easily manipulated to achieve desired physicalproperty Silicon is a semiconductor

SiO2is an insulator

Polysilicon is conducting

SiO2: Cannot be penetrated by n and p type impurities Can be selectively removed using HF (Silicon is impervious to HF)

Photosensitive polymers can be selectively solidified as this materialis resistant to HF

The solidified photo resistive covering can be removed with hot

H2SO4and mechanical abrasion SiO2is resistant to this process


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Silicon Crystal Growth

IC components are fabricated on monolithic

metallurgical grade silicon

Monolithic silicon crystal is grown using:

Czochralski (CZ) crystal growth process

Float Zone (FZ) process CZ is the most popular among these methods
http://images.google.co.in/imgres?imgurl=http://onlineheavytheory.net/images/fig2.jpg&imgrefurl=http://onlineheavytheory.net/silicon.html&h=370&w=499&sz=42&hl=en&start=9&tbnid=TJx-CbmmBUKNcM:&tbnh=96&tbnw=130&prev=/images%3Fq%3Dsilicon%2Bcrystal%26svnum%3D10%26hl%3Den%26lr%3D%26sa%3DGhttp://images.google.co.in/imgres?imgurl=http://cc.ee.ntu.edu.tw/~ywchang/Courses/Pic/fig1-13.jpg&imgrefurl=http://cc.ee.ntu.edu.tw/~ywchang/Courses/Vlsi2k/pictures.html&h=275&w=512&sz=30&hl=en&start=5&tbnid=0i4r2652zPSYdM:&tbnh=70&tbnw=131&prev=/images%3Fq%3Dsilicon%2Bcrystal%26svnum%3D10%26hl%3Den%26lr%3D%26sa%3DG


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Wafer Preparation

Steps to prepare wafers:1. Quartzite, a type of sand that's used as raw material for wafers,

undergoes a complicated refining process to become electronic grade

polysilicon (EGS)

2. The EGS material is then used to grow single crystal ultra pure silicon

ingots by the Czochralski (CZ) or Float Zone (FZ) method

3. Each ingot then undergoes grinding, sawing, and polishing to yield

many wafers


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CZ Crystal Growth

A fused silica crucible is loaded with EGS intoa precise amount of diluted silicon alloy

The gases inside the growth chamber arereplaced by an inert gas to inhibit the entranceof atmospheric gases into the melt during

crystal growing The silicon charge inside the chamber is thenmelted (Si melting point = 1421 C)

A slim seed of crystal silicon (5 mm dia. and100-300 mm long) with precise orientation isintroduced into the molten silicon

The seed crystal is then withdrawn at a verycontrolled rate. The seed crystal and thecrucible are rotated in opposite directions whilethis withdrawal process occurs


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Wafer Cutting

Silicon ingot is cut into wafers

Average thickness of wafer 0.25 mm

Flatness < 3 micron

Wafer slicing machinefinished wafer


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Photolithography

Literally means writing with light

Is a method of manufacturing IC

Involves creation of insulation layers in form of Silicon Oxide

Is used for cutting Silicon-Oxide layer with precision

Doping the exposed Silicon

Is used for pattern formation of Polysilicon Growth of Silicon Oxide layer as insulator

Cutting of Silicon Oxide to form contacts

Patterned formation of metal layers sandwiched between insulatingSilicon Oxide layers


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Oxidation of Silicon is generally achieved by thermal oxidation of Silicon in

presence of water vapor

Si + 2H2O SiO2 + 2 H2

The thickness of Oxide is usually 0.020.2 m

Silicon Oxide Growth


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Silicone Oxide Growth


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Shaping Silicon Oxide

Monolithic technique requires selective opening of Silicon Oxidethough impurities may be diffused

Methodology:1. The wafer is uniformly coated with a photosensitive emulsion

2. Through Mask the emulsion is exposed to UV light, whichpolymerizes

3. The unexposed and non-polymerized portion is then removed withchemical such as trichloroethelene.

4. The wafer is immersed in HF acid solution which removes theexposed SiO2, not protected by polymer

5. A patterned SiO2 is created under the solidified polymer

6. The polymer is later removed using H2SO4by the mechanical

abrasion process7. This results in selective opening of Silicon Oxide


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Doping - Diffusion

Historically, impurities are diffused into uncovered silicon crystal bymeans of diffusion

The diffusion oven usually accommodates 20-30 wafers in quartztubes

The wafers are heated to 1000C for 1 to 2 hours

The temperature is carefully controlled for uniform diffusion

Gaseous impurities generally used are hydrides of boron, arsenicand phosphorus

An inert gas transports impurity atoms to the surface of the wafer


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Doping- Ion Implantation

Another method of introducing impurities

In a vacuum, a beam of appropriate ions (boron for p type and

phosphorus for n type) are accelerated by energies between 30 and

200 keV

Used mostly for doping thin layers Doping concentration is more controlled in this method


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Metalization

Metal lines are fabricated over man layers (typically 4 to 9)

Aluminum layer is deposited over entire surface of the wafer byhigh vacuum evaporation of aluminum inside a bell jar

Mask is used to define the connection pattern betweencomponents and unwanted aluminum is removed

SiO2is inserted as insulation between the layers Wafer is highly polished so that next level of metal can be grown

Via cuts are made from the top for cross metal layer connections


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Epitaxial Growth

Allows vertical growth of silicon crystal with desired impurity

Performed in a special furnace called rector into which the silicon

wafer in inserted and heated to 1000C (approx)

Gaseous Silane (SiH4) or Silicon tetrachloride (SiCl4) is used as a

source of Silicon Phospine (PH3) or diboron (B2H6) is used for doping

Technique can be used to grow successive layers of p and n types

with desired dopant concentration on top of one another


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Device Isolation

Innumerable devices are built on the surface of IC

Devices need to be isolated from one another

This can be achieved by defining active regions where the devices

are built

Silicon oxide layer is built on whole wafer and the active regions arecut for building devices

LOCOS (Local Oxidation of Silicon) is another technique used for

isolation


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Isolation LOCOS

Steps:1. Thin stress relief oxide is

grown on wafer

2. The wafer is coated withsilicon nitride

3. Using photolithography, nonactive regions are etched

4. p+ doping is done forchannel isolation

5. Wafer is oxidized

6. Silicon nitride and thin Silicon

oxide layer is removed toexpose the active area


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Cutting and Packaging

Cutting Wafer diced into ICs after fabrication

100 to 8000 ICs are cut from a singlewafer

Packaging Pins available on package

Parasitic Resistance, capacitances andinductance.

Thermal conductivity

Protection from alpha particles (satellite

applications)
http://images.google.com/imgres?imgurl=http://www.finishingassociates.com/site/images/IC.jpg&imgrefurl=http://www.finishingassociates.com/site/applicat.htm&h=184&w=236&sz=37&hl=en&start=11&tbnid=Qz_R_lKkGZna_M:&tbnh=85&tbnw=109&prev=/images%3Fq%3DIC%2Bwafer%26svnum%3D10%26hl%3Den%26lr%3D%26sa%3DGhttp://images.google.com/imgres?imgurl=http://www.fujitsu.com/img/PH/shinko/oem/prod_assembly_Water_Level_Package.jpg&imgrefurl=http://www.fujitsu.com/ph/services/oem/electronics/ic/&h=212&w=294&sz=35&hl=en&start=13&tbnid=Xpe4fRTCNk_HZM:&tbnh=83&tbnw=115&prev=/images%3Fq%3DIC%2Bwafer%26svnum%3D10%26hl%3Den%26lr%3D%26sa%3DG


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Cutting and Packaging (Contd.)

Package types: Dual in-line package

Most dominant

Low cost

High inductance

Max pins- 64

Pin Grid Array Innumerable pins

Better thermal conductivity

Chip Carrier package Direct mounting of IC on PCB

Large number of pins

Can cause thermal stress

Quad Flat Packs High pin count (upto 500)

Multi Chip Module Multiple ICs in package


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Nmos Fabrication

Si-substrate

Si-substrate

SiO2(Oxide)

Si-substrate

SiO2(Oxide)

Si-substrate

SiO2(Oxide)

Thin Oxide

Si-substrate

Si-substrate

Si-substrateSiO2(Oxide)

SiO2(Oxide)

Thin Oxide

SiO2(Oxide)

Thin Oxide

Polysilicon

Polysilicon

Polysilicon

Process flow for the fabrication of n-type MOSFET on p-type silicon

(a)

(b)

(c)

(d)

(e)

(f)

(g)


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Nmos Fabrication (Contd.)

n+ n+

Si-substrate

SiO2 (Oxide)

Polysilicon

Insulating Oxide

Si-substrate

n+ n+SiO2 (Oxide)

n+ n+SiO2 (Oxide)

Insulating Oxide

Si-substrate

n+ n+SiO2 (Oxide)

Metal (Al)

n+ n+

Si-substrate

SiO2 (Oxide)

Metal Contact

(h)

(i)

(j)

(k)

(l)

Process flow for the fabrication of n-type MOSFET on p-type silicon


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Cmos Fabrication

1. N-well (for p-mos fabrication)is opened and doped

2. Active areas (both n-mos andp-mos) are opened

3. Thin oxide for gate is grown

p-type substrate

n-well regionGate oxide

Sio2


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Cmos Fabrication (Contd.)

4. Poly layer is grown for

both n-mos and p-mos

n-well region

p-type substrate

Sio2

polysilicon


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5. p+ and n+ impurities are

ion implanted into silicon

6. n+ region in p-mos is

used for subratrate

contact is also diffused

n-well region

p-type substrate

polysilicon

Source and drain

region implants

n+ n+ n+p+ p+

Sio2


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7. Insulating silicon-oxide

layer is deposited over

entire wafer using CVD

(Chemical Vapor

Deposition) technique

8. Contact cuts are created

on silicon-oxide

p-type substrate

n-well region

n+n+n+ p+ p+

Sio2


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9. Metal layer (normally

aluminium) is drawn by

selective etching

p-type substrate

n-well region

p+ p+n+ n+ n+

Sio2

Metal Metal


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10. Insulation layer is placed

on the metal

11. Cutting via for metal to

metal contacts

12. Metal is polished so thatthe surface for next

metalization is smooth

p-type substrate

n-well region

p+ p+n+ n+ n+

Sio2

Metal Metal


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Other Devices

BJT


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Other Devices (Contd.)

Diode

Schottky diode

Resistance

Capacitance


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Summary

Today we have covered:

Methodology of IC fabrication


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Reference

A Review of IC Fabrication Technology: Dr. Lynn Fuller

CMOS Digital IC: Kang & Leblebici

Micro-electronics: Millman and Grabel

http://cc.ee.ntu.edu.tw

http://hyperphysics.phy-astr.gsu.edu http://www.siliconfareast.com/crystal.htm

http://www.fujitsu.com
http://cc.ee.ntu.edu.tw/http://hyperphysics.phy-astr.gsu.edu/http://www.siliconfareast.com/crystal.htmhttp://www.fujitsu.com/http://www.fujitsu.com/http://www.siliconfareast.com/crystal.htmhttp://hyperphysics.phy-astr.gsu.edu/http://hyperphysics.phy-astr.gsu.edu/http://hyperphysics.phy-astr.gsu.edu/http://cc.ee.ntu.edu.tw/


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Thank You


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Copyright 2006 Interra Systems India Pvt. Ltd.

Presentation ID: ISL-MOD1(H)PR1

Author: Saikat Bandyopadhyay

Reviewers: Saikat Bandyopadhyay, Reena Misra, and Partha Pratim DasVersion: 1.0

Release date:

01ic fabrication

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