© 2010 Benjamin Arthur Niemoeller

AN APPROACH TO CONTROLLING AN ACTIVE PARALLEL INTERFACE BETWEEN A TRANSIENT ENERGY SOURCE AND A

DC VOLTAGE BUS

BY

BENJAMIN ARTHUR NIEMOELLER

THESIS

Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering

in the Graduate College of the University of Illinois at Urbana-Champaign, 2010

Urbana, Illinois

Adviser: Professor Philip T. Krein

ii

ABSTRACT

This thesis investigates controlling a dc-dc converter connecting a capacitor or

ultracapacitor (UC) to a dc voltage bus by regulating the series impedance of the con-

verter. Decoupling the capacitance from the voltage bus is shown to reduce the size

and/or weight of the power source. The impedance of the dc-dc converter is shaped by a

high-pass filter so that it is low at high frequencies, but infinite at dc. This shaped-

impedance controller allows load current to be shared between the dc source and decoup-

led capacitor, even when the dc source is uncontrolled, as long as the dc source has non-

zero source impedance. Charge transfer to and from the capacitor is limited to a finite

value proportional to a step change in bus voltage.

The same control approach was applied to the converter which added decoupled

bus capacitance to an electric vehicle power source, where the dc source is a battery con-

nected directly to the output voltage bus, and to a voltage regulator module (VRM) for a

desktop computer processor. Design equations and small- and large-signal models are

developed in detail for the vehicle power source. A second loop was added to the control-

ler to help regulate UC charge level. Small-signal system stability is verified across the

range of expected operating points. Experimental results of a scaled-down combined

source verify theoretical predictions. For the VRM, a multiphase buck converter is aug-

mented by a second set of phases which carry only fast current transients. Large-signal

models and switch dissipation analyses predict that the proposed topology eliminates the

need for bulk electrolytic capacitors on the voltage bus yet has efficiency comparable to a

conventional multiphase VRM.

iii

To Parents and Family

iv

ACKNOWLEDGMENTS

I am grateful for the love, support, understanding, and motivation provided by

Mom, Dad, Grammy, Grandpa, Gramma and all of my extended family on this long and

arduous journey. It made all the difference in terms of going back to school and complet-

ing the degree. I want to thank Professor Philip T. Krein, my adviser, for giving me the

opportunity to conduct this research project. His timely wisdom and preternatural pa-

tience are deeply appreciated. I also thank Joyce Mast for writing assistance and Josh

McNattin and Kevin Colravy for assistance in ordering and finding parts. I would like to

thank Dr. Santanu Kapat for insights into converter control early in the research process.

Thanks also to Sammy Nammari for his assembly help and for his resourcefulness in the

lab. Last but not least, I want to thank Ed Nykaza at CERL for funding my first year of

grad school and for general encouragement along the way.

Work on this thesis was funded by the Grainger Center for Electric Machinery

and Electromechanics.

v

TABLE OF CONTENTS

CHAPTER 1 INTRODUCTION.................................................................................................1 1.1 Combined Battery and Ultracapacitor Source for a Vehicle .......................3 1.2 VRM with Unbalanced Phases ....................................................................8

CHAPTER 2 DESIGN AND IMPLEMENTATION CONSIDERATIONS .........................................13 2.1 Vehicle Application ...................................................................................13 2.2 VRM Application.......................................................................................33

CHAPTER 3 SMALL-SIGNAL MODELS ................................................................................41 3.1 Small-Signal System Model with Three-State Plant .................................42 3.2 Small-Signal Model with Two-State Plant ................................................63 3.3 Stability Check...........................................................................................74 3.4 Summary ....................................................................................................74

CHAPTER 4 LARGE-SIGNAL MODELS ................................................................................76 4.1 Switched Model for Vehicle System .........................................................76 4.2 Nonlinear Averaged Model for Vehicle System........................................83 4.3 Switched Model for VRM .........................................................................88

CHAPTER 5 EXPERIMENTAL RESULTS ...............................................................................95 5.1 Scaling the Design .....................................................................................95 5.2 Hardware and Setup...................................................................................97 5.3 Battery Resistance Measurement.............................................................100 5.4 Step Response ..........................................................................................101 5.5 Repeated Draw Test.................................................................................104 5.6 Summary ..................................................................................................109

CHAPTER 6 CONCLUSIONS ..............................................................................................110

APPENDIX A SCRIPTS TO EVALUATE SMALL-SIGNAL TRANSFER FUNCTIONS ...............112 A.1 Main Script...............................................................................................112 A.2 Scripts for Two-State Transfer Functions................................................113 A.3 Scripts for Three-State Transfer Functions..............................................116 A.4 Helper Functions......................................................................................119

APPENDIX B EXPANDED LARGE-SIGNAL SIMULINK BLOCKS AND SET-UP CODE ...........120 B.1 Switched Nonlinear Model for Vehicle ...................................................120 B.2 Averaged Nonlinear Model for Vehicle ..................................................125 B.3 Switched Model for VRM .......................................................................130

APPENDIX C SCHEMATICS FOR BIDIRECTIONAL PCM BOOST CONVERTER...................143

vi

REFERENCES .....................................................................................................................150

1

CHAPTER 1

INTRODUCTION

A theoretically ideal voltage source has no series (source) impedance; it can sup-

ply all possible demanded currents, at any slew rate, and the voltage across source (and

load) terminals will never change. Real dc power sources cannot do this. They have a

limit on current slew rate which causes source impedance to rise with frequency. In addi-

tion, practical dc power sources have a current magnitude limit, independent of the con-

verter’s source impedance, beyond which the source will sustain damage. Adding a ca-

pacitor in parallel with the dc source raises the current slew rate limit and will also allow

the combined source to deliver more current to the load for a period of time. When the

capacitor is tied to bus voltage, though, only a small fraction of the capacitor’s stored

energy is available to the load. Decoupling the capacitor voltage from the bus voltage

makes more of this energy available, reducing the needed capacitance value. The decoup-

ling is performed by a switching dc-dc power converter that allows current to flow

through it in both directions. This connection is shown in Figure 1.1 and is called an ac-

tive parallel connection. In this figure the dc source is represented by an ideal voltage

source ocV with series resistance thR . The combination capacitor and dc-dc converter is

termed a decoupled capacitor.

A control topology which regulates the source impedance of the dc-dc converter

is applied to the decoupled capacitor. The source impedance is commanded to be low at

higher frequencies and infinite at dc, injecting transient current into the bus but limiting

the charge that is transferred from the capacitor in response to a line or load step. The

controller will inject power to the bus so long as the dc source supports bus voltage and

2

has a nonzero source impedance. Because these requirements are general to practical dc

sources, this control topology can integrate a decoupled capacitor into a dc voltage bus

without regard to application.

Rth

voc

vc

vterm

iload

Load

dc-dc

converter

Dc Source

Decoupled Capacitor

Figure 1.1. Active parallel connection of the capacitor to the voltage bus.

Combined power sources for two applications are explored in this thesis: a power

source for an electric vehicle, where the dc source is an uncontrolled battery, and a com-

puter VRM, where the dc source is a dc-dc converter with controlled nonzero source im-

pedance. Very different requirements are imposed on the power sources for these applica-

tions, and at a glance the plant and controller topologies chosen look very different. What

these applications have in common, though, is a load with a large transient energy re-

quirement and a bus voltage that is constrained to change relatively little. Each applica-

3

tion benefits from a decoupled capacitor. The features of the controller which program

the series impedance of the decoupled capacitor are the same for both proposed systems,

though other features differ to meet application requirements.

Detailed design analyses for each plant and controller combination are performed.

Small-signal models of the combined source for the vehicle are derived to determine sys-

tem stability and gauge the controller’s effectiveness at rejecting low-frequency bus volt-

age disturbances. If left unchecked, these disturbances would deplete the capacitor.

Large-signal models are derived for both systems to verify that the system stays within its

voltage, current and energy bounds for a worst-case loading. A scaled-down version of

the combined source for the vehicle was constructed and tested. Measurements closely

matched those predicted by the large-signal models.

1.1 Combined Battery and Ultracapacitor Source for a Vehicle

Energy needed to make a vehicle move must be stored on board in some form.

While most vehicles obtain their energy from hydrocarbon fuels, all-electric vehicles run

on stored electricity. The two most widely used electrical storage devices are electro-

chemical cells and capacitors. A group of electrochemical cells is called a battery. Typi-

cally energy-dense batteries are needed to provide adequate energy storage [1] in an all-

electric vehicle. However, such a battery may not provide sufficient peak power [1]. One

solution, upsizing the battery, may be unacceptably large, heavy, and expensive. Rather,

one can use the fact that the peak transient power requirement of a light passenger vehicle

is typically several times higher than the steady-state power requirement [2]. A second

source which supplies just the transient power peaks can be added to the voltage bus.

This combined source may eventually weigh and cost less than a single battery sized to

4

meet all system requirements [1]. The system described in this thesis uses ultracapacitors

(UCs) to provide the transient energy storage. The UCs are decoupled from the bus volt-

age using a dc-dc converter, and the battery is connected directly to the voltage bus.

Some background on batteries and UCs is needed to explain the choice of sources.

Charge is transported to and from the battery by means of a reversible chemical reaction

[3]. In contrast, capacitor charge is stored physically in an electric field established be-

tween two conducting sheets of material. The charge stored in a physical storage device

is directly proportional to the device terminal voltage, related by the capacitance value in

Farads. When no charge is stored in the device, the terminal voltage drops to zero. An

ultracapacitor uses the double-layer effect [4],[5] to store physical charge more densely

than a capacitor can.

Because batteries use chemical storage, they store far more energy per unit weight

than UCs [6],[5]. Battery voltage does not drop to zero when the cells are considered de-

pleted, and changes relatively little with charge level [3]. These properties make a battery

a good choice to provide steady-state energy and to support bus voltage. However, the

chemical reaction is not 100% efficient, and the active materials in the cell degrade over

time [5]. For example, energy-dense LiCoO2, or lithium-ion, cells have an input-output

efficiency of 94% when new and an efficiency of 85% after several hundred full

charge/discharge cycles [7]. Other cell chemistries are worse [7]. In addition, high current

draws substantially reduce the input-output efficiency [8],[9], apparent cell capacity [10],

and cycle life [11] of a battery. This suggests that the battery should not be exposed to

large currents. As peak current in a vehicle is transient in nature [2], a second source

which injects transient power should shield the battery from the high current peaks.

5

Two candidates to provide this transient power are a second battery and an ultra-

capacitor. Batteries in general will last for more cycles when they are shallow-cycled, or

have only a fraction of their stored energy used each cycle [11]. Some power-dense

chemistries, when shallow-cycled, have a cycle life rivaling that of a UC [12]. Table 1.1

compares properties of a commercially available “nanophosphate” LiFePO4 cell, repre-

sentative of power-dense cell chemistries, with those of a commercially available UC.

Energy and power densities are calculated from parameters supplied by the manufacturer

of each cell [14],[15], with the assumption that the battery will be discharged 10% each

cycle (shallow-cycled) and the UC will be discharged 75% each cycle. The table shows

that the technologies are roughly comparable in all areas except one: power density when

the device is being charged. Here the UC is over an order of magnitude better. This is an

important difference, as current is expected to flow through the transient energy source in

both directions at equal magnitude. For this reason a UC is chosen over a shallow-cycled

battery to serve as the transient energy source. Table 1.1. Comparison of a power-dense shallow-cycled (10% depth-of-discharge) battery to a UC.

Parameter “Nanophosphate” LiFePO4 10% DoD

UC 75% DoD

Energy density (W-h/kg) 10.8 4.5 Power density, discharging (kW/kg) 3.6 5.9 Power density, charging (kW/kg) 0.46 5.9 Input-output efficiency 94% [13] 96% [16] to

98% [17] Cycle life (number of charge/discharge cycles)

240,000 [12] 500,000 [6][5] to 1,000,000 [15]

Calendar life at room temperature 10 years [12] 10 years [15]

Strategies to incorporate a transient energy source into a vehicle traction bus fall

into two main categories: those which tie the UC directly to the bus and those which tie

the battery to the bus. Methods which make UC voltage equal to bus voltage include us-

6

ing a UC as the sole energy source [18], selecting between the battery and UC depending

on load conditions [19], and bucking the battery down to bus voltage [20]. The bus volt-

age varies by 2:1 or more in these schemes; power delivery to the load will be compro-

mised. Of the schemes which tie the battery to the bus, most use a current-mode dc-dc

converter. There is disagreement on how to set the current command, because the dc-dc

converter must be controlled not just to provide power to the bus, but also to make sure

the capacitor charge level stays within acceptable bounds. These are competing control

objectives. When only bus voltage is regulated, the capacitor is quickly depleted [21].

One approach to resolve the problem is to regulate system power and energy directly

[21]–[23]. These schemes have good design flexibility, but the resulting controllers are

nonlinear and very complicated. It is difficult to analyze the complete system for stability

and performance, and detailed analyses were not attempted in the above works.

Drolia et al. [24] and Awerbuch and Sullivan [25] propose a linear topology

which maintains much of the flexibility of the power and energy controllers but is simpler

to analyze and implement. This scheme generates an error signal by measuring bus volt-

age and high-pass filtering the measurement. The reference current is the error signal

multiplied by a finite gain value pK . In addition, a second proportional loop is used to

drive the capacitor to some nominal charge level. Since the controller is linear and time-

invariant, the full system can be analyzed using linear analysis tools when the dc-dc con-

verter is linearized.

In the above controller, the loop from bus voltage to reference current directly

programs the series impedance of the decoupled capacitor. For a buck converter, series

impedance magnitude is the reciprocal of pK [25] within the passband of the high-pass

filter (HPF). For a boost converter, series impedance magnitude is the reciprocal of pK

7

scaled by the boost ratio ctermV V . The HPF in this path gives the converter infinite im-

pedance at dc. Viewed another way, the HPF blocks the dc portion of termv ; reference

current will eventually return to zero after a step change in termv , limiting the charge

transferred to or from the decoupled capacitor. The topology seems promising, yet it has

been explored little. It was abandoned by Awerbuch and Sullivan [25] in favor of a dif-

ferent scheme. Drolia et al. [24] outlined the controller’s structure and provided a single

time-domain simulation of system response to a load step but did not follow up with

more analysis or experimental results. Lastly, these authors only investigated controlling

a UC bucked down to the bus voltage, skipping boost converters and other plant topolo-

gies.

This thesis will use a shaped-impedance controller to control a decoupled UC that

is boosted to bus voltage. The exact controller topology is different from that used in ei-

ther [24] or [25] and is shown in Figure 1.2. The bus voltage measurement is low-pass

filtered to keep noise and voltage ripple out of the current command. The loop which

regulates UC charge level is placed in parallel with the first loop and an integrator is

added to it. The integrator improves rejection of very low-frequency disturbances and

supports the offset between reference current refi and average inductor current Li . This

offset is inherent to peak current mode (PCM) control [26] and must be addressed by any

outer loop control strategy. Because the controller does not regulate power directly,

power distribution between the sources must be calculated in the design stage. Design

equations and models are presented in Section 2.1. Chapter 3 develops linearized small-

signal models of the complete system. These models are used to find system response to

disturbances in the frequency domain. As the system has different dominant dynamics at

different frequencies, frequency-domain analysis is useful for visualizing system behav-

8

ior. Large-signal models are developed and simulated results are shown in Chapter 4.

Experimental results using scaled-down power sources are presented in Chapter 5. Large-

signal models verify the design equations, and the experimental results closely follow

large-signal predictions.

UC voltage

UC reference

Bus voltage

Kp-1HPF LPF iref

PI

Figure 1.2. Outer loop controller for electric vehicle application.

1.2 VRM with Unbalanced Phases

A voltage regulator module (VRM) is a dc-dc converter which regulates the proc-

essor bus voltage busv . Full VRM design specifications for present generation Intel desk-

top microprocessors are published in a technical report [27] written by the manufacturer.

These processors draw up to 150 A of current from the VRM, with 120 A transients at

frequencies up to 2 MHz [27]. The VRM is also required to drop the 12 V rail from the

computer’s main power supply to a voltage as low as 0.8 V [27]. VRM output voltage is

allowed to droop with load current, but must stay within 50 mV of the target load line

under all operating conditions [27]. This means that the VRM needs to have a constant,

but nonzero, source impedance at all frequencies.

Typical VRMs use multiple interleaved [28] buck phases feeding into a common

bus capacitor to supply current to the processor. The term phase in this context refers to

the inductor and switch pair portion of a power converter; one buck phase is shown in

9

Figure 1.3. A typical switching frequency is 300 kHz which yields a control bandwidth

(BW) of 30-40 kHz [27], above which the series impedance of the phases rises due to a

constrained current slew rate. An array of electrolytic and ceramic capacitors near the

processor chip is employed as a second energy source to supply currents outside the con-

verter’s control BW [27]. As the current demand of processors continues to increase, and

supply voltage regulation tightens ([27] compared to [29]), more and more energy storage

available from a source with lower and lower series impedance is needed to supply these

transients.

vin vbus

Figure 1.3. One converter phase.

Adding more bulk capacitors to the processor voltage bus is one way to meet

these requirements. This solution presents packaging challenges; in order to have a suffi-

ciently low series impedance, the capacitors must be located right next to the processor

socket. Another solution is to raise the VRM’s switching frequency in order to increase

its control BW and thus reduce the required bus capacitance. Simply raising the switching

frequency, however, increases commutation loss in the switches and thus reduces effi-

ciency [30]. A third alternative is to add another active power source to the processor

voltage bus to supply current at frequencies between that of the dc source and the capaci-

tor bank. This third source carries no dc current, and therefore carries less RMS current

than the dc-carrying converter phases. The lower current requirement makes it practical

for the third source to have a high control BW and thus reduce bus capacitance. Previous

10

attempts achieve the needed BW using switched resistors [31] or linear regulators [32] to

source and sink transient current. Dissipative devices such as these unnecessarily harm

efficiency, though, if switching devices and reactive (energy-storing) elements can be

used instead.

This thesis investigates using a decoupled capacitor as the third power source.

The decoupled bulk capacitor need not be independent of other energy sources, as it was

drawn in Figure 1.1; a bulk capacitor tied to a higher voltage, more loosely regulated rail

(voltage bus) will be used more efficiently than if it were tied to busv . It can also be lo-

cated further from the processor socket as its impedance is actively controlled. As the

main power supply for the computer is capable of supplying full power to the processor,

the input of the decoupled capacitor can be connected to the same voltage rail as the dc-

carrying VRM phases. This structure is shown in Figure 1.4 and resembles a multiphase

dc-dc converter, with one set of phases carrying net dc current and another set carrying

transient current only. Section 2.2.2 shows that, through prudent choice of components

and system parameters, a VRM with fast transient-carrying phases can have substantially

less bus capacitance than, but comparable efficiency to, a typical multiphase VRM.

Cdecoup

5 mΩ

vin vbusC

Resr

transient-

carrying

phases

dc-

carrying

phases

Figure 1.4. VRM with transient-carrying phases in parallel with the dc-carrying phases.

Mossoba and Krein [33] previously modeled a VRM with a structure similar to

Figure 1.4, except a single transient-carrying phase was used. The fast transient-carrying

11

phase was controlled using sensorless current mode (SCM) control described in [34],

while the slow dc-carrying phases used PCM control. While a single phase was adequate

for processor loads in the past, multiple transient-carrying phases are needed to supply

today’s processors. Series input SCM phases share current [35] but there is no inherent

sharing between SCM-controlled phases when the inputs are in parallel. Thus the topol-

ogy studied in this thesis uses PCM control for all phases.

The current command for each phase is generated by the outer loop controller

shown in Figure 1.5. Filters split the current command cmdi by frequency, sending a high-

passed cmdi to the transient-carrying phases and a low-passed cmdi to the dc-carrying

phases. One Offset correction block makes the average of the sum of the current through

each transient-carrying phase track ,cmd fi , while the other performs an analogous function

for the dc-carrying phases. The particular correction scheme used was developed by

Huang et al. [36] and is called Native AVP in their paper. Since the decoupled capacitor

decoupC in Figure 1.4 obtains net energy from the input voltage inv , the outer loop control-

ler is not responsible for maintaining the charge level of this capacitor. The controller is

discussed in more detail in Section 2.2.1. Large-signal models and simulated results of

the proposed VRM and controller are given in Section 4.3. Simulation results show that

the converter is well within voltage tolerance limits specified in [27] when subjected to

substantial line, load and reference steps.

12

Referencevoltage

Bus voltage

Kf

HPF

LPF

iref,f

iref,s

∑iL,s

icmd

icmd,f

icmd,s

∑iL,f

Offsetcorrection

Offsetcorrection

1N

1M

to M transient-carrying phases

to N dc-carrying phases

Figure 1.5. Outer loop controller for VRM application.

For the overall thesis, Chapter 6 contains conclusions and ideas for future work.

Expanded block diagrams for the Simulink models, MATLAB code, and schematics for

the prototype converter are listed in the appendices. References to a label within a block

diagram or figure, such as Offset correction in Figure 1.5, are denoted with a sans-serif

font.

13

CHAPTER 2

DESIGN AND IMPLEMENTATION CONSIDERATIONS

This chapter discusses the plant and controller topologies in depth for each appli-

cation. Both applications use a current-mode dc-dc converter to decouple a capacitor or

UC from a voltage bus. The current command is set using high-pass filtered feedback of

bus voltage. Other sections of each controller modify the current command to meet plant

constraints or application requirements. Design equations for preliminary controller tun-

ing and part selection are presented.

2.1 Vehicle Application

Figure 2.1 is a detailed version of Figure 1.1, showing the combined power source

with its controller. Power-handling elements are in the dashed box marked Plant. The

battery is modeled by the voltage source ocv in series with resistance battR . Ultracapacitor

ucC is decoupled from the bus via a boost converter. Exact reasons for choosing a boost

topology over a buck are given in Section 2.1.1.

The Controller block includes the outer loop controller described in Figure 1.2

along with a comparator and S-R latch to implement PCM control. As inductor current Li

is fed back through the comparator, the portion of the controller between refi and the

switch pair , 'q q is called the PCM inner loop, inner current loop, or else just inner

loop. Blocks between input termv and refi compose the power-distributing loop which sets

the series impedance of the decoupled capacitor and thus influences how load power is

divided between the battery and UC. The PI controller and reference input ,uc refv between

inv and refi make up the charging loop, which is responsible for rejecting low-frequency

14

variations in termv and losses which would otherwise drain the UC. Lowercase variables

in Figure 2.1 are instantaneous quantities. The quantity outi is equal to the current through

the top FET averaged over one switching cycle [37]. Other lowercase variables in this

thesis with overhead bars represent that quantity averaged over one switching cycle.

vocLoad

Rbatt

ibatt

iL

iL

load i

iciout

LC

vin

vin

vuc,ref

vterm

vterm

QS

R Q

Kp-1HPF LPF

ramp

clock

iref

PI

Cuc

Controller

Plant

Figure 2.1. Active-parallel interface for the vehicle application.

The plant in Figure 2.1 presents several challenges for the controller to address.

The first challenge is that the plant provides no means to directly control the battery cur-

rent batti . Instead, current flow is determined passively by the value of battR and the dif-

ference between ocv and termv . The power-distributing loop commands the dc-dc con-

verter to inject current into the dc bus in response to a change in termv , with the balance of

the load current drawn from the battery. It is desired to transform knowledge of the im-

15

pedance of each source into an estimate of how power is apportioned between the sources

at any point in time. This estimate is needed to choose controller gains which keep batti

below its limit in response to a particular loading, and also to determine the power and

energy demanded from the UC bank. Equations and a Simulink model which perform this

estimate are discussed in Section 2.1.2.

The second challenge is that UC is an independent source. The dc-dc converter

must be controlled to keep the UC from becoming depleted or overcharged in the face of

UC loss, converter loss, and low-frequency variations in inv that are not completely re-

jected by the HPF. The charging loop addresses this problem, and its topology is intro-

duced in Section 2.1.3.

The third challenge is that the relatively large gain pK can cause refi to slew

faster than Li is capable of slewing. This will make the plant states overshoot their in-

tended targets, and can make the converter oscillate in extreme cases. The problem is

exacerbated in a boost converter. Section 2.1.4 analyzes two methods which guarantee

that refi will not slew faster than Li , and chooses the method appropriate for this system.

With the loops defined as such, the outer loop controller is attempting to regulate

two plant states (bus voltage termv and UC voltage inv ) using only one control input (the

switch pair , 'q q in Figure 2.1, transformed to reference current refi by the PCM inner

loop). While control of both states is possible because the two states are coupled via the

inductor, the control input cannot raise one state without driving the other state lower in

turn. Thus the power-distributing and charging loops will necessarily fight one another;

simply cranking up the gains of both will not improve regulation. The solution is to make

the power-distributing and charging loops dominant over different frequency ranges. As

the power-distributing loop must be tuned to balance battery power against UC energy,

16

the charging loop is tuned to not interfere with the power-distributing loop. This is dis-

cussed in more detail in Section 2.1.3 and in Chapter 3.

The significant power-handling components are sized in Section 2.1.5.

2.1.1 Boost vs. Buck Topology

In Figure 2.1 the UC voltage is boosted up to bus voltage. Why is a boost topol-

ogy chosen instead of a buck? For a vehicle application both ultracapacitors and batteries

have a cell voltage that is two orders of magnitude below what is needed for a traction

system. Making the cell size larger increases energy capacity and current capability but

not the potential across its terminals, as this voltage is intrinsic to the cell chemistry [3].

The only way to raise terminal voltage is to string cells together in series. As large-format

batteries and ultracapacitors mature, their cost per watt-hour and kW drop below that of

smaller cells. In future applications it will be more cost-effective to meet a power and

energy requirement with fewer large cells (boost) than with many smaller cells (buck);

therefore, a boost topology is studied.

One disadvantage to using the boost is that the PCM process regulates converter

input current, instead of output current as is the case with a buck. For a fixed pK the

converter’s source impedance (in the filter passband) will be the reciprocal of ' pD K ,

where 'D is one minus the steady-state switch duty ratio. So long as the converter’s

source impedance is much less than battR over the frequency band where the UC is ex-

pected to supply current, this variation will have little effect on power division. The boost

topology allows UC current to be controlled directly, which makes regulating its charge

level more straightforward.

17

2.1.2 Power and Energy Apportioning between Dc and Second Sources

An examination of how the power magnitude is divided between the sources is

motivated by the fact that a battery sized to meet a long-term energy requirement may not

be capable of supplying the peak load power by itself. Consider an electric vehicle with

the following traction power requirement:

1) Peak power: 100 kW for 10 seconds, both directions

2) Average power: 25 kW long-term

3) Load slew: zero to peak power in 0.2 s, peak to peak power in 0.4 s

4) 400 V nominal traction bus [38]

5) 59 kWh energy requirement for acceptable range

To minimize loss, the battery pack (henceforth called the battery) is connected directly to

the voltage bus. The 59 kWh energy requirement and 400 V nominal bus voltage trans-

lates to a battery with a charge capacity of 147 A-h. A battery consisting of 67 strings of

100 lithium-ion cells, each size 18650, will meet these requirements. Datasheets [10],[39]

for commercial lithium-ion cells suggest that charging and discharging rates should be

limited to no higher than one times the A-h rating of the battery, or 147 A. As the battery

discharges, its open-circuit terminal voltage drops. If the battery is considered fully dis-

charged when its open-circuit voltage reaches 340 V, then the worst-case power the bat-

tery can provide to the bus without exceeding 1 C discharge rate is 50 kW. Using the

datasheets and [40] the battery resistance is estimated to be 0.15 Ω at low frequencies.

Looking at Figure 2.1, the HPF and gain pK determine how load power is divided

between the battery and ultracapacitor. To better see this relationship, first define battery

power as battp , second source power as ucp , and load power as loadp . Load power is al-

ways equal to the sum of battp and ucp . For convenience, losses will be neglected from

18

the second source and power converter, and battp will be defined as power available from

the battery. Powers battp and loadp can be split into dc and ac portions, in anticipation of

establishing a relationship in the Laplace domain (where the dc values of variables are

ignored). The following relationships are defined:

, , , ,

, ,

,

ˆ

batt batt dc batt ac load load dc load ac

batt ac term batt ac

oc termbatt ac

bat

c in L

t

u

p p p p p p

p v i

v vi

R

p v i

(2.1)

Next, the ac powers and currents (including ucp , which has no dc component when losses

are excluded) are placed into the Laplace domain. In the Laplace domain, the term ˆocv is

zero, and so the relationships are

, ,

,

( ) ( ) ( )

( )( )

( ) ( ) ( )

batt ac term batt ac

termbatt ac

batt

uc i Ln

P s V s I s

V sI s

R

P s V s I s

(2.2)

As the second source and power converter are assumed to have no loss, the following

relationship holds:

in term o tL uv i v i (2.3)

The expression in the Laplace domain is

( ) ( ) ( ) ( )in tL erm outV s I s V s I s . (2.4)

A block diagram of the HPF used in the feedback path (HPF block in Figure 2.1)

is presented in Figure 2.2. The expression for this HPF in the Laplace domain is

19

High Pass Filter

Low Pass Filter

Out1

2

Out

1

Integrator1

1s

Integrator

1s

Gain1

1

Gain

1

In1

2

In

1

τ1

τ2

Figure 2.2. High-pass and low-pass filter prototypes.

1

1

( )1

sHPF s

s

. (2.5)

Further assuming that Lrefi I , the expression for the termV -to- LI control loop is

1

1

( ) 1 ( )1pL term

sI s K V s

s

. (2.6)

Next, define parameter K as

in batt

termp

v RK K

v . (2.7)

The relationship is the same in the Laplace domain:

( )

( )in batt

termp

V s RK K

V s . (2.8)

Multiplying both sides of (2.6) by ( )inV s and substituting in (2.4) and the middle line of

(2.2) gives

20

1

1,( ) ( ) ( ) ( ) 1 ( ) ( )

1in term out p in battL ac batt

sV s I s V s I s K V s I s R

s

,

1

1

( ) ( )

( ) ( ) 1out term

pbatt ac in batt

I s V s sK

I s V s R s

. (2.9)

Further substitution and simplification yields

, ,

( ) ( )

( ) ( )uc out

batt ac batt ac

P s I s

P s I s

1

1,

( )

( ) 1uc

batt ac

P s sK

P s s

. (2.10)

With losses neglected and , ( )batt acP s defined as in (2.2),

, ,load dc batt dcp p (2.11)

and

, ,

1

1,

( ) ( ) ( )

1 ( )1

load ac uc batt ac

batt ac

P s P s P s

sK P s

s

. (2.12)

The transfer function relating , ( )batt acP s to , ( )load acP s is

1

1 1

1

1

,

1

,

1

( ) 11

( ) 1 111

11 11 1 1 1

1 1

1 1 1

batt ac

load ac

P s sKsP s s K

s

s K

Ks K s K

s

s K s

(2.13)

where

11K . (2.14)

21

Likewise,

,

( )

( ) 1 1uc

load ac

P s K s

P s K s

. (2.15)

Equations (2.13) and (2.15) demonstrate how load power is apportioned to the dc and

second sources, respectively. The dc source sees the dc and low-passed portions of loadp

(per equation (2.11)), plus a portion of the high-passed portion of loadp . The second

source sees the remainder of the high-passed portion of loadp . The parameter K deter-

mines how the high-passed portion of the signal is divided between the dc and second

sources, while parameter determines the location of the frequency corner. Tuning of K

and may be done by creating a stateful model (time-domain model with state variables)

based on (2.11), (2.13) and (2.15) in a numeric simulation program and viewing the re-

sponse of ( )battp t and ( )ucp t to ( )loadp t . Figure 2.3 shows this model created in Simulink.

HPF'dPload

filter time constant

1/tau

To Workspace2

uc_energy

Puc(t)

uc_power

Pload(t)

roadpower

Pbatt(t)

batt_power

Integrator1

1s

Integrator

1s

Gain1

1/(K+1)

Gain

K/(K+1)

Figure 2.3. Simulink model to determine dynamic power and energy distribution between the battery

and ultracapacitor.

A load power waveform which will put maximum transient and steady-state

stresses on the combined source is a pulse train with 100 kW magnitude, 40 s period, and

25% duty cycle. This waveform draws full load power from the combined source for 10

22

seconds, followed by no power for 30 seconds, resulting in an average draw of 25 kW.

Figure 2.4 shows this waveform and its Fourier series expansion. Power splitting is found

by loading this waveform into the Pload(t) block in Figure 2.3 and running the simulation

for various values of K and . The Integrator blocks in Figure 2.3 have an initial condi-

tion of zero, representing a condition where neither source is transferring power.

0 20 40 60 80 100 120

0

2

4

6

8

10

x 104

Time (s)

Pow

er (

W)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4-2

0

2

4

6x 10

4

Frequency (Hz)

Pow

er (

W)

Figure 2.4. (Top) Pulse train with 100 kW peak power and 25 kW average power. (Bottom) Fourier

series expansion of this waveform.

Three combinations of K and which keep battery power just under 50 kW are

listed in Table 2.1 along with resulting peak UC power and energy draw. Figure 2.5

draws battery power, UC power and UC energy as functions of time. The solid lines in

Figure 2.5 are the simulation output for the 100 kW pulse train input. The trend here is

that the energy drawn from the UC rises as is decreased, even while peak UC power

and K grow larger. To see why this happens, the simulation was run again with zero ini-

tial condition with Pload(t) replaced by a 25 kW step. The dashed lines in Figure 2.5

show the result. Figure 2.6 (on page 24) compares the UC power and energy response for

23

each K and more clearly. With 70 the energy drawn in response to the 25 kW step

is over twice what is drawn when is smaller. Although peak UC power is less due to

smaller K, the larger makes the filter take longer to drive UC power to zero and thus

significantly increases the area under the power curve. Figures 2.5 and 2.6 show that an

HPF alone is enough to limit net UC charge transfer when a load step is applied.

Table 2.1. Component power and energy for three combinations of K and τ. τ K Peak Battery Power Peak UC Power Peak UC Energy

70 2.8 48.8 kW 72.8 kW 1570 kJ 25 6.5 48.9 kW 83.6 kW 890 kJ 20 15 48.7 kW 89.7 kW 849 kJ

0 100 200 300 400 5000

10

20

30

40

50

Bat

tery

Pow

er (

kW)

0 100 200 300 400 500-50

0

50

100

UC

Pow

er (

kW)

= 70 K = 2.8

0 100 200 300 400 5000

500

1000

1500

UC

Ene

rgy

(kJ)

0 100 200 300 400 5000

10

20

30

40

50

Bat

tery

Pow

er (

kW)

0 100 200 300 400 500-50

0

50

100

UC

Pow

er (

kW)

= 25 K = 6.5

0 100 200 300 400 5000

500

1000

1500

UC

Ene

rgy

(kJ)

0 100 200 300 400 5000

10

20

30

40

50

Time (sec)

Bat

tery

Pow

er (

kW)

0 100 200 300 400 500-50

0

50

100

Time (sec)

UC

Pow

er (

kW)

= 20 K = 15

0 100 200 300 400 5000

500

1000

1500

Time (sec)

UC

Ene

rgy

(kJ)

100 kW 10s pulsed

Constant 25 kW

Figure 2.5. Simulation output for 100 kW pulse train and 25 kW step inputs.

24

0 100 200 300 400 5000

5

10

15

20

25

UC

Pow

er (

kW)

0 100 200 300 400 5000

500

1000

1500

UC

Ene

rgy

(kJ)

Time (s)

= 70, K = 2.8

= 25, K = 6.5

= 20, K = 15

Figure 2.6. UC power and energy response to 25 kW step for various K and τ.

2.1.3 Charging Loop

In Section 2.1.2, it was shown that the HPF prevents UC energy from exceeding

a certain threshold in response to a load step. The threshold is directly proportional to the

step magnitude; if the peak step is known, the energy can be calculated and the UC sized

to supply it. In practice, losses and ultracapacitor leakage current will consume net en-

ergy, and the controller may be reset (e.g., by the operator turning off the device) before

the power storage system reaches an equilibrium value. Some compensation is needed to

ensure the ultracapacitor does not become over- or undercharged as a result of these dis-

turbances. A feedback path from inv to refi provides this compensation and is termed the

charging loop.

The charging loop uses a proportional-integral (PI) controller to bring inv up to

(or down to) a reference level ,uc refv by manipulating refi . In steady state, refi is related to

25

Li by a dc offset. Due to the boost topology, Li has the same magnitude and opposite sign

as UC current uci . As discussed in the introduction to Section 2.1, the charging loop

needs to have low gain at frequencies where the power-distributing loop has high gain,

and may have high gain at frequencies below this. The controller discriminates between

legitimate load transients and line disturbances (or net power losses) by frequency, reject-

ing only the very long-term disturbances to inv which will drain or overcharge the UC.

A block diagram of just the second source (an ultracapacitor in this case) and the

charge controller is shown in Figure 2.7. This figure uses the assumption that Lrefi i ,

valid when the dc offset is small. The transfer function from reference ,uc refv to output inv

in the Laplace domain is

,

2

( )

( )chg ichgin

uc ref uc chg ichg

sK Kv s

v s s C sK K

. (2.16)

This equation provides a starting point for setting controller gains chgK and ichgK . Good

candidate values of chgK and ichgK will make the poles of (2.16) well-damped and give

(2.16) little gain at frequencies at and above 1 . The variable is the coefficient for the

power-apportioning filter discussed in Section 2.1.2; frequency 1 will be several times

lower than HPF angular corner frequency 11/ . Small-signal transfer functions which

relate inv to load and battery disturbances are derived in Chapter 3.

26

Charging Controller Ultracapacitor

~ i_L v_in

1

Kichg

Kichg

Kchg

Kchg

Integrator

1s

Int

1s

Gain

-1/Cuc

v_uc,ref

1i_ref v_in

Figure 2.7. Block diagram of feedback loop containing ultracapacitor and charge controller.

2.1.4 Limiting iref Slew

PCM control commands a state variable, ( )Li t , to follow a signal, ( )refi t , gener-

ated from two other state variables, termv and inv , each switching cycle. As state variables

in general represent energy stored in a device or circuit element, they may not change

value, or slew, arbitrarily quickly. When refi slews faster than Li , both Li and termv tend

to overshoot their target values, causing device stress. In extreme cases the power con-

verter can oscillate, a condition which may destroy the converter or devices connected to

it. Therefore it is desired to find ways to make sure refi cannot slew faster than Li .

The inductor current ( )Li t in a switching power converter is often analyzed by

separating it into a “ripple” portion Li plus a “fast averaged” portion Li [37]. The fast

averaged portion is the current transferred to the dc bus. A dc-dc converter is said to be

boosting when Li is flowing from a lower-voltage node to a higher-voltage node and

bucking when the opposite occurs. Looking at the power-handling components of Figure

2.1, the switching converter in this diagram is boosting when 0Li and is bucking when

0Li .

27

Practical boost converters have a hard duty ratio limit programmed into the device

which generates the switching signal [41]. As a consequence, if Li is positive and needs

to increase further (due to an increase in refi ), the rate at which it may increase is consid-

erably less than the positive-going slope of the inductor current ( )Li t when the active

switch is on. Figure 2.8 shows trajectories of ( )Li t at some operating point , in termV V .

The inductor current slopes are

21in c termV V V

m mL L

(2.17)

using the nomenclature from Figure 2.1. The solid line shows inductor current for the

case when (0) ( )L Li i T . The active switch turns off at time DT, where D is defined as

1 in

term

VD

V . (2.18)

-m2

-m2

m1

m1

iL(t)

ΔIL

0 TDT dmaxT t

Figure 2.8. Trajectory of iL(t) at an operating point (Vin,Vterm) in steady state (solid line) and at

maximum duty ratio (dashed line).

28

The dashed line is the current trajectory under the same operating condition, except the

active switch is turned off at time maxd T , where maxd is the maximum duty ratio of the

boost converter. Over the course of one switching cycle, the net change in inductor cur-

rent is

1 2

( ) (0)

1max max

L L LI i T i

m d T m d T

. (2.19)

Substituting (2.17) into (2.19) gives

1in max terL m

TI V d V

L .

Finally, substituting (2.18) for inV gives

term ma

LxV d D T

IL

. (2.20)

The peak slew rate of Li at operating point ,in termV V is just

L term mL

LaxV d DI I

it T L

. (2.21)

Notice that as D approaches maxd , the peak positive slew on Li rapidly shrinks.

This has two implications for the converter design:

1) The largest steady-state D should be kept well away from maxd . For a maxd of

0.85, D should be no higher than 0.6 or 0.65 for a practical system. This corre-

sponds to a boost ratio no higher than 2 or 2.5:1 once losses are accounted for.

2) Attention needs to be paid to refi so that the slew rate of refi should not exceed the

slew rate of Li at worst-case D.

On fast time scales, the slew rate of refi is the slew rate of termV multiplied by gain

pK . One way to limit refi slew rate is to size the bus capacitor so that termV changes suffi-

29

ciently slowly. Here the bus capacitor provides energy to the bus, so there are now three

sources on the bus which provide significant energy to the load, and is appropriate when

the load current’s slew rate exceeds the maximum possible slew rate of the decoupled

capacitor. Another method is to tune the low-pass filter LPF in Figure 2.1 to slow the

slew rate of refi . This method is appropriate when the load current’s slew rate is less than

that of the decoupled capacitor. Here the bus capacitor does not provide appreciable en-

ergy to the load, and so only needs to be sized to meet the bus voltage ripple requirement.

Equations which give an estimate of capacitance C or low-pass filter (LPF) coefficient 2

are presented next.

The required bus capacitance C is estimated by looking at capacitor current just

after a load transient occurs. When the converter is in steady state, the fast average of the

capacitor current is zero. Suppose a step change in load current

,0

loadload

c

PI

V

(2.22)

is applied, where ,0c

V represents fast-averaged capacitor voltage just before the step is

applied. At time 0t , just after the step is applied, the capacitor current is equal to

loadI since no other source has yet adjusted its current delivery. The fast average slew

rate of cV at this time is

0

0

slew cc

loaddV IV

dt C

. (2.23)

Next, cV slew is related to refi slew by the constant parameter pK . It is desired to con-

strain refi slew to be less than or equal to that of LI slew. Plugging (2.21) and (2.22) into

(2.23) produces

2

,0

load

a c

p

m x

P K LC

d D V

. (2.24)

30

This capacitance value guarantees that Li slew will not exceed the value given in (2.21)

for a load step loadP . Setting D, loadP and ,0c

V to their worst-case values produces a C

that will enforce (2.21) under all operating conditions. When using a large bus capacitor,

coefficient 2 should be set to a small value. This allows the LPF to filter out switching

noise but not degrade transient response of refi .

To set the LPF coefficient, a few assumptions must be made:

1) The bus capacitor is small enough that a step change in load current very nearly

produces a step change in termV .

2) The dc source is capable of supplying power at high frequencies. A battery fits

this description, although drawing high currents will deplete the cell’s energy [40]

and shorten its cycle life [11].

3) The system is in steady state just before the transient is applied, and thus at time

0t load current is equal to battery current.

Using the first assumption, at time 0t the battery is again supplying virtually all the

load current, as the inductor has not yet had time to respond. Thus load battI I and

,0

loadterm batt load batt

c

PV R I R

V

(2.25)

assuming ,0term c

V V . A prototype of the first-order LPF was given in Figure 2.2. Fol-

lowing the termV -to- refi feedback path in Figure 2.1, the step change incident on the LPF

integrator at time 0 is

,2 0

loadbat

pt

c

K PR

V

. (2.26)

The output of the integrator sets refi ; thus the slope of refi at time 0t is the expression

given in (2.26). Setting (2.26) less than or equal to (2.21) and solving for 2 yields

31

,

2 2

0

load batt

max c

pP K R L

d D V

. (2.27)

Notice that pK appears in the numerator of both (2.24) and (2.27). If pK is very

large, refi slew will only be held less than Li slew if the converter has either a very large

bus capacitor or else a small control bandwidth. These factors need to be traded off

against the desired UC energy storage and power apportioning when selecting pK .

2.1.5 Choosing the Power-Handling Components

The inductor L, bus capacitor C, and UC ucC are sized in this section, and

switches are chosen. The inductor needs to be large enough to keep current ripple reason-

able, but small enough to allow its current (and UC current) to slew quickly enough to

meet load requirements. Bus capacitor size is set according to the required bus voltage

ripple. As the battery is connected directly to the bus, the voltage ripple requirement is

determined by the current ripple the battery can tolerate. The UC bank is sized for energy

and voltage requirements.

The current slew rate requirement places a maximum value on inductor L. Output

current from the converter must slew from 0 to 250 A in 0.2 s. This means Li must slew

625 A in 0.2 s when steady-state duty ratio is 0.6. A switching frequency of 10 kHz

means that Li has 2000 cycles to move 625 A, or 0.31 A per cycle. The linear outer loop

controller will make Li follow either a decaying exponential or a damped second-order

trajectory. Thus, Li may slew at up to 0.62 A per cycle, or twice the above prediction.

With cV = 400 V, D = 0.6, and maxd = 0.85, rearranging (2.20) gives a maximum permis-

sible inductance value of 16.1 mH. A 500 µH inductor is chosen, which will yield an

acceptable 20 A steady-state ripple current and good current slew rate.

32

As inductor current can slew fast enough to meet load requirements, the bus ca-

pacitor does not need to provide energy to the load and so is chosen to meet the voltage

ripple requirement. The voltage ripple is set by the battery current ripple requirement. For

the 400 V, 147 A-h battery with battR = 0.15 Ω, a voltage ripple of 3.82 V limits RMS

current ripple to 10% of battery A-h capacity. At peak load this voltage ripple require-

ment is met by an 8000 µF capacitor with an equivalent series resistance (ESR) of 3.1

mΩ. Because a boost topology is used, the bus capacitor will need to supply load current

during the time the active switch is off, and absorb the difference between inductor cur-

rent and load current when the switch is on. Eighteen 1000 µF, 450 V electrolytic capaci-

tors are needed in order to reliable source and sink these large currents each switching

cycle [42]. The capacitance bank has an ESR of about 3.14 mΩ [42]; it will meet the

voltage ripple requirement.

Insulated-gate bipolar transistors (IGBTs) are selected for switches q and 'q be-

cause these devices will block the 400 V bus voltage. Both switches must be transistors in

order to allow current to flow in both directions between the UC and dc bus. The typical

on-state voltage drop of an IGBT is 2 V, or 0.5% of bus voltage. This is small enough to

be neglected from the dynamic models. Switch loss will be modeled by a small series

resistance. A 10 kHz switching frequency is an appropriate choice for IGBTs with the

required voltage and current rating.

The maximum and minimum UC voltages are chosen to be 320 and 180 V, re-

spectively, to allow for duty ratio headroom. This allows 68% of the stored UC energy to

be accessed, compared to less than 10% when the UCs are passively connected to the

bus. The UC reference voltage is chosen to correspond to 55% [43] of the usable UC

charge capacity, or 266 V. Considerations from Section 2.1.2, combined with modeling

33

to be described in the next two chapters, yield a pK of 65 and 1 of 3.71. With these pa-

rameters the UC must provide 859 kJ of energy as it discharges from 266 to 180 V. The

capacitance needed to make this happen is

2 21

2

859 kJ44.16 F

266 180ucC

. (2.28)

Two strings of 119 large ultracapacitors, each rated for 2.7 V and 3000 F, are needed to

meet this capacitance requirement. This is a physically large UC bank but still several

times smaller than what would be required if the UCs were connected directly to bus

voltage. The importance of decoupling UC voltage from bus voltage is made evident

here.

2.2 VRM Application

In Section 2.2.1 the plant and controller for the three-source VRM are described

in detail. The outer loop controller is shown to make the source impedance of the two

active sources constant over their combined control BW. In Section 2.2.2 power-handling

components for a three-source converter are chosen and compared to those used for a

typical VRM design. Required bus capacitance and power loss are calculated for both

designs and compared.

2.2.1 Plant and Controller in Detail

Figure 2.9 (on page 35) shows the VRM plant and controller in detail. The input

voltage rail is modeled by the voltage source inv with series resistance srcR . The N dc-

carrying phases have a relatively low switching frequency, a larger inductor bigL and are

programmed by the current reference ,ref si . The M transient-carrying phases have a high

34

switching frequency, a small inductor smallL and are programmed by ,ref fi . All phases

feed into a common bus capacitor C. The slow clock signals are N-way interleaved, while

the fast clock signals are M-way interleaved independently of the slow clock. The com-

parator and S-R latch in the PCM & PWM block are applied to each phase, and implement

PCM control of each switch pair. Since there are only two reference currents, an offset

correction block is used for each set of phases, rather than for each individual phase. The

offset correction acts to slowly vary an offset between ,cmd ji and ,ref ji using fed-back cur-

rent information; at high frequencies the block behaves like a constant additive term, pre-

serving the good dynamic performance of PCM.

The entire VRM, with all sources combined, needs to take on a constant nonzero

output impedance [27]. Ideally the VRM will behave like a voltage source refv in series

with a resistance thR , and busv will droop with load current. A drooping bus voltage is

straightforward to implement with PCM-controlled phases; the outer voltage loop simply

needs to have a fixed finite gain and compensated so that the voltage loop programs aver-

age current instead of peak current. In Figure 2.9, gain fK is the reciprocal of thR so

long as the average current through all phases tracks cmdi .

Representing the currents in the Laplace domain,

,

,

1( ) ( )

1

( ) ( )1

cmd s cmd

cmd f cmd

i s i ss

si s i s

s

(2.29)

where

( ) ( ) ( )f bucmd rs efi s K v s v s (2.30)

35

vin

Load

Rsrc

iL,s1iL,s1

iloadLbig

C

qs1(t)

1-qs1(t)

vref

vbus

Resr

vbus

iref,f

iref,f

iref,s

iref,s

PCM &

PWM

iL,sN

Lbig

qsN(t)

1-qsN(t)

iL,f1

Lsmall

qf1(t)

1-qf1(t)

iL,fM

Lsmall

qfM(t)

1-qfM(t)

slow clock

iL,sN

PCM &

PWM

slow clock

iL,f1

PCM &

PWM

fast clock

iL,fM

PCM &

PWM

fast clock

iL

q(t)QS

R Q

ramp

clock

iref

PCM & PWM Block

Outer Loop Controller

Kf

HPF

LPF

iref,f

iref,s

∑iL,s

icmd

icmd,f

icmd,s

∑iL,f

Offsetcorrection

Offsetcorrection

1N

1M

Figure 2.9. Topology of proposed VRM with M transient-carrying and N dc-carrying phases.

36

and is the coefficient for the high-pass and low-pass filters. For small ripple current the

approximations

,

1

,

,

1,

( ) ( )

( ) ( )

N

cmd sL sp

L fq

p

M

cmd fq

i s i s

i s i s

(2.31)

hold for 0s , and the approximation is an equality when 0s . Using (2.29) and (2.31)

the sum of the current through all phases is

1

, ,1

1( ) ( ) ( )

1 1

N M

cmdp q

L sp L fq

si s i s i s

s s

1

( ) ( )1 cmd cmd

si s i s

s

.

Thus in the time domain

cL mdi i (2.32)

within the control bandwidth spanned by both the slow and fast phases. Substituting

(2.30) into (2.32) and transforming back into the time domain gives the equivalent source

resistance

1bus ref

L fth

v vR

i K

. (2.33)

The outer loop controller should keep thR nearly constant across the control bandwidth of

both the fast and slow phases. Deviations from thR will be due to a change in offset (due

to change in line or bus voltage, or duty ratio) and not from current transitioning from

fast to slow phases.

Recall from Section 1.2 that the VRM is responsible for dropping the 12 V supply

voltage to 0.8 V. A parallel-input parallel-output (PIPO) buck converter would need to

37

operate at a very low steady-state duty ratio in order to do this. Phase current would be

able to slew up (more positive) quickly, but the limited duty ratio headroom constrains

the current to slew down (more negative) slowly. As the transient-carrying phases need to

slew in both directions quickly and with equal speed, they will operate best at a steady-

state duty ratio near 0.5. Thus an additional dc-dc converter is introduced to drop the 12

V supply rail to an intermediate 2 V rail, and the transient-carrying phases drop this in-

termediate voltage to busv . Previous research [44] shows that a two-stage VRM (a VRM

with two cascaded dc-dc converters) can be more efficient than a single-stage VRM when

the voltage transformation ratio is high, and so the dc-carrying phases are connected to

the intermediate voltage rail as well. The entire connection is shown in Figure 2.10. The

second stage, labeled VRM, is identical to Figure 1.4 and is the only stage that is dis-

cussed in detail in this thesis.

12 V Cdecoup

5 mΩ

2 V 0.8 VC

Resr

First stage

transient-

carrying

phases

dc-

carrying

phases

Second stage

(VRM)

dc-dc Load

Figure 2.10. Power converters needed to drop 12 V to 0.8 V. Second stage of this structure is the

VRM studied in this thesis.

2.2.2 Impact of Fast Phases on Loss and Bus Capacitor Size

The natural design strategy is to optimize the dc-carrying phases for steady-state

efficiency and the transient-carrying phases for fast dynamic response. The dc-carrying

phases may use a lower-than-normal switching frequency, larger-than-normal inductors,

and low-Rds,on switches to minimize loss. The transient-carrying phases should use an

38

extremely high switching frequency and very small inductors in order to maximize tran-

sient response and minimize the needed bus capacitance. Since RMS current through the

transient-carrying phases is expected to be low, switches with high conduction loss but

low gate charge will be the most efficient.

Two converters will be examined for loss and bus capacitor size. The design

specifications are:

2 V input, 0.8 V output (2-stage design for both)

140 A dc load current

Desired source impedance of 0.8 mΩ.

Sample component values are compiled in Table 2.2. Values for the slow and fast phases

are listed in the middle table columns. The sample converter has four slow phases sharing

dc current and two fast phases sharing the fast transient current. Values for a typical four-

phase VRM with matched phases are listed in the right-hand column for comparison. The

FETs in this table are chosen from the same product line and represent state-of-the-art

technology.

Table 2.2. Sample component values.

Parameter Value for Slow Phases

Value for Fast Phases

Value for Typical VRM Phase

L 500 µH 10 µH 150 µH

swf 150 kHz 5 MHz 300 kHz

swR 1.4 mΩ [45] 5.2 mΩ [46] 1.4 mΩ [45]

Vgs 10 V 4.5 V 10 V

Gate Charge 35 nC [45] 13 nC [46] 35 nC [45]

Rise / Fall Time 27 / 11 ns [45] 13 / 5.4 ns [46] 27 / 11 ns [45]

Per-phase current 35 A 5 Arms 35 A

39

Table 2.3 lists expected per-phase current and loss for each design, along with

total loss and required bus capacitance. Ripple current is found using the straight-line

approximation for buck converters [47] and converted to RMS under the assumption that

the ripple current approximates a triangle wave. Commutation loss is calculated assuming

linear dsV and dsI trajectories [30]. Bus capacitance is estimated using a form of (2.24)

modified for the buck converter and for multiple interleaved [28] phases. The equation is

,

2

0min( ,1 )

pload

in

I K LC

D D V M

(2.34)

Table 2.3. Comparison of per-phase and overall switching losses and bus capacitance of proposed

VRM compared to typical VRM.

Per-phase Parameters

Parameter Value for Slow

Phases Value for Fast

Phases Value for Typical

VRM Phase RMS ripple current 1.85 Arms 2.77 Arms 3.08 Arms

RMS switch current 36.85 Arms 7.77 Arms 38.08 Arms

Gate Charge Loss 0.055 W 0.292 W 0.105 W

Commutation Loss 0.281 W 0.958 W 0.582 W

Conduction Loss 1.90 W 0.314 W 2.03 W

Whole Converter Parameters

Parameter VRM with 4 Slow, 2 Fast Phases VRM with

Balanced Phases Total Switch Loss 12.1 W 10.9 W

Bus Capacitance 670 µF 2500 µF

where M is the number of fast phases in the converter (or number of total phases for the

VRM with all phases matched). It keeps refi slew from exceeding Li slew when the cur-

rent command is not low-pass filtered. The M term is squared because both 1 tp hK R

and L are divided by the number of phases present. It is assumed for now that C in (2.34)

is big enough to meet the voltage ripple specification; voltage ripple with ESR included

will be verified by the dynamic switched model presented in Section 4.3. The VRM with

40

additional fast phases requires less than one-third the bus capacitance of the typical VRM

design, yet consumes only 1.2 W more power. The higher efficiency of the dc-carrying

phases, made possible through use of a decoupled capacitor, nearly offset the additional

power consumed by the transient-carrying phases. The overall efficiency of the VRM at

112 W load is reduced less than one percent.

41

CHAPTER 3

SMALL-SIGNAL MODELS

The active-parallel combined source for the vehicle application, shown in Figure

2.1, has different dominant behavior at different time scales. These time scales are

stretched across many orders of magnitude. It is desired to find the plant states’ sensitiv-

ity, particularly UC voltage, to changes in battery voltage and load current. Frequency-

domain analysis gives a concise representation of sensitivity at all frequencies, but only

linear time-invariant systems may be analyzed using this technique.

Section 3.1 develops a linear model of the system in Figure 2.1, comprised of the

three-state plant and its associated controller. To do this, the switched power converter

plant is first averaged over one switching cycle [37]. The averaged model is then lin-

earized using small-signal perturbation analysis [48],[41]. Inner- and outer-loop control-

lers are wrapped around this linearized plant model to make the complete closed-loop

system. The resulting small-signal model will have a cluster of poles and zeros at low

frequencies and another cluster at higher frequencies (but still well below the switching

frequency). Lower-frequency dynamics are attributed to the ultracapacitor, inv -to- refi

charging loop, and HPF on the power-distributing cv -to- refi loop. Higher-frequency dy-

namics are attributed to the current loop, the passed portion of the power-distributing

loop, and boost converter L-C dynamics. As discussed in Section 2.1.4, the outer loop

controller must be set so that per-cycle inductor current does not change too quickly un-

der worst-case operating conditions. This means that the bandwidth of the controller will

necessarily be well below the converter’s switching frequency. An averaged, linearized

42

plant should be sufficiently accurate to develop a whole system model at all frequencies

where the controller has appreciable open loop gain.

3.1 Small-Signal System Model with Three-State Plant

3.1.1 Model of Plant

Figure 3.1 presents the plant portion of the active-parallel combined source with

significant parasitic resistances added. The bus voltage termV has been labeled ( )cv t to

show that bus voltage is equal to the voltage across the bus capacitor. The circuit has

three states: capacitor voltage ( )cv t , inductor current ( )Li t and ultracapacitor voltage

( )inv t . The energy-storing circuit elements are linear. Switches q and 'q reconfigure the

interconnection between the circuit elements; they are the control input to the system.

The switches are controlled as in a boost converter: when active switch q is on, inductor

current rises; when it is off, inductor current falls. As both switches allow current to flow

in either direction, continuous-conduction mode [41] is assumed. Other plant inputs are

open-circuit voltage ( )ocv t and current source ( )loadi t . This current source is a distur-

bance input, not part of the physical system, to inject small load disturbances into the

model.

43

voc(t)

Rbatt

ibatt(t)

iL(t)iuc(t)

ic(t)

L C

vin(t)

vL(t)

vc(t)

q

q’

Ruc

RLR

Rsw

Rsw

Cuc

iload(t)

(distur-

bance

input)

(load)

Figure 3.1. Power-handling components of the combined source for an electric vehicle.

When the active switch is ON, inductor current flows through ucC , L , and para-

sitic resistances , , and uc L swR R R . When the active switch is OFF, inductor current flows

through these same circuit elements and enters the circuit node where

, , and ( )batt loadC R R i t meet. Since inductor current flows through , , and uc L swR R R regard-

less of switch position, these resistances may be replaced by an equivalent resistance inR .

State equations can be written for each linear subsystem. The state equations with the

active switch ON are

( )( ) ( ) ( )

( ) ( ) ( ) ( )( ) ( )

( )( ) ( )

in in

ocload

batt

inuc

LL L

c c c

c L

c

u

di tv t L v t R i t

dtdv t v t v t v t

i t C i tdt R R

dv ti t C i t

dt

(3.1)

When the active switch is OFF the equations are

44

( )( ) ( ) ( ) ( )

( ) ( ) ( ) ( )( ) ( ) ( )

( )( ) ( )

inL

L L c

c c cc L

in

ocload

batt

inuc uc L

di tv t L v t R i t v t

dtdv t v t v t v t

i t C i t i tdt R R

dv ti t C i t

dt

(3.2)

In (3.1) and (3.2), the lowercase variables represent instantaneous voltage or current. Up-

percase variables are constants.

The rationale and procedure for using time averaging (or simply averaging) is

given in [41] and also in [48]. As switching frequency is fixed, averaging may be used.

The time average of (3.1) and (3.2) is

(1 )

(1 )

(1 )

in in in in

oc ocload load

batt batt

i

LL L c

c c c c cL

nuc L L

diL d v R i d v R i v

dt

dv v v v v v vC d i d i i

dt R R R R

dvC d i d i

dt

(3.3)

where d is the switch duty ratio. In (3.3) the instantaneous state and input variables are

replaced by averaged quantities, denoted by an overhead bar. The averaged quantities are

allowed to “move” [41] and so are functions of time. Duty ratio d represents the fraction

of time the active switch is ON during each cycle; thus it is inherently an averaged quan-

tity. Here d is also allowed to vary with time. The bars over the variables in (3.3) will be

neglected for clarity; lowercase variables are assumed to be averaged values that vary

with time. With like terms canceled and 'd substituted for 1 d , (3.3) becomes

'

'

LL cin in

ocload

batt

inuc

c c cL

L

diL v R i d v

dtdv v v v

C d i idt R R

dvC i

dt

(3.4)

45

As the variable 'd is a control input [41], equation (3.4) contains multiplicative nonlin-

earities between a state variable and an input. It must be linearized in order to use linear

analysis tools.

Equation (3.4) is linearized by replacing each averaged state variable,

, , and c L inv i v , and input, ', , and oc loadd v i , with a constant dc value plus a time-varying

perturbed quantity [41],[48]. The perturbed quantity is assumed to be small compared to

the dc value; thus products of perturbed terms are neglected [41]. Introducing constant

and perturbed variables is functionally equivalent to performing a Taylor series expan-

sion of (3.4) and neglecting the higher-order terms [48]. The substitutions are

' 1 ( ) '

in

oc oc oc

load load l

c c c

L L L

i

oad

n in

d D d D d

v V v

i I i

v V v

v V v

i I i

(3.5)

Define loadI to be zero; no dc load current will be applied through the disturbance input.

Substituting (3.5) into (3.4) and neglecting products of perturbed quantities gives

' '

' '

L LL Lin in in

ocload

b

c c c

c c oc c c c cL L L

i

att

inuc

nL L

dI diL V v R I i D V dV D v

dt dt

d dv V v V v V vC D I dI D i i

dt dt

V

V

R R

d dvC I i

dt dt

(3.6)

46

The linearized plant model (3.6) is valid for small perturbations of the state and input

variables about an equilibrium operating point. In equilibrium, the following dc relation-

ships apply:

0 0 0

'

' 0

' 0

L

L

c

in c

c in

in in

in

oc

batt

L

c cL

dV dVdI

dt dt dt

V R ID

V

V D V R I

V V VD I

R R

(3.7)

The relationships in (3.7) cancel all of the dc terms in (3.6) except for LI in the state

equation for inv . As inv is in equilibrium only when the ultracapacitor current is zero, and

the UC current is equal to the inductor current, the dc quantity of the inductor current

must always be zero. At higher frequencies, it is possible for the converter to be in quasi-

steady-state with a nonzero LI . A two-state model presented in Section 3.2 handles this

case and discusses the result. With the dc cancellations made and LI set to zero, the re-

sulting averaged small-signal ac model of the plant in Figure 3.1 is

'

'

in in

ocload

b

Lc c

att eq

i

L

c cL

Ln

uc

diL v D v dV R i

dtdv v v

C D i idt R R

dvC i

dt

(3.8)

where eqR is the parallel combination of resistances R and battR .

The next step is to put (3.8) into the Laplace domain and obtain transfer functions

relating plant inputs to plant states. The plant states are chosen as “outputs” because each

47

is measured and fed into some portion of the controller. The Laplace transforms of the

perturbed variables are

( )

( )

( )

( )

( )

( )

in in

oc oc

load load

L L

c c

i i s

v v s

v v s

d d s

v v s

i i s

(3.9)

With three inputs and three outputs, there will be nine transfer functions representing the

plant. To facilitate production of the transfer functions, the lines of (3.8) are put into the

Laplace domain and solved for each of the state variables:

( ) ( ) ' ( )( ) cin

in

cL

v s d s V D v si s

sL R

(3.10)

( )' ( ) ( )

( )1

ocload

battL

c

eq

v sD i s i s

Rv s

sCR

(3.11)

( )

( )inuc

Li sv s

sC

(3.12)

The input-to- ( )cv s transfer functions are found by eliminating ( )Li s and ( )inv s from

(3.10)–(3.12), leaving ( )cv s in terms of the input variables. First, ( )inv s is eliminated by

substituting (3.12) into (3.10). The resulting expression is solved for ( )Li s and plugged

into (3.11). Solving this last expression for ( )cv s gives the transfer functions

48

13

1

13

2

2 2

23

2

( ) '( )

( ) '

( )( )

( ) '

( ) 1( )

( )

ucvd LC Ruc in

uc uc in uc ucR R Req eq eq

Rbattvo LC Ruc inoc

uc uc in uc ucR R Req eq eq

vl LCucloaduc uc inReq

c c

c

c

v s sC D VG s

d s s LCC s CC R s C C D C

v sG s

v s s LCC s CC R s C C D C

v sG s

i s s LCC s CC R s

2 1'Rin

uc uc R Req eqC C D C

(3.13)

The input-to- ( )Li s transfer functions are found by plugging (3.11) and (3.12) into (3.10)

and solving for ( )Li s :

2

2 2

2 2

13

'

13

3

( )( )

( ) '

( )( )

( ) '

'( )( )

( )

V

uc uc Reqid LC Ruc in

uc uc in uc ucR R Req eq eq

Duc Rbatt

io LC Ruc inocuc uc in uc ucR R Req eq eq

ucil

lo

cc

L

L

L

aduc

s C CV sCi sG s

d s s LCC s CC R s C C D C

sCi sG s

v s s LCC s CC R s C C D C

sC Di sG s

i s s LCC

2 12 '

LC Ruc inuc in uc ucR R Req eq eq

s CC R s C C D C

(3.14)

Lastly, the input-to- ( )inv s transfer functions are found by substituting (3.11) into (3.10)

to eliminate ( )cv s , solving for ( )Li s , plugging the result into (3.12), and solving for

( )inv s :

49

13

'

13 2

3

2 2

2

2

( )( )

( ) '

( )( )

( ) '

( ) '( )

( )

V

Reqinud LC Ruc in

uc uc in uc ucR R Req eq eq

D

Rin battuo LC Ruc inoc

uc uc in uc ucR R Req eq eq

inul LCucload

uc Re

cc

q

sCVv sG s

d s s LCC s CC R s C C D C

v sG s

v s s LCC s CC R s C C D C

v s DG s

i s s LCC s C

2 1'Rin

uc in uc uc R Req eqC R s C C D C

(3.15)

For the 3-state model, steady-state cV is calculated from

oca t

cb t

RV V

R R

(3.16)

since 0LI in steady state.

Each of the nine transfer functions has the same denominator. The ( )ocv s -to-

output transfer functions are equal to the ( )loadi s -to-output transfer functions scaled by

1 battR . Looking back at Figure 3.1, cv moves in response not just to changes in load

current, but also to changes in battery current. A change in ocv makes the voltage across

battR change, with batti and cv following. From an observability standpoint, the result here

says that a controller using a measurement of cv as an input cannot distinguish between a

change in load and a change in open-circuit voltage. This controller cannot inject current

to the bus in response to increased load current without also injecting current when open-

circuit voltage drops, without using an additional measurement.

Figure 3.2 shows ( )vdG s , ( )idG s and ( )udG s using parameters given in Table 3.1

(on page 51). Parameters are chosen with regard to the design considerations laid out for

the 100 kW example given in Chapter 2. The operating point is at full load with a fairly

high boost ratio; curve magnitudes will represent a worst-case operating condition but the

curve shapes are general to all stable operating points. Two of the poles are near the L-C

50

resonance and one is at a lower frequency near 'eq ucR D C . From (3.13)–(3.15) all are in

the left half plane (LHP). The L-C resonance is heavily damped by the battery, as battR

(and thus eqR ) are expected to be relatively small. Functions vdG and idG have transmis-

sion zeros attributed to the UC. This is also expected, as the UC is being modeled as a

capacitor, with associated finite energy storage.

-100

-50

0

50

100

Mag

nitu

de (

dB)

10-3

10-2

10-1

100

101

102

103

-180

-90

0

90

180

Pha

se (

deg)

Bode diagram of 3-state Gvd, Gid, Gud

Frequency (Hz)

GvdGidGud

Figure 3.2. Plot of three-state Gvd, Gid, Gud.

51

Table 3.1. Parameters used to generate small-signal model results.

Circuit Parameters Controller Gains Operating Point Parameter Value Parameter Value Parameter Value

L 500 µH pK 65

ocV 400 V

C 18,000 µF 1 3.71

inV 180 V

ucC 44.16 F R 1.6 Ω

inR 21.1 mΩ chgK 0.4

battR 0.15 Ω

T 1*10-4 s ichgK 0.00015

battI (2-state) 30 A

aM 0.7*M2 2 0.0291

2M (400-180)/L cV (3-state) 366 V

cV (2-state) 396 V

All plotted transfer functions have a very high gain due to the high nominal bus

voltage cV . The phase of ( )vdG s and also of ( )udG s wraps to almost 180° at the gain

crossover points; introducing linear, unity feedback from either cV or inV directly to the

duty ratio input would likely result in an unstable system. The phase of ( )idG s , in con-

trast, wraps from 90° to –90° everywhere; feedback of ( )Li s to the duty ratio input

should present no problems.

3.1.2 Model of PCM Process

From an averaged model perspective, PCM control commands the averaged in-

ductor current, Li , to track the averaged reference current, refi , with some offset [49]. An

LTI model of the relationship between Li and refi was originally given by Verghese et al.

in [50]. Results are given for a boost converter in [49]. This model is reasonably accurate

at frequencies up to one-tenth the switching frequency [50] even though the boost con-

verter model is known to have dc error. A skeletal derivation follows.

A graphical relationship between instantaneous ( )Li t and ( )refi t over one switch-

ing cycle is presented in Figure 3.3. The relationship is general to dc-dc converters. The

slope of the positive-going inductor current is 1m , 2m of the negative-going inductor

52

current, and am of the compensation ramp. Duty ratio is presented as the steady-state

duty ratio, D, plus a time perturbation, d . As the converter is not in steady state, ( )Li T is

not equal to (0)Li . This is reflected in the line segment 0

T

L

D di

being unequal to dL

T

D Ti

,

where

0( ) (0)

( ) ( )

L L L

L L

D d T

T

D Ld T

i i D d T i

i i T i D d T

-ma

ma

-m2m1

m1

iref

iL(t)

0 T(D+d)T

iL

(D+d)T2

(D+d)T

m2 (D+d)T2

t

(D+d)T

0

iL (D+d)TT

Figure 3.3. Relationship of iL to iref.

Looking at the plot, the distance between averaged Li and averaged refi can be written as

the distance ( )am D d T plus the weighted sum of the current ripple averaged over each

subinterval:

1 2( ) ( ' )( ) ( ) ( ' )

2 2ref L a

m D d T m D d Ti i m D d T D d D d

. (3.17)

53

Next, the variables Li , refi , 1m and 2m are linearized and perturbed. Ramp slope am is

not perturbed because its slope is programmed and thus constant; it will be replaced by

the dc value aM . Neglecting the dc and higher-order terms, noting that 1 2'DM D M , and

solving for d , (3.17) becomes

2 2

1 2

1 '

2 2ref La

D T D Td i i m m

M T

. (3.18)

The next step is to put the perturbed inductor current slopes 1m and 2m in terms of per-

turbations in the voltage across the inductor. For a boost converter, the relationships are

21in c inv v v

m mL L

.

Substituting these into (3.18) and grouping terms gives

21 (2 1) '

2 2ref L in ca

D T D Td i i v v

M T L L

. (3.19)

The model (3.19) allows d to be written in terms of perturbed state variables

, , and c L inv i v and a new input variable refi . Using notation in (3.9), (3.19) in the Laplace

domain is

( ) ( ) ( ) ( ) ( )im ref L inn t coud s F i s i s F v s F v s (3.20)

where

21 (2 1) '

2 2m in ta

ou

D T D TF F F

M T L L

. (3.21)

This controller equation is “wrapped” around the plant transfer functions (3.13)–(3.15) to

create closed-inner-loop transfer functions. The exact steps follow.

54

3.1.3 Current Loop

The controller equation (3.20) is closed around the plant by use of algebraic sub-

stitution guided by the block diagram shown in Figure 3.4. The substitution procedure

follows that in [49]; the differences are that ( )inv s is a state variable and there are addi-

tional inputs ( )ocv s and ( )loadi s . The closed-loop transfer functions of interest are the

input-to- ( )cv s , input-to- ( )inv s , and ( )refi s -to- ( )Li s functions. The former functions pro-

vide inputs to the voltage feedback loops. The ( )refi s -to- ( )Li s function is used to check if

a chosen ramp compensation slope aM allows for adequate current tracking. It is as-

sumed that all variables are in the Laplace domain; the (s) notation is dropped.

Open-loop Plant

-+

-

+

- +

++

+

++

+

++

Figure 3.4. Block diagram of inner current loop.

55

From Figure 3.4, superposition gives

id iu oc il loaL di G d G v G i (3.22)

vd vo oc vl loac dv G d G v G i (3.23)

in ud uo oc ul loadv G d G v G i (3.24)

The open-loop refi -to- Li transfer function will be an expression with the Li feedback path

open and the cv and inv paths closed. To close the cv and inv paths, plug (3.23) and

(3.24) into (3.19) and solve for d :

1

ref in uo oc ul load out vo oc vl load

m in ud m o t vd

m L

u

F i i F G v G i F G v G id

F F G F F G

Substituting into (3.22) and solving for Li gives

1

m idLir

ref im d m in ud m out vd

F GiH

i F G F F G F F G

. (3.25)

Figure 3.5 plots irH for the vehicle application. Current Li closely tracks refi between

0.001 Hz and 1 kHz. In a real system Li will still track refi at the lowest frequencies pro-

vided that the UC has not run out of energy. The plot reinforces the notion that the UC

has a charge limit.

The input-to- cv transfer functions are obtained by eliminating Li and inv from

(3.19), plugging this into (3.23), then solving for cv . Solving for cv closes this last loop.

The expression for d with (3.22) and (3.24) plugged in is

1ref io in uo oc il in ul lm coad out

m in ud m out vd

F i G F G v G F G i F vd

F F G F F G

after grouping the input terms together. The resulting input-to- cv transfer functions are

56

-60

-50

-40

-30

-20

-10

0

10

Mag

nitu

de (

dB)

10-6

10-4

10-2

100

102

104

106

-90

-45

0

45

90

Pha

se (

deg)

Bode diagram of 3-state Hir

Frequency (Hz)

Figure 3.5. Plot of three-state Hir.

1

1

1

vdvr

ref id m in ud out vd

vo vd io in uovo

oc id m in ud out vd

vl vd il in ulvl

load id m in ud out v

c m

m m

mc

m m

mc

m m d

v F GH

i F G F F G F F G

G F G G F GvH

v F G F F G F F G

G F G G F GvH

i F G F F G F F G

(3.26)

The input-to- inv transfer functions are obtained in a similar fashion. The results are

1

1

1

in udur

ref id m in ud out vd

uo ud io out voinuo

oc id m in ud out vd

ul ud il out vlinul

load id m in ud out vd

m

m m

m

m m

m

m m

v F GH

i F G F F G F F G

G F G G F GvH

v F G F F G F F G

G F G G F GvH

i F G F F G F F G

(3.27)

Again, all lowercase variables are functions of s in the Laplace domain.

57

Figure 3.6 plots vrH and urH . As function vrH has a low gain, feeding the bus

voltage back to refi should be stable. Also, the higher-frequency poles are spread apart in

frequency, as is typical for current-mode control [49],[51]. The urH plot shows the UC’s

sensitivity to low-frequency current commands. Because sensitivity is high at low fre-

quencies, only a small amount of charging loop gain is needed to drive the UC to the de-

sired charge level. Furthermore, the slope of urH is first order between 0.001 Hz and 1

kHz and constant below 0.001 Hz. Placing an HPF on the function which sets the domi-

nant portion of refi (in this case the power-splitting cv -to- refi loop) is sufficient to enforce

a charge limit on the UC in response to a change in cv . That is, if the load current

changes by X amount, the UC charge level will change no more than Y. The tools in

Chapter 2 and the averaged nonlinear model presented in Chapter 4 provide a way to find

what the UC discharge will be in response to a particular load. This approach is different

from that taken by Awerbuch and Sullivan [25],[52] and others [22],[23] where the UC

charge is held to a hard limit Y regardless of load.

-250

-200

-150

-100

-50

0

50

Mag

nitu

de (

dB)

10-6

10-4

10-2

100

102

104

106

-180

-90

0

90

180

Pha

se (

deg)

Bode diagram of 3-state Hvr, Hur

Frequency (Hz)

HvrHur

Figure 3.6. Plot of three-state Hvr, Hur.

58

3.1.4 Outer Loop

Equations (3.26) and (3.27) describe Figure 3.1 with the current loop closed

around it. The power-distributing cv -to- refi and charging inv -to- refi voltage loops can

then be wrapped around this model. Figure 3.7 gives the block diagram for this connec-

tion. The high-pass and low-pass filters are included in the block labeled BPF(s), while

the PI controller for the charging loop is in the block labeled Kc(s). The final closed-loop

system will have disturbance inputs ocv and loadi , UC voltage reference ,uc refv , and out-

puts inv and cv .

+

+

+

+

-+

+

+

Plant with CurrentLoop Closed

+

+

Figure 3.7. Block diagram of outer voltage loops.

59

From Figure 3.7, the input-to-output relationship of the controller is

,( ) ( )p cref c uc fn reii HPF s K v K s v v . (3.28)

Equations of the plant with current loop closed are

vr ref vo oc loac vl dv H i H v H i (3.29)

in ur ref uo oc ul loadv H i H v H i (3.30)

Closed-loop input-to- cv transfer functions are obtained by plugging (3.30) into (3.28),

solving for refi , then plugging this result into (3.29) and solving for cv . The closed-loop

input-to- inv transfer functions are found in a similar fashion. The results are

,

( )

1 ( ) ( )

1 ( ) ( )

1 ( ) ( )

1 ( ) ( )

1 ( ) ( )

vrvr

uc ref ur vr

vo ur c uo vrvo

oc ur vr

vl ur c ul vrvl

load ur

c c

c p

cc

c p

cc

c p vr

v K s HJ

v K s H BPF s K H

H K s H K s H HvJ

v K s H BPF s K H

H K s H K s H HvJ

i K s H BPF s K H

(3.31)

,

( )

1 ( ) ( )

1 ( ) ( )

1 ( ) ( )

1 ( ) ( )

1 ( ) ( )

urur

uc ref ur vr

uo vr vo urinuo

oc ur vr

ul vr vl urinul

load ur

in c

c p

p p

c p

p

c v

p

p r

v K s HJ

v K s H BPF s K H

H BPF s K H BPF s K H HvJ

v K s H BPF s K H

H BPF s K H BPF s K H HvJ

i K s H BPF s K H

(3.32)

The transfer functions of blocks ( )BPF s and ( )cK s are

60

1 12

1 2 1 2 1 2

1( )

1 1 1

( ) ichg chg ichgc chg

s sBPF s

s s s s

K sK KK s K

s s

(3.33)

where gains 1 2, , and chg ichgK K are those defined in Section 2.1.

At first the ( ) uc rK s H term in the denominator of (3.31)–(3.32) looks problem-

atic. However, the numerator of urH is um dF G , and from (3.15) udG has a negative nu-

merator. Thus the negative signs cancel and (3.31)–(3.32) will be stable whenever the H’s

are stable.

Figure 3.8 plots uoJ for various loop configurations; Figure 3.9 does the same for

ulJ . Figure 3.10 plots vlJ , the magnitude of which is the dynamic output impedance (the

impedance of the combined source in parallel with the load). In Figures 3.8 through 3.10

the frequency range where the UC is being controlled to inject the most power is marked

2nd src contrib. The cutoff points are those of ( )BPF s in (3.33) scaled by 1K , K de-

fined in (2.7). The output impedance rises at higher frequencies due to the LPF attenuat-

ing refi at frequencies below which the bus capacitor may provide energy. At the lowest

frequencies output impedance is equal to eqR .

61

-150

-100

-50

0

50

100

Mag

nitu

de (

dB)

2nd src contrib

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

-180

-90

0

90

180

Pha

se (

deg) 2nd src contrib

Bode diagram of Juo with various outer loop configurations

Frequency (Hz)

No HPF, No Kc(s)With HPF, No Kc(s)With HPF and Kc(s)

Figure 3.8. Plots of three-state Juo.

-200

-150

-100

-50

0

50

Mag

nitu

de (

dB) 2nd src contrib

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

-180

-90

0

90

180

Pha

se (

deg)

2nd src contrib

Bode diagram of Jul with various outer loop configurations

Frequency (Hz)

No HPF, No Kc(s)With HPF, No Kc(s)With HPF and Kc(s)

Figure 3.9. Plots of three-state Jul.

62

-80

-60

-40

-20

0

Mag

nitu

de (

dB) 2nd src contrib

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

-180

-90

0

90

180

Pha

se (

deg)

2nd src contrib

Bode diagram of Jvl with various outer loop configurations

Frequency (Hz)

No HPF, No Kc(s)With HPF, No Kc(s)With HPF and Kc(s)

Figure 3.10. Plots of three-state Jvl.

For battR that is much less than load resistance R (true for all practical batteries),

changes in ocV have a strong effect on cV . This in turn will move the UC charge level via

the power-distributing loop. With no HPF, inv (and UC charge level) is very sensitive to

ocv and loadi disturbances. Adding the HPF with 1 3.71 reduces sensitivity at the low-

est frequencies (over a timespan of hours or days) but leaves a peak at around 0.5 mHz.

Introducing the charging loop with 0.4chgK and 0.00015ichgK attenuates the peak to

just below 0 dB without disturbing output impedance in and around the passband. In-

creasing the charging loop gain moves the peak lower in magnitude and up in frequency

but starts to impact vlJ within the 2nd src contrib region.

At low and very high frequencies, the phase of vlJ , uoJ and ulJ wraps considera-

bly. It was noted in [52] that a first-order HPF causes the UC phase in response to load

disturbances to wrap beyond where it should be, resulting in the UC contributing nega-

63

tively to load current at very low frequencies. The uoJ and ulJ plots support this observa-

tion; the phase of both transfer functions is advanced 90° near 0.001 Hz with no filter,

compared to phase in the “2nd src contrib” region. Phase is advanced about 180° with the

HPF installed. However, the magnitude of any current command at 0.001 Hz will be very

small with 1 3.71 . In addition, adding the HPF flattens the magnitude and phase of

vlJ , uoJ and ulJ across the current command passband. This is a performance improve-

ment, since the current delivered from the UC is more in phase with the load current in

this region.

3.2 Small-Signal Model with Two-State Plant

In Section 3.1.1, it was seen that the three-state plant shown in Figure 3.1 was in

equilibrium only when steady-state inductor current LI was equal to zero. On a fast time

scale, the fast dynamics of the time-averaged plant may be very close to equilibrium

when inductor current is nonzero. The small-signal averaged model of a typical boost

converter exhibits a right-half-plane (RHP) zero in the d -to- cv transfer function that is

attributed in part to dc inductor current [53]. This RHP zero carries through to the closed-

current-loop refi -to- cv transfer function, limiting feedback gain pK compared to what is

possible with a buck topology.

Figure 3.11 shows the system in Figure 3.1 with the ultracapacitor replaced by a

voltage source. The state equations with active switch q ON are

( )( ) ( ) ( )

( ) ( ) ( ) ( )( ) ( )

LL L

c

in in

oc cload

b

cc

att

di tv t L v t i t R

dtdv t v t v t v t

i t C i tdt R R

(3.34)

With the active switch OFF the equations are

64

( )( ) ( ) ( ) ( )

( ) ( ) ( ) ( )( ) ( ) ( )

LL L c

c

in in

oc cload

ba

cc

ttL

di tv t L v t i t R v t

dtdv t v t v t v t

i t C i t i tdt R R

(3.35)

voc(t)

ibatt(t)

Rbatt

RiL(t)

iload(t)

ic(t)

LC

vin(t)

vc(t)vL(t)

q

q’

RL

(distur-

bance

input)

(load)

Figure 3.11. Plant with voltage source in place of ultracapacitor.

The time-average of (3.34) and (3.35) is

'

'

in in

ocl

LL L c

c cc oad

batt eqL

div L v i R d v

dtdv v v

i C d i idt R R

(3.36)

where eqR is the parallel combination of R and battR . The variables to be perturbed are

the same as those for the three-state plant. Substituting (3.5) into (3.36), with 0loadI ,

gives

' '

' '

in in L in inL L

c L c c

c c c cL L L

oc ocload

batt eq batt eq

dI diL V R I D V v R i D v dV

dt dt

d dv V V v vC D I D i dI i

dt dt R R R R

V

(3.37)

65

With the converter in equilibrium, the dc relationships listed in (3.7) hold for the

two-state model. Thus all pure dc terms in (3.37) are canceled. The averaged ac small-

signal system has four inputs, , , , and in oc loadd v v i , and two state variables, cv and Li .

Transfer functions are found by placing the remainder of (3.37) into the Laplace domain

and substituting one equation into the other to get the appropriate output variable in terms

of the input variables. The open-loop plant transfer functions are

2

2

1

2

2

2

2

2

( ) '( )

( ) '

( ) '( )

( ) '

( )( )

( ) '

( )( )

( )

invd RL in

inR Req eq

vu RL inininR Req eq

inRbattvo RL inoc

inR Req eq

invl

Lload

Re

c L c L

c

c

c

v s sLI V D R IG s

d s s LC s CR D

v s DG s

v s s LC s CR D

sL Rv sG s

v s s LC s CR D

sL Rv sG s

i s s LC s

2'Rin

in Rq eqCR D

(3.38)

66

2

1

2

'

2

2

2

2

2

'( )( )

( ) '

( )( )

( ) '

( )( )

( ) '

( ) '( )

( )

V

Reqid RL in

inR Req eq

Reqiu RL inin

inR Req eq

D

Rbattio RL inoc

inR Req eq

ilL

loadiRe

cc L

L

L

q

L

L

sCV D Ii sG s

d s s LC s CR D

sCi sG s

v s s LC s CR D

i sG s

v s s LC s CR D

i s DG s

i s s LC s CR

2'

Rinn Req

D

(3.39)

At a particular operating point , , , ,oc in batt battV V I R R , cV , LI and 'D are defined by

'

c

c cL

in L

oc batt batt

battin

in in L

c

V V I R

V VI I

V R I R

V R ID

V

(3.40)

where LI may be solved implicitly or approximated by setting inR to zero.

The transfer function vdG has an RHP zero for all practical values of inR . Figure

3.12 plots vdG with a high LI and other parameters typical to the vehicle application.

Here it is seen that even a small feedback from ( )cv s to ( )d s will destabilize the plant if

no other compensation or feedback is introduced.

67

0

10

20

30

40

50

60

70

80

Mag

nitu

de (

dB)

10-1

100

101

102

103

-270

-180

-90

0

Pha

se (

deg)

Bode diagram of 2-state Gvd, Gid

Frequency (Hz)

GvdGid

Figure 3.12. Plot of two-state Gvd, Gid.

The linearized model of the PCM process derived in Section 3.1.2 will be applied

to the small-signal model of the two-state plant. The block diagram of the resulting sys-

tem is shown in Figure 3.13. Variables and blocks are in the Laplace domain; the (s) no-

tation is dropped. Either block diagram manipulation or algebraic substitution gives the

closed current loop refi -to- Li transfer function

( )1

idir

id out vd

m

m m

F GH s

F G F F G

. (3.41)

The closed-current-loop input-to- cv transfer functions are

68

Open-loop Plant

-+

-

+

-++

+

+

+

+

+

+

Figure 3.13. Block diagram of inner current loop for two-state plant.

1

1

1

1

1

1

1

c m

m m

m mc

m m

m mc

vdvr

ref id out vd

vu id vd iu invu

in id out vd

vo id vd iovo

oc id out vd

vl id vd i

m m

m mc lvl

load id out vdm m

v F GH

i F G F F G

G F G F G G FvH

v F G F F G

G F G F G GvH

v F G F F G

G F G F G GvH

i F G F F G

(3.42)

69

With vdG in the numerator of vrH , vrH also has an RHP zero. Root locus plots show the

effect of the zero when feedback from cv to refi is added. Figure 3.14 is the root locus of

vrH (using vdG plotted in Figure 3.12) with no filtering in the feedback path. A pK

greater than about 28 makes the closed-loop system unstable. This is a rather small pK ; it

corresponds to a K of about 1.9 per (2.7). Adding an LPF to the voltage feedback path is

one solution to the problem. Figure 3.15 plots the root locus of vrH with such a filter in

place. The peak allowed pK is now 377, and a pK of 65 results in a well-damped re-

sponse to a load step. The prospect that voltage feedback into the current command of a

current-mode converter could be unstable was brought up in [25]; models here verify that

this is the case and the problem is addressed by adding an LPF and choosing appropri-

ate pK .

-3 -2 -1 0 1 2 3 4

x 104

-6000

-4000

-2000

0

2000

4000

6000

System: Hvr_no_LPFGain: 28.6Pole: 31.2 + 5.25e+003iDamping: -0.00594Overshoot (%): 102Frequency (rad/sec): 5.25e+003

Root Locus of Hvr without LPF in feedback path

Real Axis

Imag

inar

y A

xis

Figure 3.14. Root locus of two-state Hvr, no filters in feedback path.

70

-1000 -500 0 500 1000 1500-1000

-500

0

500

1000System: Hvr_with_LPFGain: 377Pole: 0.433 + 546iDamping: -0.000793Overshoot (%): 100Frequency (rad/sec): 546

System: Hvr_with_LPFGain: 65Pole: -195 - 164iDamping: 0.766Overshoot (%): 2.38Frequency (rad/sec): 254

Root Locus of Hvr with LPF; 2 = 0.0291

Real Axis

Imag

inar

y A

xis

Figure 3.15. Root locus of two-state Hvr, LPF in feedback path.

The last step is to obtain the complete system sensitivity functions, with the volt-

age loop closed. Because the HPF typically has a large time constant, it will have little

effect at higher frequencies. More importantly, the open-loop pole in the HPF is no

longer counteracted by the transmission zero attributed to ucC in the plant input-to- cv

equations, so including the HPF on the two-state model will actually produce an errone-

ous result. Therefore, the HPF is neglected from the expression. The charging loop is

neglected for the same reasons. Figure 3.16 shows the remaining connection.

71

Plant with Current Loop Closed

+ +

++

Figure 3.16. Block diagram of the portion of the outer voltage loop that is dominant at high

frequencies.

Following the procedure outlined in Section 3.1.4, the closed-loop input-to- cv

transfer functions are

1 ( )

1 ( )

1 ( )

vuvu

in vr

vo

c

p

c

p

c

vooc vr

vlvl

load vr p

v HJ

v H LPF s K

v HJ

v H LPF s K

v HJ

i H LPF s K

(3.43)

where

2

1( )

1LPF s

s

. (3.44)

Figure 3.17 plots voJ defined in (3.43) against its three-state equivalent; Figure 3.18 does

the same for vlJ . The point marked “LP corner” in Figure 3.17 is the corner frequency of

72

the LPF scaled by 1K , where K is defined in (2.7). Function vlJ is the dynamic output

impedance of the closed-loop system, valid at higher frequencies. These plots show that

cv is considerably more sensitive to disturbances ocv and loadi when the converter is

boosting current ( 0LI ) than when 0LI . The hump in voJ and vlJ around 40 Hz is

attributed to the “gap” where neither the bus capacitor nor the second source is providing

energy to the load. It is created by the choice of LPF coefficient 2 and bus capacitance.

The output impedance vlJ rises to eqR at the peak of the hump. Finally, Figure 3.19 plots

, and vu vu vuG H J . These functions correspond to audio susceptibility in a boost converter

[53] and follow the same basic shape as the line-to-output transfer functions [53],[49].

The double pole on vdG is damped by small eqR .

-40

-30

-20

-10

0

Mag

nitu

de (

dB)

LP corner

10-1

100

101

102

103

-180

-90

0

90

180

Pha

se (

deg)

LP corner

Bode diagram of 2-state, 3-state Jvo

Frequency (Hz)

2-state Jvo3-state Jvo

Figure 3.17. Plots of two-state and three-state Jvo.

73

-60

-50

-40

-30

-20

-10

Mag

nitu

de (

dB)

LP corner

10-1

100

101

102

103

-180

-90

0

90

180

Pha

se (

deg)

LP corner

Bode diagram of 2-state, 3-state Jvl

Frequency (Hz)

2-state Jvl3-state Jvl

Figure 3.18. Plots of two-state and three-state Jvl.

-60

-40

-20

0

20

Mag

nitu

de (

dB)

LP corner

10-1

100

101

102

103

-180

-135

-90

-45

0

45

Pha

se (

deg)

LP corner

Bode diagram of Gvu, Hvu, Jvu

Frequency (Hz)

GvuHvuJvu

Figure 3.19. Comparison plot of the two-state Gvu, Hvu, Jvu.

74

3.3 Stability Check

The small-signal models provide a simple way to see whether a particular operat-

ing point is stable — just check to see whether or not all poles are in the open LHP

(OLHP). A MATLAB script which computes the various G, H and J transfer functions

and checks their poles was written and is documented in Appendix A. To determine sys-

tem stability, the script was run over the range of operating points given in Table 3.2. The

two-state models were closed-loop stable at all tested points, with both forward and re-

verse LI . The three-state models were closed-loop stable everywhere except at the ex-

treme operating point of 140 VinV , 420 VocV , 0.1 battR and any R. System sta-

bility is maintained up to the target 2.5:1 maximum boost ratio and across all load cur-

rents with the choice of circuit parameters and controller gains.

Table 3.2. Operating points at which system stability was checked.

Parameter Values Checked

inV 140 to 320 V, 20 V steps

inV 300 to 420 V, 20 V steps

R 1.6 Ω, 16 Ω, 1 MΩ

battR 0.1, 0.15, 0.75 Ω

loadI (2-state only) 0, 14, 147 A

3.4 Summary

The small-signal models derived in this chapter are useful tools for analyzing the

system proposed for the vehicle application. The three-state model shows that an HPF in

the cv feedback path is capable of enforcing a charge limit on the UC for a given change

in cv , and that the charging loop makes UC voltage (state-of-charge) less sensitive to

very low frequency changes in cv . The two-state model shows that too high a pK can

drive the converter unstable on account of the RHP zero, and filtering the current com-

75

mand with an LPF increases the permissible pK . The controller cannot distinguish

whether changes in cv result from a change in load current or a change in ocv ; and the

models showed that small changes in ocv can have a dramatic effect on UC charge level.

System stability is validated for the choice of circuit parameters and controller gains for

this application. The small-signal plant models provide a solid platform on which to

evaluate other controller designs.

76

CHAPTER 4

LARGE-SIGNAL MODELS

4.1 Switched Model for Vehicle System

The power-handling portion of the combined source and controller is viewed as a

switched system comprised of two subsystems (3.1) and (3.2). Both (3.1) and (3.2) are

linear ordinary differential equations (ODEs). The system is solved by computing the

state trajectories according to (3.1) for a period of time, then switching over to (3.2) and

continuing the computation. Alternating between the two, the final state values of one

equation are used as initial values of the other equation. Switching instants are decided by

a switching signal created by another routine, in this case a stateful model of the Control-

ler portion of Figure 2.1. In this fashion the system may be solved out to an arbitrary

point in time given some initial condition at time zero.

The switched model is derived and documented in Section 4.1.1. Solver step size

is discussed in Section 4.1.2 and the state initialization routine is given in Section 4.1.3.

Simulation results are presented in Section 4.1.4.

4.1.1 Model Derivation

The Simulink package was used to create the switched model. Plant equations

(3.1) and (3.2) were modified to include the capacitor ESR. They are

in in

oc esr esrload

ba

LL L

c c c ccc

tt

inuc uc L

div L v R i

dtv v i R v i Rdv

i C idt R R

dvi C i

dt

(4.1)

77

when the active switch is ON and

LL L c c

c c

in in esr

oc esr esc rload

batt

inuc

cc

uc L

cL

div L v R i v i R

dtv v i R v i Rdv

i C i idt R R

dvi C i

dt

(4.2)

when the active switch is OFF. Simulink handles these implicitly-defined functions by

using the previous value of ci to compute the next value of state variables , , and c L inv i v .

An overview of the switched model is presented in Figure 4.1. The blocks on the right-

hand side of the diagram represent disturbances that may be injected into the system.

Next, the controller block is expanded as shown in Figure 4.2. The upper half of this dia-

gram contains the outer voltage loops and the PCM process is modeled in the lower half.

The active switch is turned ON by a positive clock pulse and turned OFF when ( )Li t

meets or exceeds ( )refi t . Controller sub-blocks are broken out in Appendix B.1. The

boost converter plant model is based upon work done by Logue [54],[55].

78

ucap capa-citance

-K-

Vuc, Vout

Voc step

TransportDelay

Manual Switch5Manual Switch4

Manual Switch3Manual Switch1

Manual Switch

ManualSwitch2

Loadstep

Loadramp

Iout, Ibatt, Iload

Integrator

1s

Iload step

Iload ramp

Iload pulse

IL, Iout, Ibatt, Iload, Iref Fixed iload

0

Fixed R

1e6

Divide

Controller

Vc

I_ind

Vin

Scope out

q(t)

Boost converter(Bidirectional;

Lossy switching)

vin

iout

q(t)

vout

iin

Batt open-ckt voltage

Voc

1/Rbatt

-K-

Figure 4.1. Overview of switched model of the combined source for an electric vehicle.

Iref

q(t)

2

Scope out

1

Vuc,ref

-C-

Terminator

Stabilizing Ramp

SR latch

S

R

Q

Q'

P

Kp

Manual Switch

Low corner

In1 Out1

Kichg

-K-

Kchg

-K-

Integrator1

1

s

Fixed Iref

-C-

Comparator

+

-

Out

Clock

BPF

In1 Out1

-BPF'd Vc

Vin

3

I_ind

2

Vc

1

Figure 4.2. Controller block of Figure 4.1, expanded.

79

4.1.2 Step Size Limitation

Because a numerical solver must break the continuous time domain into discrete

steps, most of the time the ON-to-OFF switching transition will happen when ( )Li t is not

exactly equal to ( )refi t . This represents an estimation error compared to what would hap-

pen in an idealized continuous-time system. Recall from the small-signal model deriva-

tion in Section 3.1.1 that there is a high gain between duty ratio and state variables cv and

Li . A small error in the estimation of a switching instant will result in large state trajec-

tory errors. When running the switched model, the maximum solver step size needed to

be set to one one-thousandth of a switching period ( 710 seconds for a 10 kHz switching

frequency) in order to get acceptable accuracy. The solver dropped its step size further at

the switching instants, where the derivatives of the state trajectories are discontinuous.

The small step size made it impractical to execute more than a few seconds’ worth of

simulation time. The switched model is very useful for verifying fast transient behavior,

but is impractical for analyzing behavior which occurs over long periods of time.

4.1.3 State Initialization Procedure

The states of the switched model are never in equilibrium. When the system is

considered to be in steady state, plant and controller states follow a limit cycle trajectory

[56],[57]. Initial state values need to be chosen such that the model starts in this limit

cycle trajectory with no disturbances. The states which most strongly determine whether

or not the model is in a limit cycle are , L ci v and the state of the integrator which follows

gain ichgK (the charging loop integrator) in Figure 4.2, and so this section focuses on

finding the initial values of these states.

80

When the UC is in steady state, it supplies no power to the load. This means that

average LI is zero and average cV is

oca t

cb t

RV V

R R

. (4.3)

If no net power is transferred to the load, after one switching cycle no net charge is trans-

ferred from the inductor to the capacitor. This means

0

0 0

( ) 0

( )

T

T T

oc ocbatt batt

L

c

i t dt

R Rv t dt V V T

R R R R

. (4.4)

A numerical solver is used to compute the trajectory of ( )Li t and ( )cv t over one

switching cycle, using model equations (4.1) and (4.2). An implicit solver is used due to

the presence of ci on the right-hand side of the equations. The switching instant occurs at

time DT, where D is the steady-state duty ratio

1 in in

esr batt lo

L

L adc

V R ID

V R I I I

. (4.5)

Here, LI , battI and loadI are ( )Li t , ( )batti t and ( )loadi t , respectively, averaged over one

switching cycle. Since 0LI and obatt l adI I in pure steady state, D reduces to

1 i

c

nVD

V . (4.6)

To get initial states (0)Li and (0)cv , the solver is executed for various initial conditions

until a set is found where both

(0) ( )

(0) ( )L L

c c

i i T

v v T

(4.7)

81

and equation (4.4) hold. The initial state of the charging loop integrator, ,ref initI , is then

given by

, ( )ref in t ai LI i DT m DT . (4.8)

Current ( )Li DT is the inductor current found by the solver at time DT using initial condi-

tions (0)Li and (0)cv , and am is the slope of the compensation ramp required to ensure

the stability of the PCM process [51].

4.1.4 Simulation Results

A sequence of full-scale load steps was performed on the switched model. The

resulting current trajectories are drawn in Figure 4.3. An instantaneous 250 A or 500 A

load step is an abusive condition that should never be seen under normal operation; the

test is used to see how Li responds to large changes in termv . Setting the LPF filter coeffi-

cient 2 to 0.0291 makes Li follow a damped second-order trajectory. This confirms

what was predicted in Figure 3.15 using the two-state small-signal model. The lower por-

tion of Figure 4.3 is a close-up of Li and refi trajectories during the steepest rise in induc-

tor current at 305 ms. The duty ratio is about 0.65 in this graph, near the steady-state D of

0.55 and well within the 0.85 limit. The 18,000 µF bus capacitor prevents the LPF from

seeing a true step, making (2.27) inaccurately predict the relationship between the duty

ratio swing and 2 .

82

0 50 100 150 200 250 300 350 400 450 500

-400

-200

0

200

400

600

Cur

rent

(A

)

Time (ms)

iL

ibatt

load I

304 304.2 304.4 304.6 304.8 305 305.2 305.4 305.6 305.8 306-200

-150

-100

-50

0

50

Time (ms)

Cur

rent

(A

)

iL

iref

Figure 4.3. (Top) Response of iL, ibatt to load step. (Bottom) Close-up of iL rise after 500 A step up.

Figure 4.4 shows current and voltage trajectories when a load ramp is applied.

The ramp has the peak magnitude and slew that the load is expected to demand in prac-

tice. The plot shows that batti is well-controlled; the control bandwidth allowed by 2 is

sufficient to make the second source absorb the fast components of the ramp. The trajec-

tories, especially termv in the lower plot, vary in thickness with load because the switched

model outputs both the ripple and averaged portions of the variables. Twenty thousand

switching cycles elapse over two seconds, and so the line thickness corresponds to ripple

magnitude. The termv plot in the lower portion of Figure 4.4 shows that voltage ripple is

about 2.5 V and within design specification.

83

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-500

-375

-250

-125

0

125

250

375

500

Cur

rent

(A

)

iL

ibatt

load I

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2390

395

400

405

410

Time (s)

Vol

tage

(V

)

vterm

Figure 4.4. (Top) Response of iL, ibatt to load ramp. (Bottom) Bus voltage in response to load ramp.

4.2 Nonlinear Averaged Model for Vehicle System

As discussed in Section 4.1, it is impractical to use the switched model to observe

dynamic behavior which occurs on slow time scales. Since the step size was constrained

by switching phenomena, removing the “switching” part of the model allows the step size

to be greatly reduced. The switching information is removed by time-averaging (4.1) and

(4.2). The time-averaged dynamic equations for the plant, with capacitor ESR included,

are

84

'

'

in in out

oc out outload

batt

inuc

LL

cL

L

cu e rco t s

diL v R i d v

dt

dv v v vC d i i

dt R R

dvC i

dt

v v i R

(4.9)

Here the lowercase variables represent quantities that are time-averaged over one switch-

ing cycle. The duty ratio d is

1

' 1

L

c

in in

esr batt loaL d

v R id

v R i i i

d d

(4.10)

where

oc esr

batt

c cbatt

esrload

c c

v v i Ri

R

v i Ri

R

(4.11)

Equation (4.9) and the quantities that substitute into it are left implicitly defined. The past

value of ci is used to compute the next value of each state variable. This gives acceptable

accuracy for small esrR and allows for all non-switching loss to be accounted for.

At lower frequencies, the reference current refi is related to time-averaged Li by

'

'2 2

cref L a

ininv v d Tv dT

i i d d m dTL L

(4.12)

per [50]. Since Li is completely controlled at low frequencies, the state attributed to the

inductor is eliminated from the model. Equation (4.12) accounts for the impact of the

85

current loop on plant dynamics at lower frequencies when the voltage loops are closed

around it.

Figure 4.5 shows an overview of the complete averaged model. Individual blocks

are expanded in Appendix B.2. This model is used to verify that a choice of gains pK and

1 distributes power as predicted by the equations in Section 2.1.2. It can also show the

charging loop’s impact on the system in the time domain. Selecting initial states which

put the system in equilibrium is straightforward because the average system exhibits true

steady-state behavior.

load R

Vc

Pload_desRiref_to_iL

Vin

i_ref

v_c

dp

i_L

ibatt, il=-iuc, iref

i_uc

-u(1)

i_c

Vin

i_L

Vc

R

i_c

dp

Voc

ibatt

Voc, Vc, Vin_state,Vin_term

Vin_term

f(u)

UC energy

Terminator1

TerminatorRepeatingSequence1

Product Integrator2

1s

Integrator1

1s

Integrator

1s

FromWorkspace

sine_vec

Dp

Controller

Vin

Vciref

100 kW pulse

1/Cuc

-K-

1/C

-K-Vc

Vin

Figure 4.5. Overview of averaged nonlinear model of the combined source for an electric vehicle.

86

4.2.1 Simulation Results

Figure 4.6 shows the response of the averaged model to the 100 kW pulse train

described in Section 2.1.2. The model was started in steady state with inv equal to

, 266 Vuc refv . Battery current reaches a maximum of 143 A at the end of the third dis-

charge cycle, which is within the 147 A specification. UC voltage bottoms out at 188 V

before being pulled back toward the reference level by the charging loop. This is within

the 180 V design specification. The middle plot shows that peak inductor current reaches

320 A when the pulse is first applied. This is lower than the ~500 A inductor current seen

in Figure 4.4 because inv starts at 266 V instead of 180 V. The charging loop brings inv

close to ,uc refv after about 300 s, successfully compensating for the offset between Li and

refi .

0 100 200 300 400 500 600 700180

220

260

300

Vol

tage

(V

)

vin

0 100 200 300 400 500 600 700-200

0

200

400

Cur

rent

(A

) iL

iref

0 100 200 300 400 500 600 7000

50

100

150

Time (s)

Cur

rent

(A

) ibatt

Figure 4.6. Response to the 100 kW pulse train described in Figure 2.4.

87

Figure 4.7 shows the response of inv and batti to a 20 A, 0.5 mHz sinusoidal load

current. The gray line is the system response when charging loop gains chgK and ichgK

are both set to zero. The UC voltage varies considerably while the batti magnitude ex-

ceeds load current and lags it in phase. Awerbuch and Sullivan [52] observed that the

extra battery draw hurts system efficiency. Thus, the currents flowing through the UC in

phase with load current need to be minimized. Adding the charging loop reduces the inv

ripple magnitude by almost a factor of 3, indicating that the UC current was also reduced

by this magnitude, but does not completely eliminate the circulating current, as the mag-

nitude of batti still exceeds load current.

0 2000 4000 6000 8000 10000 12000 14000236

246

256

266

276

Vol

tage

(V

)

Time (s)

vin

no chg loop

vin

w/ chg loop

6000 6200 6400 6600 6800 70000

5

10

15

20

Cur

rent

(A

)

Time (s)

ibatt

no chg loop

ibatt

w/ chg loop

load i

Figure 4.7. (Top) vin response to 0.5 mHz sine wave load. (Bottom) Zoomed view of one half-cycle of

ibatt and load current.

88

4.3 Switched Model for VRM

A switched model is developed in Simulink for the VRM with multiple transient-

carrying phases described in Section 2.2 and shown in Figure 2.9. The model will be used

to predict the system’s response to large load, line and reference steps. The objective is to

see whether the proposed topology will regulate bus voltage to the specifications outlined

in [27] using the small 670 µF bus capacitance predicted by (2.34).

Figure 4.8 shows the major model blocks and their connections. The dc phase, ac

phase and Bus Capacitor blocks implement state equations for the plant portion of Figure

2.9 and are based upon work done by Logue [54],[55]. Here “dc” refers to the four dc-

carrying phases and “ac” refers to the two fast phases which carry transient current only.

The 2 V source block models the first converter stage in Figure 2.10 as a voltage source

with series impedance of 5 mΩ, substantially higher than the 0.8 mΩ required by the

processor. With 5 mΩ series impedance, the intermediate voltage swings between 2 V

and 1.25 V with load current, allowing the VRM’s steady-state duty ratio to be between

0.4 and 0.6 under all loads. Figure 4.9 (on page 90) details the outer loop controller. The

LPF and BPF blocks divide the main current command by frequency. They contain first-

order low-pass and bandpass filters, respectively. Offset correction for each group of

phases is provided by the Native AVP blocks [36]. The full model is expanded in Appen-

dix B.3.

89

dc pcm process

IL_1

IL_2

IL_3

IL_4

Iref/4

Scope out

q(t)_1

q(t)_2

q(t)_3

q(t)_4

ac pcm process

IL_1

IL_2

Iref/2

Scope out

q(t)_1

q(t)_2

Vzero

Voc

Vin, Vout

Outer loopcontroller

sum_IL_s

Vout

Vzero

sum IL f

Iref_s

Iref_f

Load R

Irefs, ILs

Divide

Dc phase 4

vin

iout

q(t)

vc

iL

iin

Dc phase 3

vin

iout

q(t)

vc

iL

iin

Dc phase 2

vin

iout

q(t)

vc

iL

iin

Dc phase 1

vin

iout

q(t)

vc

iL

iin

BusCapacitor

i_c

vout

vc

Ac phase 2

vin

iout

q(t)

vc

iL

iin

Ac phase 1

vin

iout

q(t)

vc

iL

iin

2 V source

iinVin

iout

Figure 4.8. Overview of switched model of the VRM.

90

Iref_f

2

Iref_s

1

iref_s/4

1/4

iref_f/2

1/2

iL/4

1/4

iL/2

1/2

Native AVP1

iL

iref

ioff

Native AVP

iL

iref

ioff

LPF

In1 Out1

Kp/4

Kp

BPF

In1 Out1

sum_IL_f

4

Vzero

3

Vout

2

sum_IL_s

1

Vzero iref_s

iref_f

Figure 4.9. VRM outer loop controller (Controller block in Figure 4.8).

Key simulation and model parameters are listed in Table 4.1 (on page 91). The

dividing point between the fast and slow phases was chosen to be 3 kHz. The corner for

the LPF in the Native AVP block is chosen to be slow so that the offset provided by this

block is essentially fixed on fast time scales. Each set of phases is interleaved with regard

to other phases in that set, but fast phases run asynchronously from the slow phases. Code

to start the model very close to steady state with no load current is listed in Appendix

B.3. At present these scripts will not start the model in steady state with nonzero load

current.

91

Table 4.1. Parameters used in the VRM model.

Per-Phase Circuit Parameters Controller Gains Common Parameters Parameter Value Parameter Value Parameter Value

bigL 500 nH pK 1250

refV 0.8 V

Slow LswR R 4.15 mΩ , ,c lpf dcf 3 kHz

inV 2 V

slowT 66.67 10 s , ,c hpf transf 3 kHz srcR 5 mΩ

,a slowM 0.7 0.8 bigL , ,c lpf transf 7.96 MHz C 670 µF

,c navpf 200 Hz

esrR 0.8 mΩ

smallL 10 nH

Fast LswR R 7.5 mΩ

fastT 72 10 s

,a fastM 0.7 0.8 smallL

4.3.1 Simulation Results

Substantial load, line and reference steps are applied to the simulated system.

Phase currents are plotted in response to each disturbance, along with bus voltage. Plots

show how current is distributed between the phases and if bus voltage meets the targets

established in [27].

Figure 4.10 shows phase currents and bus voltage when a 120 A load is applied at

t = 0.1 ms, and then removed at t = 0.5 ms. The specification in [27] calls for bus voltage

to be 0.8 V when load current is 0 A and 0.704 V when load current is 120 A, with no

more than 50 mV overshoot of these targets. Figure 4.10 shows that BPF and LPF in the

outer loop distribute current as is expected, and current trajectories are well-behaved. Bus

voltage overshoot is 15 mV or less, well within the 50 mV specification.

92

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

-60

-40

-20

0

20

40

60

Pha

se c

urre

nt (A

)

Time (ms)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90.65

0.7

0.75

0.8

Time (ms)

Vol

tage

(V)

Vbus

Slow phase currents

Fast phase currents

Figure 4.10. Response of phase currents (top) and bus voltage (bottom) to 120 A load step.

Figure 4.11 shows the response to 25% line steps. Load current before the steps

were applied is 120 A. The simulation was started at no load, then load resistance was

changed to 5.87 mΩ and the system was allowed to settle before the line steps were ap-

plied. A 2 to 2.5 V line step up was applied 1 ms into the simulation run. The left-hand

plots in Figure 4.11 show the response of phase currents and bus voltage to the step. Plots

on the right do the same for a 2.5 to 2 V line step down occurring 1.5 ms into the run. The

bus voltage deviates less than 5 mV from nominal in response to either line step. Voltage

ripple increases because of the higher line voltage but is still only a few mV.

93

0.98 1 1.02 1.04

-10

0

10

20

30

40P

hase

cur

rent

(A

)

Time (ms)

Slow phase currents

Fast phase currents

0.98 1 1.02 1.040.68

0.69

0.7

0.71

0.72

Time (ms)

Vol

tage

(V

)

Vbus

1.48 1.5 1.52 1.54

-10

0

10

20

30

40

Pha

se c

urre

nt (

A)

Time (ms)

Slow phase currents

Fast phase currents

1.48 1.5 1.52 1.540.68

0.69

0.7

0.71

0.72

Time (ms)

Vol

tage

(V

)V

bus

Figure 4.11. (Left plots) Phase current, vbus response to 2-to-2.5 V line step up at t = 1 ms.

(Right plots) Phase current, vbus response to 2.5-to-2 V line step down at t = 1.5 ms.

Figure 4.12 shows the response to 25% open-circuit reference steps. Load resis-

tance was 8.89 mΩ, corresponding to about 80 A load when the open-circuit reference is

0.8 V. Like the line step plots, the simulation was started under no load, the load resistor

applied, and the system allowed to settle 1 ms before the reference was stepped from 0.8

to 1 V. The reference was stepped back down to 0.8 V at time 1.5 ms. Due to the small

output capacitor and fast phases, output voltage responds very quickly to a step change in

reference voltage. Again there is little voltage overshoot, and current through the fast

phases returns to zero in steady state. In all three of the figures, fast phase current appears

“noisy” because the displayed simulation output was sampled only ten times per fast

switching cycle. No subharmonic instability was observed on these phases.

94

1 1.05 1.1

-20

0

20

40

60P

hase

cur

rent

(A

)

Time (ms)

Slow phase currents

Fast phase currents

1 1.05 1.1

0.7

0.75

0.8

0.85

0.9

Time (ms)

Vol

tage

(V

)

Vbus

1.5 1.55 1.6-60

-40

-20

0

20

40

Pha

se c

urre

nt (

A)

Time (ms)

Slow phase currents

Fast phase currents

1.5 1.55 1.6

0.7

0.75

0.8

0.85

0.9

Time (ms)

Vol

tage

(V

)

Vbus

Figure 4.12. (Left plots) Phase current, vbus response to 25% reference step up at t = 1 ms.

(Right plots) Phase current, vbus response to 25% reference step down at t = 1.5 ms.

It is emphasized that simulations were run using a 670 µF bus capacitor with 0.8

mΩ ESR. This is a smaller capacitor, with larger ESR, than the decoupling capacitors

near the processor socket [27]. These results show that the fast phases can completely

replace the bulk capacitors on the board.

95

CHAPTER 5

EXPERIMENTAL RESULTS

A combined power source for an electric vehicle application was built and ex-

perimentally tested to verify predictions of the large-signal models, and by association

the design equations and small-signal models. As full-scale hardware is difficult to test,

experiments were performed on scaled-down hardware. Scaling is discussed in Section

5.1. The hardware itself is described in Section 5.2. Battery impedance was characterized

in Section 5.3 in order to supply an accurate value of battR to the models, as power appor-

tioning and thus system state values depend strongly on this parameter. Step response and

repeated full-power draw tests were performed on the hardware in Sections 5.4 and 5.5,

respectively, to verify that the system meets its design targets and to see how well its be-

havior follows that predicted by the models.

5.1 Scaling the Design

A 100 kW, 400 V power source requires special equipment to test. A low-voltage,

lower power system can be tested using bench equipment. A 12 V nominal bus is selected

to ease development and circuit measurements; this is 3% of 400 V. Scaled current is 7.5

A, or 3% of 250 A, and scaled power is 90 W. Load requirements are scaled in magnitude

but not in time:

Peak power: 90 W for 10 seconds, both directions

Average power: 22.5 W long-term

Load slew: zero to peak power in 0.2 s, peak to peak power in 0.4 s

Battery power restricted to 45 W at low cell voltage.

96

Since the time parameters are the same as before, the required UC power and energy

scales by 0.032. Maximum and minimum UC voltage is 80% and 45% of bus voltage,

respectively. Table 5.1 shows a summary of the scaling.

Table 5.1. Full and scaled system values. Parameter Full Value Scaled Value Scaling Factor

Bus voltage 400 V 12 V 0.03 Peak load current 250 A 7.5 A 0.03 Peak load power 100 kW 90 W 0.032 Battery charge capacity 147 A-h 4.4 A-h 0.03 Peak battery power 50 kW 45 W 0.032 Long-term average power 25 kW 22.5 W 0.032 Battery resistance 0.15 Ω 0.15 Ω Unchanged Load slew rate 1250 A/s 37.5 A/s 0.03 UC energy needed 859 kJ 773 J 0.032 Peak UC voltage 320 V 9.6 V 0.03 Min UC voltage 180 V 5.4 V 0.03 Required Cuc 44.16 F 44.16 F Unchanged

With system parameters scaled according to Table 5.1, battR and ucC are identical

for both systems. Other critical ratios, such as peak-to-average power, are also un-

changed. These properties give the two systems the same dynamic response at lower fre-

quencies, and therefore both systems should require the same outer-loop control tunings

to get the desired power apportioning and UC charging. Setting 2 the same for both

converters will make their control bandwidths approximately equal.

The scaled battery is made from two strings of three cells each, of the same type

and size chosen in Section 2.1.2 for the full-sized battery. Cells of this size and type are

well-characterized in [40]. The UC is a string of five 350 F ultracapacitors, resulting in

70 F capacitance. This is about 50% more than the 44.16 F scaled value. The extra ca-

pacitance will not affect how power is apportioned but it will require increasing the

charging loop gains to maintain disturbance rejection. Key converter parameters are

97

compiled in Table 5.2. These parameters will be entered into the averaged and switched

nonlinear models; the models themselves do not change as a result of scaling.

Table 5.2. Hardware and controller parameters for the scaled-down converter.

Circuit Parameters Controller Gains Parameter Value Parameter Value

L 100 µH pK 65

C 8000 µF 1 3.71

ucC 70 F

inR 22.9 mΩ chgK 1.05

T 1*10-4 s ichgK 0.002

aM 0.7*M2 2 0.0291

2M (12-5.4)/L

5.2 Hardware and Setup

Figure 5.1 is a close-up picture of the power converter hardware. The PCM proc-

ess is implemented using a UC3823A PWM IC. To make the IC support bidirectional

current flow, the protection features were disabled and the sensed inductor current signal

was level-shifted. Logic was added to allow the FETs to be shut down by an external

command from the outer loop controller in order to provide a minimum level of circuit

protection. Appendix C contains the hardware schematics.

98

Figure 5.1. Close-up of power converter hardware.

Figure 5.2 gives an overview of the controller for the power converter hardware.

This software controller was implemented using MATLAB Real-Time Workshop and is

executed on a PC running xPC Target operating system. It contains the linear outer loop

controller described in Section 4.1.1 and routines to provide circuit protection. The con-

troller takes in measurements of inv , Li , and a high-passed termv , and outputs refi and a

FET Enable signal to the board. Bus voltage termv is high-pass filtered and amplified in

hardware, on the power converter board, in order to get sufficient amplitude resolution

when this signal is passed to the A/D interface. Controller states are updated at fixed 15

µs intervals.

99

xPC Target SetOverload Counter

SetOverload Counter

Vin_gain

2

Vin

Undervoltage Hiccup Mode

Vin

Iref_in

Enable

Iref

Re-enable Delay

Enable_in Enable

Q8 DA

Q8Quanser

Analog Output

1

5Q8 AD

Q8Quanser

Analog Input

1

2

5

Overcurrent Protection

Iref_in

I_L

Iref

Enable

LogicalOperator

ANDLinear controller

Vin

Vterm

Iref

Iref_gain

0.01

Iref

I_L IL_gain

10

HPFd_Vtermgain

-0.1

HPFd_Vterm

Enable Gain

10

Enable

Data TypeConversion2

Convert

Data TypeConversion1

Convert

Data TypeConversion

Convert

Constant2

0

Constant1

-C-

Constant

0

Add1

Add

v_in

i_L

Iref

-HPFd Vterm

Figure 5.2. Overview of outer loop controller running on xPC Target.

A Quanser Q8 A/D interfaces the xPC Target machine with the power converter

hardware. The A/D was read and written to every 90 µs, with about 17 µs latency [58].

This is sufficient speed for this application. Figure 5.3 shows a picture of the complete

hardware setup with various components labeled. Load is provided by either a load resis-

tor or a programmable dc load as is appropriate for the test.

100

Figure 5.3. Test setup.

5.3 Battery Resistance Measurement

The battery resistance battR is vitally important for both power distribution and

system dynamics. A characterization of battR across frequency is needed. To measure

impedance, the battery was hooked up to a programmable dc load biased with a dc supply

so that current could both flow into and out of the battery [59]. A sinusoidal current was

101

drawn from the battery and its terminal voltage was measured. Table 5.3 lists the imped-

ance magnitudes measured at different frequencies. The battery was charged to 12 V

nominal and current magnitude was 1 A peak-to-peak (p-p).

Table 5.3. Battery impedance measurement. Frequency P-P Current

Draw P-P

Voltage Battery Impedance

Magnitude 0.1 Hz 1 A 0.58 V 0.58 Ω 0.3 Hz 1 A 0.48 V 0.48 Ω

1 Hz 1 A 0.35 V 0.35 Ω 3 Hz 1 A 0.35 V 0.35 Ω

10 Hz 1 A 0.35 V 0.35 Ω 30 Hz 1 A 0.34 V 0.34 Ω

100 Hz 1 A 0.33 V 0.33 Ω 300 Hz 1 A 0.34 V 0.34 Ω

1000 Hz 1 A 0.33 V 0.33 Ω 3000 Hz 1 A 0.43 V 0.43 Ω

10000 Hz 1 A 0.94 V 0.94 Ω

Expected cell impedance magnitude is between 0.06 Ω and 0.1 Ω depending on

frequency [40]. With three cells in series and two in parallel, impedance of the battery

pack should be 1.5 times this value, or 0.09-0.15 Ω. The impedance reported in Table 5.3

is over three times the expected value. Very high series impedance is an indicator of poor

battery health [60]; further testing revealed that the battery is indeed at the end of its life.

It could not sustain even a moderate current draw for more than a few minutes. This bat-

tery was used to complete the step response test in Section 5.4, which requires only brief

current draws, but a dc supply was used for the repeated draw test in Section 5.5.

5.4 Step Response

The purpose of the step response test is to make sure the choice of 2 is sufficient

to keep inductor current from ringing when termv changes abruptly. As the capacitor in

this system is not large enough to provide transient energy, the difference between load

102

power and the average current through the top converter FET must be supplied by the dc

source (the battery).

A load step was generated by switching a load resistor into and out of the voltage

bus. The load resistor had a measured resistance of 1.41 Ω. A FET was used as the switch

to get a sharp, clean step. Initial UC voltage was 6 V and battery voltage was 12 V. The

UC voltage is set low in order to evaluate worst-case behavior. Voltages and currents

were measured using an oscilloscope set to 2 ms per division and 25 kHz sampling rate.

The same load step was applied to a switched model of the system. The model was set up

using the initial UC and battery voltages above. Parameter battR was set to the average

battery resistance at frequencies between 100 and 1000 Hz, 0.34 Ω.

Figure 5.4 plots Li , termv and batti after the 1.41 Ω load resistor was switched into

the bus. Measurements matched the predictions well. Inductor current Li follows a sec-

ond-order trajectory with a small amount of overshoot. This overshoot was predicted by

the simulation; it can be removed if needed through further controller tuning. With the

present tuning, no load transient during normal operation will make Li ring or become

untracked from refi . All variables are close to their final values after 15 ms, adequate for

the application and similar to what was predicted for the 100 kW converter.

Figure 5.5 plots Li , termv and batti when the load resistor is abruptly removed from

the bus. The measured step down was initiated about 5 s after the load resistor was con-

nected to the bus. The switched model was run under the same conditions — load was

applied and then removed 5 s later, and responses were recorded when the load was re-

moved. The model and measured system have different state values just before the step,

but after the step their trajectories follow similar paths. Inductor current follows a second-

order trajectory with slight overshoot of the final value and no ringing.

103

0 5 10 15 20 25

0

5

10

load

i (A

)

SimMeas

0 5 10 15 20 25

0

10

20

i L (A

)

SimMeas

0 5 10 15 20 2510

11

12

v term

(V

)

SimMeas

0 5 10 15 20 25

0

2

4

i batt (

A)

Time (ms)

SimMeas

Figure 5.4. Simulated and measured response to step addition of 1.41 Ω load.

104

0 5 10 15 20 25

0

5

10

load

i (A

)SimMeas

0 5 10 15 20 25-10

0

10

20

i L (A

)

SimMeas

0 5 10 15 20 25

11

12

13

v term

(V

)

SimMeas

0 5 10 15 20 25-4

-2

0

2

i batt (

A)

Time (ms)

SimMeas

Figure 5.5. Simulated and measured response to step removal of 1.41 Ω load. Time t = 0 is set to the

instant when the load was removed.

5.5 Repeated Draw Test

In this test, the dc load is commanded to run the following program:

1) Ramp from 0 to 7.5 A in 0.2 s.

2) Hold at 7.5 A for 9.8 s.

3) Ramp from 7.5 to 0 A in 0.2 s.

105

4) Hold at 0 A for 29.8 s.

5) Repeat.

This signal has period 40 s and draws the same average current as a 7.5 A, 25% duty

pulse train. The xPC Target was also used to program the dc load and store measured

data, in addition to providing system control and hardware protection. Additional hard-

ware was used to condition the measured currents and voltages and feed them into the

A/D; schematics are in Appendix C. For these tests the UC is initialized to 8.03 V and

bus voltage is set to 12.07 V no-load. Simulation results are provided by the averaged

nonlinear model presented in Section 5.2.

Because of the battery’s high series impedance and inability to sustain a current

draw, the battery was replaced by the dc source shown in Figure 5.6. A diode prevents

reverse current from flowing into the dc supply. The voltage across the diode varies with

the current flowing through it, even with the strong bias provided by the 3 Ω ballast resis-

tor. In addition, the bench supply does not perfectly regulate output voltage as load cur-

rent varies. These nonidealities warrant characterization if the system model is to match

the physical system.

dc supply 3 Ω vtermvballast

Rbatt

ibatt

Figure 5.6. Dc source used for the repeated draw test.

106

As the series resistance battR is fixed, the dc supply can be modeled by a current-

dependent voltage source with fixed series resistance. The resistors implementing battR

measured 0.176 Ω with lead wires included. Table 5.4 lists the voltage across the ballast

resistor, ballastv , as current batti varied from 0 to 6 A. Voltage measurements were taken

when the diode was warm, as it will be warm during the repeated draw test. Figure 5.7 is

a graph of the table data. The graph generally has the nonlinear I-V characteristic of a

diode. A lookup table implements the current-dependent voltage source in the averaged

nonlinear model.

Table 5.4. Voltage across 3 Ω ballast resistor at specific ibatt current values.

batti ballastv

0 A 12.07 V 0.5 A 12.06 V 1 A 12.047 V

1.5 A 12.026 V 2 A 12.012 V 3 A 12.006 V 4 A 11.995 V 5 A 11.983 V 6 A 11.979 V

0 1 2 3 4 5 611.96

11.98

12

12.02

12.04

12.06

12.08

ibatt

(A)

v balla

st (

V)

Figure 5.7. Plot of the data in Table 6.4.

107

Figure 5.8 plots measured and predicted termv , batti and Li in response to the re-

peated load draws. Data was filtered somewhat and sampled every 0.2 s, removing the

switching ripple from the measurement. Measured data matches predictions very well

after about five loading cycles, and are nearly identical after 350 s. The active-parallel

system is effective at smoothing battery current — load current is 7.5 A peak, yet battery

current never exceeds 4 A. Figure 5.9 shows inv measured over a longer time interval,

along with the prediction. Here the measured value diverges from the prediction by about

half a volt after several loading cycles, but the two match after around 2400 s (40 min-

utes). Based on the data presented here, the likely reason for the divergence is that the

offset between reference current refi and per-cycle average inductor current Li was not

initialized correctly for the physical system. Since Li is more negative than predicted by

the model, the offset was likely too small. The more negative Li raises inv until the charg-

ing loop compensates. The charging loop integrator slowly brings inv down until it cycles

about the reference value. UC voltage stays within its physical bounds over the entire

time interval, and the charging loop ultimately rejects the disturbance without impacting

the ability of the power-distributing loop to supply legitimate load transients. Line distur-

bances from the dc source, where supply voltage varied nonlinearly due to the series di-

ode, are also rejected.

108

0 50 100 150 200 250 300 350 400 450 500

11.2

11.4

11.6

11.8

12v te

rm (

V)

Measured Simulated

0 50 100 150 200 250 300 350 400 450 5000

1

2

3

4

5

i batt (

A)

Measured Simulated

0 50 100 150 200 250 300 350 400 450 500

-5

0

5

10

15

Time (s)

i L (A

)

Measured Simulated

Figure 5.8. vterm(t), ibatt(t) and iL(t) of measured scaled-down combined source, compared to simulated.

0 500 1000 1500 2000 2500

6.5

7

7.5

8

8.5

9

Time (s)

v in (

V)

Measured Simulated vuc,ref

Figure 5.9. vin(t) measured scaled-down combined source, compared to simulated.

109

5.6 Summary

The hardware demonstration proves that the active-parallel system is capable of

reducing peak battery current by smoothing the load peaks. The outer loop controller

provides rejection of disturbances which would otherwise cause net flows of energy into

or out of the UC. Furthermore, the LPF and charging loop are effective at keeping Li

trajectory well-behaved and at compensating for the offset between refi and Li inherent to

the PCM process. In all tests the measured voltages and currents closely followed those

predicted by the switched and averaged large-signal models, proving the models are a

valid means to predict system behavior. As large-signal model results are congruent with

predictions made by the design equations small-signal models, these experimental results

indirectly reinforce the validity of these tools as well.

110

CHAPTER 6

CONCLUSIONS

This thesis presented and analyzed the use of a shaped-impedance controller to

control a dc-dc converter which decouples bulk capacitance from a dc voltage bus. Com-

plete combined power sources were developed for an electric vehicle power source and

for a desktop computer processor VRM. Employing a decoupled capacitor reduced the

size and/or weight of the power source needed to meet a given load requirement, whether

it was used in place of additional batteries or additional bus capacitance.

Design equations and large-signal dynamic models were developed for each sys-

tem. Linearized small-signal models were developed for the vehicle application to enable

this system to be analyzed in the frequency domain. These equations and models provide

a systematic way to tune the controller and select power-handling components. Together

the models give a good picture of overall system behavior. A scaled-down combined

source for a vehicle was constructed and tested. There was generally good agreement

between design equations, models, and measured results.

The controllers for both applications set the decoupled capacitor’s reference cur-

rent using a high-pass filtered and scaled measurement of bus voltage. The controller for

the vehicle application kept battery power and UC energy depletion from exceeding an

amount proportional to a step change in bus voltage. The charging loop kept UC charge

level within its bounds in the face of net loss, offset between reference and average in-

ductor currents, and slowly-varying disturbances in bus voltage. Design equations and the

switched VRM model predicted that decoupled bulk capacitance could be integrated ef-

111

fectively into a VRM design. Processor voltage bus capacitance could be substantially

reduced with little impact on voltage regulation or efficiency.

Future work can involve further optimizing the controller developed for the vehi-

cle application. Small-signal models of the system for the vehicle application revealed

that there is a large frequency region over which neither bus voltage nor UC charge is

tightly regulated. UC currents flowed opposite the direction intended within this band.

Making this crossover region smaller may allow better low-frequency disturbance rejec-

tion, further decreasing the UC size. Simply raising the filter order will decrease phase

margin appreciably, so this direction does not look promising. A nonlinear filter in the

charging loop has the potential to narrow the transition band without hurting phase mar-

gin. It would also be worth investigating the use of power-dense batteries as the transient

energy source, as these devices are more energy-dense than UCs and continue to become

more power-dense. The charging loop would need to be redesigned in order to properly

maintain the charge level of these batteries.

The VRM design looks promising as a way to reduce bus capacitor size without

harming efficiency or adding too much system complexity. Future work includes per-

forming further analysis and fabricating a prototype. It is also worth seeing if series-input

parallel-output (SIPO) SCM-controlled phases could be employed to carry the transient

current. Voltage droop would be implemented using adaptive voltage positioning to mod-

ify the SCM reference voltage. Bus voltage could be dropped from 12 V nominal to 0.8 V

nominal using five transient-carrying phases operating at a duty ratio near 0.5. The first

converter stage would no longer be needed, eliminating a point of failure and potentially

increasing efficiency.

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APPENDIX A

SCRIPTS TO EVALUATE SMALL-SIGNAL TRANSFER FUNCTIONS

In Chapter 3, system stability was determined by evaluating small-signal models

across a range of system operating points. This section details the scripts which per-

formed this work.

A.1 Main Script

% nominal or constant parameters % These values are for the 100 kW converter; other values are substituted % in for the scaled-down converters L = 500e-6; C = 18000e-6; R = 1.6; Cuc = 44.16; Vin = 180; Voc = 400; Rbatt = 0.15; Ibatt = 30; %relevant for 2-state plant only Resr = 0.00314; Rin = (17.2+1.5+2.4)*1e-3; T = 100e-6; %switching period Ma_r = 0.7; %relationship of Ma to off-time slope of inductor current M2 = (400-180)/L; % abs. value of off-time slope of inductor current Kp = 65; Kchg = 0.4; Kichg = .00015; Kdchg = 0; tau1 = 3.71; tau2 = 0.0291; D_filter = 10; vin_corner = 200; %nominal parameters which take on a range of values R_v = [1.6 16 1e6]; Vin_v = [140:20:320]; Voc_v = [300:20:420]; Rbatt_v = [0.1 0.15 0.75]; Ibatt_v = [0 14 147]; % run the sub-scripts iL_dir = 1; iteration_script_2state_vcloop; twostate_result = PMs; iL_dir = -1; iteration_script_2state_vcloop;

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twostate_result = [twostate_result;PMs]; iteration_script_3state_bothloops; threestate_result = PMs; [mag,idx] = max(twostate_result(:,[5 6 15 17])) [mag,idx] = max(twostate_result(:,8:14)) [mag,idx] = max(threestate_result(:,[5 6 20 22 24 26])) [mag,idx] = max(threestate_result(:,8:19))

A.2 Scripts for Two-State Transfer Functions

A.2.1 iteration_script_2state_vcloop.m

%Script to iterate through all combinations of variable parameters for %2-state plant, Rin and Resr, vc-to-iref loop with LPF only % calculated, but fixed, parameters M2 = (Voc-Vin)/L; % abs. value of off-time slope of inductor current Ma = Ma_r*M2; %initialize storage array q = 0; clear PMs; PMs = 0; clc; for m = 1:length(Vin_v) Vin = Vin_v(m); for n = 1:length(Voc_v) Voc = Voc_v(n); for o = 1:length(R_v); R = R_v(o); for p = 1:length(Rbatt_v) Rbatt = Rbatt_v(p); for w = 1:length(Ibatt_v) Ibatt = Ibatt_v(w); Vc = Voc-Ibatt*Rbatt; if Vin < Vc %calculated nominal parameters clear IL; Iout = Vc/R-Ibatt; IL_nom = Iout*Vc/Vin; IL = fzero(@(IL) ... lossy_IL_fcn2(IL,Iout,Rin,Vin,Vc),IL_nom); if iL_dir < 0 IL = -IL; end D = 1 - (Vin-IL*Rin)/(Vc); Dp = 1 - D; Req = 1/(1/R+1/Rbatt); q = q+1; %generate transfer functions tfs_2state_fast_vc_loop;

114

%find PM and crossover frequency of each tf, store in a %vector fprintf('Vin %5.3g, Voc %5.3g, R %5.3g, Rbatt %5.3g, Ibatt %5.3g, Vc %5.3g \n',Vin,Voc,R,Rbatt,Ibatt,Vc) yidx = 8; PMs(q,19) = 0; PMs(q,1) = Vin; PMs(q,2) = Voc; PMs(q,3) = R; PMs(q,4) = Rbatt; PMs(q,5) = Ibatt; PMs(q,6) = Vc; % [GM, PM, GMfreq, crossfreq] = margin(open_iref_il); rr = rlocus(open_iref_il,[0 1]); PMs(q,7) = max(real(rr(:,1))); %see if open-loop iref-to-il is unstable PMs(q,8) = max(real(rr(:,2))); %see if closed-loop iref-to-il is unstable PMs(q,yidx) = isOpenLoopUnstable(Hvr); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Hvu); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Hvo); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Hvl); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jvu); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jvo); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jvl); yidx = yidx+1; [mag,freq] = get_max_mag(Jvo); PMs(q,yidx) = mag; yidx = yidx+1; PMs(q,yidx) = freq; yidx = yidx+1; [mag,freq] = get_max_mag(Jvl); PMs(q,yidx) = mag; yidx = yidx+1; PMs(q,yidx) = freq; yidx = yidx+1; end end end end end end

A.2.2 tfs_2state_fast_vc_loop.m

% Small-signal transfer functions for current-controlled converter, no % outer loop, battery connected to output, Vin treated as constant on a % fast scale, converter losses Rin and Req included. % Fixed tfs 6/11 and added input for perturbed Voc. % clear Gvd Gvv Gvl Gid Giv Gil Fm Fin Fout Hvr Hvv Hvl Fll Jvl Jvv outer_loop_gain;

115

% linearized perturbed transfer functions of plant, with no control applied Gvd = tf([-L*IL -Rin*IL+Dp*Vc],... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %control-to-Vc tf Gvu = tf(Dp,... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %vin-to-Vc tf Gvo = tf([L/Rbatt Rin/Rbatt],... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %iload-to-Vc tf Gvl = tf([-L -Rin],... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %iload-to-Vc tf Gid = tf([C*Vc Dp*IL+Vc/Req],... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %control-to-IL tf Giu = tf([C 1/Req],... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %vin-to-il tf Gio = tf(-Dp/Rbatt,... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %vin-to-il tf Gil = tf(Dp,... [L*C (C*Rin+L/Req) Dp^2+Rin/Req]); %iload-to-il tf % gains and relating iref to il Fm = 1/(Ma*T); Fin = (2*D-1)*T/(2*L); Fout = Dp^2*T/(2*L); % iref-to-il gain Hir = Fm*Gid/(1+Fm*Gid+Gvd*Fm*Fout); %iref-to-il tf % closed inner loop transfer functions Hvr = Fm*Gvd/(1+Fm*Gid+Gvd*Fm*Fout); %iref-to-vc tf Hvu = (Gvu*(1+Fm*Gid) - (Giu+Fin)*Fm*Gvd)/... (1+Fm*Gid+Gvd*Fm*Fout); %vin-to-vc tf Hvo = (Gvo*(1+Fm*Gid) - Gio*Fm*Gvd)/... (1+Fm*Gid+Gvd*Fm*Fout); %voc-to-vc tf Hvl = (Gvl*(1+Fm*Gid - Gil*Fm*Gvd))/... (1+Fm*Gid+Gvd*Fm*Fout); %iload-to-vc tf % remove pole-zero pairs that cancel from the H's Hvr = cancelPZPairs(Hvr,0.05); Hvu = cancelPZPairs(Hvu,0.05); Hvo = cancelPZPairs(Hvo,0.05); Hvl = cancelPZPairs(Hvl,0.05); % outer loop controller TF Fll = Kp*tf(1,[tau2 1]); %tau1 = HPF time constant, tau2 = LPF time constant % check loop gain of outer loop - it is desirable for the outer loop to be % stable when open; at minimum this facilitates loop gain measurements outer_loop_gain = Hvr*Fll; %closed outer loop transfer functions Jvu = Hvu/(1+Hvr*Fll); %vin-to-vc tf Jvo = Hvo/(1+Hvr*Fll); %voc-to-vc tf Jvl = Hvl/(1+Hvr*Fll); %iload-to-vc tf % remove pole-zero pairs that cancel from the J's Jvu = cancelPZPairs(Jvu,0.05); Jvo = cancelPZPairs(Jvo,0.05); Jvl = cancelPZPairs(Jvl,0.05);

116

A.3 Scripts for Three-State Transfer Functions

A.3.1 iteration_script_3state_bothloops.m

%Script to iterate through all combinations of variable parameters for %3-state plant, Rin, no Resr, both vc-to-iref and vin-to-iref loops % calculated, but fixed, parameters M2 = (Voc-Vin)/L; % abs. value of off-time slope of inductor current Ma = Ma_r*M2; %initialize storage array q = 0; clear PMs; PMs = 0; clc; for m = 1:length(Vin_v) Vin = Vin_v(m); for n = 1:length(Voc_v) Voc = Voc_v(n); for o = 1:length(R_v); R = R_v(o); for p = 1:length(Rbatt_v) Rbatt = Rbatt_v(p); Vc = Voc*R/(R+Rbatt); if Vin < Vc %calculated nominal parameters clear IL; IL_nom = Vc^2/(R*Vin); IL = fzero(@(IL) ... lossy_IL_fcn(IL,0,Rbatt,Rin,R,Vin,Vc,Kp),IL_nom); D = 1 - (Vin-IL*Rin)/(Vc); Dp = 1 - D; Req = 1/(1/R+1/Rbatt); q = q+1; %generate transfer functions tfs_3state_plant_and_chg_loop; %find PM and crossover frequency of each tf, store in a %vector fprintf('Vin %5.3g, Voc %5.3g, R %5.3g, Rbatt %5.3g, Vc %5.3g \n',Vin,Voc,R,Rbatt,Vc) yidx = 8; PMs(q,27) = 0; PMs(q,1) = Vin; PMs(q,2) = Voc; PMs(q,3) = R; PMs(q,4) = Rbatt; PMs(q,5) = Vc; % [GM, PM, GMfreq, crossfreq] = margin(open_iref_il); rr = rlocus(open_iref_il,[0 1]); PMs(q,6) = max(real(rr(:,1))); %see if open-loop iref-to-il is unstable PMs(q,7) = max(real(rr(:,2))); %see if closed-loop iref-to-il is unstable PMs(q,yidx) = isOpenLoopUnstable(Hvr); yidx = yidx+1;

117

PMs(q,yidx) = isOpenLoopUnstable(Hvo); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Hvl); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Hur); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Huo); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Hul); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jvr); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jvo); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jvl); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jur); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Juo); yidx = yidx+1; PMs(q,yidx) = isOpenLoopUnstable(Jul); yidx = yidx+1; [mag,freq] = get_max_mag(Jvo); PMs(q,yidx) = mag; yidx = yidx+1; PMs(q,yidx) = freq; yidx = yidx+1; [mag,freq] = get_max_mag(Jvl); PMs(q,yidx) = mag; yidx = yidx+1; PMs(q,yidx) = freq; yidx = yidx+1; [mag,freq] = get_max_mag(Juo); PMs(q,yidx) = mag; yidx = yidx+1; PMs(q,yidx) = freq; yidx = yidx+1; [mag,freq] = get_max_mag(Jul); PMs(q,yidx) = mag; yidx = yidx+1; PMs(q,yidx) = freq; yidx = yidx+1; end end end end end

A.3.2 tfs_3state_plant_and_chg_loop.m

% Small-signal transfer functions for current-controlled converter, no % outer loop, battery connected to output, Vin treated as constant on a % fast scale. Main difference between this model and a regular boost % converter is that R is replaced by Req = R||Rbatt. % Transfer functions only; this file is meant to be run as a script. % Parameters need to be loaded in the workspace before this script is run. % % linearized perturbed transfer functions of plant, with no control applied % uc is included, il points toward c % input-to-vc tfs Gvd = tf([Dp*Cuc*Vc 0],[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); Gvo = tf([L*Cuc/Rbatt Cuc*Rin/Rbatt 1/Rbatt],[L*C*Cuc ... L*Cuc/Req+C*Cuc*Rin C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); Gvl = tf([-L*Cuc -Cuc*Rin -1],[L*C*Cuc ... L*Cuc/Req+C*Cuc*Rin C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); %input-to-vin tfs Gud = tf([-C*Vc -Vc/Req],[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); Guo = tf(Dp/Rbatt,[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); Gul = tf(-Dp,[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]);

118

%input-to-il tfs Gid = tf([C*Cuc*Vc Cuc*Vc/Req 0],[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); Gio = tf([-Cuc*Dp/Rbatt 0],[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); Gil = tf([Cuc*Dp 0],[L*C*Cuc L*Cuc/Req+C*Cuc*Rin ... C+Cuc*Dp^2+Cuc*Rin/Req 1/Req]); % gains and relating iref to il Fm = 1/(Ma*T); Fin = (2*D-1)*T/(2*L); % Fin = (1-2*D)*T/(2*L); Fout = Dp^2*T/(2*L); % iref-to-il gain with current loop open open_iref_il = Fm*Gid/(1+Fm*Fin*Gud+Fm*Fout*Gvd); open_iref_il = cancelPZPairs(open_iref_il,.005); % with current loop closed Hir = Fm*Gid/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); % new closed inner-loop transfer functions with new current loop model % input-to-vc tfs Hvr = Fm*Gvd/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); Hvo = (Gvo-Gvd*Fm*(Gio+Fin*Guo))/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); Hvl = (Gvl-Gvd*Fm*(Gil+Fin*Gul))/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); % input-to-vin tfs Hur = Fm*Gud/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); Huo = (Guo-Fm*Gud*(Gio+Fout*Gvo))/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); Hul = (Gul-Fm*Gud*(Gil+Fout*Gvl))/(1+Fm*Gid+Fm*Fin*Gud+Fm*Fout*Gvd); % remove pole-zero pairs that cancel from the H's Hvr = cancelPZPairs(Hvr,0.05); Hvo = cancelPZPairs(Hvo,0.05); Hvl = cancelPZPairs(Hvl,0.05); Hur = cancelPZPairs(Hur,0.05); Huo = cancelPZPairs(Huo,0.05); Hul = cancelPZPairs(Hul,0.05); Hir = cancelPZPairs(Hir,0.05); % control gains for vc and vin feedback loops % COMMENT these out when running Juo_only routine BPF_Kp = Kp*tf([tau1 0],[tau1*tau2 tau1+tau2 1]); %tau1 = HPF time constant, tau2 = LPF time constant Kc = tf([Kchg Kichg],[1 0]); % check loop gain of outer loop - it is desirable for the outer loop to be % stable when open; at minimum this facilitates loop gain measurements outer_loop_gain = Hvr*BPF_Kp; % tfs with both voltage feedback loops closed - 6 total % input-to-vc tfs Jvr = -Hvr*Kc/(1-Hur*Kc+Hvr*BPF_Kp); %vuc_ref-to-vc tf Jvo = (Hvo*(1-Hur*Kc)+Hvr*Huo*Kc)/(1-Hur*Kc+Hvr*BPF_Kp); Jvl = (Hvl*(1-Hur*Kc)+Hvr*Hul*Kc)/(1-Hur*Kc+Hvr*BPF_Kp); % input-to-vin tfs Jur = -Hur*Kc/(1-Hur*Kc+Hvr*BPF_Kp); %vuc_ref-to-vin tf Juo = (Huo*(1+Hvr*BPF_Kp)-Hur*Hvo*BPF_Kp)/(1-Hur*Kc+Hvr*BPF_Kp); Jul = (Hul*(1+Hvr*BPF_Kp)-Hur*Hvl*BPF_Kp)/(1-Hur*Kc+Hvr*BPF_Kp);

119

% remove pole-zero pairs that cancel from the J's Jvr = cancelPZPairs(Jvr,0.05); Jvo = cancelPZPairs(Jvo,0.05); Jvl = cancelPZPairs(Jvl,0.05); Jur = cancelPZPairs(Jur,0.05); Juo = cancelPZPairs(Juo,0.05); Jul = cancelPZPairs(Jul,0.05);

A.4 Helper Functions

The scripts above call a few helper functions. A description of the functions is as follows:

sys2 = cancelPZPairs(sys,eps). When MATLAB divides one tf object

by another, the quotient contains poles and zeros which numerically cancel, but

are present nonetheless. These extraneous terms cause problems when the quo-

tient is further manipulated. The function cancelPZPairs removes pole/zero

pairs from sys which are within magnitude eps of each other, and returns the re-

sult in sys2.

[ff,maxpole] = isOpenLoopUnstable(sys). This function sees if any

poles of sys are not in the OLHP, and marks ff accordingly. The angular fre-

quency of largest (fastest) unstable pole is returned in maxpole.

[mag,freq] = get_max_mag(sys). This function returns the peak magnitude

of the Bode plot of sys, along with the frequency (in Hz) at which the peak oc-

curs.

120

APPENDIX B

EXPANDED LARGE-SIGNAL SIMULINK BLOCKS AND SET-UP CODE

B.1 Switched Nonlinear Model for Vehicle

B.1.1 Expanded Controller Blocks

The parent for these blocks is the Controller detailed in Section 4.1.1. The header

of each sub-figure in Figure B.1 shows the name of the expanded block, along with its

location in the model hierarchy.

TF is (F1(s)-1)(F2(s) = -s*tau1/((s*tau1+1)(s*tau2+1)) tau1 = low cutoff

tau2 = high cutoff

Out1

1

Low corner

In1 Out1High corner

In1 Out1In1

1

nonlin_switched_10kHz/Controller/BPF

Figure B.1. Expanded Controller blocks from switched model.

121

Out1

1

Integrator

1s

1/tau1

-K-

In1

1

nonlin_switched_10kHz/Controller/BPF/Low corner

Figure B.1. (Continued.)

Out1

1

Integrator

1s

1/tau2

-K-

In1

1

nonlin_switched_10kHz/Controller/BPF/High corner

Figure B.1. (Continued.)

122

Out1

1

Integrator

1s

Hz to rad

-K-

Corner freq

-K-

In1

1

nonlin_switched_10kHz/Controller/Low corner

Figure B.1. (Continued.)

Out

1Subtract1

MinMax

max

Gain

-1

CompareTo Zero

>= 0

85% Duty Ratio Limit

-

2

+

1

nonlin_switched_10kHz/Controller/Comparator

Figure B.1. (Continued.)

123

B.1.2 Set-Up Code for Switched Nonlinear Model

% nominal or constant parameters % These parameters are for the 100 kW converter. L = 500e-6; C = 18000e-6; R = 1.6; Cuc = 44.16; Vin = 180; Vc = 400; Voc = Vc; Rbatt = 0.15; Resr = 0.00314; Rin = (17.2+1.5+2.4)*1e-3; T = 100e-6; %sampling period Ma_r = 0.7; %relationship of Ma to off-time slope of inductor current Kp = 65; Kchg = 0.4; Kichg = .00015; Kdchg = 0; tau1 = 3.71; %4.167; tau2 = 0.0291; %.001478; D_filter = 10; vin_corner = 2000; % %nominal parameters which take on a range of values % R_v = [1.3 13 1000]; % Vin_v = [5 5.9:1:12.9]; % Vc_v = [9:1:13]; % Rbatt_v = [0.1 1 10000]; % simulation parameters Pload_step = 1e5; s_t = 1e-6; %rise time of step r_t = 0.2; %length of rise time of ramp %Calculated parameters % clear Vterm; % Vterm = fzero(@(Vterm) Vterm_fcn(Vterm,Vin,Voc,Rbatt,Kp,T,L,Ma_r),Voc); Vuc_ref = Vin; Vterm = Vc; Dp = Vin/Vterm; D = 1 - Dp; M1 = Vin/L; %slope of rising inductor current; is equal to (Vin-Vswitch)/L in boost converter M2 = (Vterm-Vin)/L; %in lossless boost converter Ma = M2*Ma_r; % find initial states of inductor, capacitor, chg loop integrator h0T = get_f0T_handle(Voc,Vin,1e6,Rin,Resr,Rbatt,L,C,D,T); x0 = fsolve(h0T,[-Vin*D*T/(2*L);Voc],optimset('TolFun',1e-10)); Ilmin = x0(1); Vcmax = x0(2); h0DT = get_f0DT_handle(Voc,Vin,1e6,Rin,Resr,Rbatt,L,C); [ttt,xDT] = ode15i(h0DT,[0,D*T],[Ilmin;Vcmax],[0;0]); Iref_init = xDT(end,1)+Ma*D*T; Ibatt_min = (Vterm-Vcmax)/Rbatt; Iload_nom = (Voc-Vterm)/Rbatt; Iout_max = Pload_step/Voc+20;

124

Iload_step = Pload_step/Voc;

Helper functions used by fsolve and ode15i function h = get_f0DT_handle(Voc,Vin,R,Rin,Resr,Rbatt,L,C) h = @f0DT; function err = f0DT(t,x,xp) err = [0;0]; Vout = x(2) + xp(2)*C*Resr; err(1) = L*xp(1) - (Vin-Rin*x(1)); err(2) = C*xp(2) - ((Voc-Vout)/Rbatt-Vout/R); end end

function h = get_fDT_T_handle(Voc,Vin,R,Rin,Resr,Rbatt,L,C) h = @fDT_T; function err = fDT_T(t,x,xp) err = [0;0]; Vout = x(2) + xp(2)*C*Resr; err(1) = L*xp(1) - (Vin-Rin*x(1)-Vout); err(2) = C*xp(2) - (x(1)+(Voc-Vout)/Rbatt-Vout/R); end end

function h = get_f0T_handle(Voc,Vin,R,Rin,Resr,Rbatt,L,C,D,T) h = @f0T; function err = f0T(x0) % integrates systems f0DT and FDT_T from time 0 to T % initialize vars and function handles err = [0;0]; hDT = get_f0DT_handle(Voc,Vin,R,Rin,Resr,Rbatt,L,C); hT = get_fDT_T_handle(Voc,Vin,R,Rin,Resr,Rbatt,L,C); [t,x] = ode15i(hDT,[0,D*T],x0,[0;0],odeset('MaxStep',T/100)); [t2,x2] = ode15i(hT,[D*T,T],[x(end,1);x(end,2)],[0;x(end,1)],odeset('MaxStep',T/100)); % find area under Vc(t) t_shift = [0;t;t2(1:end-1)]; ddt = [t;t2]-t_shift; vc_area = [x(:,2)' x2(:,2)']*ddt; % These metrics are valid when the converter is sourcing no power. % Note that the square of a small number is even smaller - fsolve % tolerance needs to be very small for these equations to be % useful. err(1) = 2*(x0(1)+x(end,1)-Voc/R)^2 + (x0(1)-x2(end,1))^2; err(2) = 1000*(vc_area-Voc*T*R/(R+Rbatt))^2 + (x0(2)-x2(end,2))^2; end end

125

B.2 Averaged Nonlinear Model for Vehicle

B.2.1 Expanded Model

This section contains the averaged nonlinear model with significant blocks ex-

panded. The overview drawing from Section 4.2 is reprinted here for clarity. The header

of each sub-figure in Figure B.2 shows the name of the expanded block, along with its

location in the model hierarchy. Individual function blocks implement the equations

given in Section 4.2.

126

load R

Vc

Pload_desRiref_to_iL

Vin

i_ref

v_c

dp

i_L

ibatt, il=-iuc, iref

i_uc

-u(1)

i_c

Vin

i_L

Vc

R

i_c

dp

Voc

ibatt

Voc, Vc, Vin_state,

Vin_term

Vin_term

f(u)

UC energy

Terminator1

TerminatorRepeating

Sequence1

Product Integrator2

1

s

Integrator1

1

s

Integrator

1

s

From

Workspace

sine_vec

Dp

Controller

Vin

Vciref

100 kW pulse

? ? ?

1/Cuc

-K-

1/C

-K-Vc

Vin

nonlinear_avgd_model_lossy2_100kW

Figure B.2. Averaged nonlinear model of combined power source for vehicle.

127

iref

1

Vuc,ref

-C-

P

Kp

Kichg

-K-

Kchg

-K-

Integrator1

1s

BPF

In1 Out1

Vc

2

Vin

1

nonlinear_avgd_model_lossy2_100kW/Controller

Figure B.2. (Continued.)

ibatt

4

Voc

3

dp

2

i_c

1

ic_fcn

f(u)

d'

Vin

i_L

Vc

Voc

R

i_c

Dp

ibatt

Voc1

ibatt Voc

Req

f(u)

Memory2

Memory1

Memory

R

4

Vc

3

i_L

2

Vin

1

nonlinear_avgd_model_lossy2_100kW/i_c

Figure B.2. (Continued.)

128

ibatt

2

Dp

1

iload

f(u)

ibatt_fcn

f(u)

d'

f(u)

i_c

6

R

5

Voc

4

Vc

3

i_L

2

Vin

1

nonlinear_avgd_model_lossy2_100kW/i_c/d'

Figure B.2. (Continued.)

Voc

1

Integrator

1s

Gain

-Kbatt

ibatt

1

nonlinear_avgd_model_lossy2_100kW/i_c/Voc1

Figure B.2. (Continued.)

129

i_L

1

iref-to-il

f(u)

d

1-u(1)

dp

4

v_c

3

i_ref

2

Vin

1

nonlinear_avgd_model_lossy2_100kW/iref_to_iL

Figure B.2. (Continued.)

R

1

Fcn

u(1)^2/u(2)

Pload_des

2

Vc

1

nonlinear_avgd_model_lossy2_100kW/load R

Figure B.2. (Continued.)

130

B.2.2 Set-Up Code for Averaged Nonlinear Model

% nonlinear averaged model setup % These parameters are for the 100 kW converter. % physical parameters L = 500e-6; C = 18000e-6; Cuc = 44.16; %3000*2.5/320; Voc_init = 400; Vuc_init = 266.2; Resr = 0.00314; Rin = (17.2+1.5+2.4)*1e-3; Rbatt = 0.15; batt_ah = 147; T = 1e-4; Ma_r = 0.7; Pmax = 1e5; %controller parameters tau1 = 3.71; %HPF cutoff tau2 = 0.0291; %.001478; D_filter = 10; Kp = 65; Kchg = .4; %.1; Kichg = 0.00015; %.00001; Kdchg = 0; %100; %calculated parameters Kbatt = 0; %(12.6-9)/(3600*batt_ah); uc_soc_init = .55; Vuc_ref = sqrt(abs(-(1-uc_soc_init)*(.45*Voc_init)^2-uc_soc_init*(.8*Voc_init)^2)); M2 = (400-180)/L; % abs. value of off-time slope of inductor current Ma = Ma_r*M2; Dp = Vuc_ref/Voc_init; D = 1-Dp; Iref_init = (1/2)*(D^2*Vuc_ref*T/(2*L) + Dp^2*Voc_init*T/(2*L)) + Ma*D*T % create sinusoid time_vec = [0:1:14400]; sine_vec = 20*sin(2*pi*time_vec./2000); sine_vec = [time_vec;sine_vec]';

B.3 Switched Model for VRM

B.3.1 Expanded Model

This section contains the switched model of the VRM system. The system over-

view drawing from Section 4.3 is reprinted here for clarity. The header of each sub-figure

in Figure B.3 shows the name of the expanded block, along with its location in the model

hierarchy.

131

v ref

vzero

dc pcm process

IL_1

IL_2

IL_3

IL_4

Iref/4

Scope out

q(t)_1

q(t)_2

q(t)_3

q(t)_4

ac pcm process

IL_1

IL_2

Iref/2

Scope out

q(t)_1

q(t)_2

Vin, Vout

Outer loopcontroller

sum_IL_s

Vout

Vzero

sum IL f

Iref_s

Iref_f

Load R

Out1

Irefs, ILs

Divide

Dc phase 4

vin

iout

q(t)

vc

iL

iin

Dc phase 3

vin

iout

q(t)

vc

iL

iin

Dc phase 2

vin

iout

q(t)

vc

iL

iin

Dc phase 1

vin

iout

q(t)

vc

iL

iin

BusCapacitor

i_c

vout

vc

Ac phase 2

vin

iout

q(t)

vc

iL

iin

Ac phase 1

vin

iout

q(t)

vc

iL

iin

2 V source

iinVin

iout

nonlin_switched_slowfast

Figure B.3. Switched model for VRM application with significant blocks expanded.

132

Iref_f

2

Iref_s

1

iref_s/4

1/4

iref_f/2

1/2

iL/4

1/4

iL/2

1/2

Native AVP1

iL

iref

ioff

Native AVP

iL

iref

ioff

LPF

In1 Out1

Kp/4

Kp

BPF

In1 Out1

sum_IL_f

4

Vzero

3

Vout

2

sum_IL_s

1

Vzero iref_s

iref_f

nonlin_switched_slowfast/Outer loop controller

Figure B.3. (Continued.)

133

tau1 = low cutofftau2 = high cutoff

TF is (F1(s)-1)(F2(s) = -s*tau1/((s*tau1+1)(s*tau2+1))

Out1

1

Low corner

In1 Out1High corner

In1 Out1In1

1

nonlin_switched_slowfast/Outer loop controller/BPF

Figure B.3. (Continued.)

Out1

1

Integrator

1s

1/tau1

-K-

In1

1

nonlin_switched_slowfast/Outer loop controller/BPF/Low corner

Figure B.3. (Continued.)

134

Out1

1

Integrator

1s

1/tau2

-K-

In1

1

nonlin_switched_slowfast/Outer loop controller/BPF/High corner

Figure B.3. (Continued.)

Out1

1

Integrator

1s

1/tau1

-K-

In1

1

nonlin_switched_slowfast/Outer loop controller/LPF

Figure B.3. (Continued.)

135

ioff

1

filter coef

-K-

Integrator1

1s

iref

2

iL

1

nonlin_switched_slowfast/Outer loop controller/Native AVP

Figure B.3. (Continued.)

Vin

1

line step

Rsrc

-K-

Manual SwitchConstant

2

iin

1

nonlin_switched_slowfast/2 V source

Figure B.3. (Continued.)

136

q(t)_4

5

q(t)_3

4

q(t)_2

3

q(t)_1

2

Scope out

1

Terminator3

Terminator2

Terminator1

Terminator

Stabilizing Ramp4

Stabilizing Ramp2

Stabilizing Ramp1

Stabilizing Ramp

SR latch3

S

R

Q

Q'

SR latch2

S

R

Q

Q'

SR latch1

S

R

Q

Q'

SR latch

S

R

Q

Q'

Comparator3

+

-

Out

Comparator2

+

-

Out

Comparator1

+

-

Out

Comparator

+

-

Out

Clock 4

Clock 3

Clock 2

Clock 1

Iref/4

5

IL_4

4

IL_3

3

IL_2

2

IL_1

1

nonlin_switched_slowfast/dc pcm process

Figure B.3. (Continued.)

137

q(t)_2

3

q(t)_1

2

Scope out

1

Terminator1

Terminator

Stabilizing Ramp1

Stabilizing Ramp

SR latch1

S

R

Q

Q'

SR latch

S

R

Q

Q'

Comparator1

+

-

Out

Comparator

+

-

Out

Clock 2

Clock 1

Iref/2

3

IL_2

2

IL_1

1

nonlin_switched_slowfast/ac pcm process

Figure B.3. (Continued.)

138

iin

2

iL

1

iLstate

1s

Vd

Vd

Rs

Rs

Rl+Resr

-K-

Resr1

-K-

Rd

Rd

Logic Invert Data Type Conversion3

Convert

Data Type Conversion

Convert

1/L

1/L

vc

4

q(t)

3

iout

2

vin

1

nonlin_switched_slowfast/Dc phase 1

Note: Other phases follow this topology.

Figure B.3. (Continued.)

139

vc

2

vout

1

cap

1s

TransportDelay

Resr

-K-

1/C

-K-

i_c

1

nonlin_switched_slowfast/Bus Capacitor

Figure B.3. (Continued.)

B.3.2 Set-Up Code

% Parameters for the PCM batt-ucap converter, 10kHz, 1000uF output % capacitance % This tuning is stable for new controller % Plant parameters Lfast = 10e-9; Ldc = 500e-9; C = 670e-6; R = 0.08; Vin = 2; Vc = 0.8; Voc = 0.8; Rth = 0.8e-3; Resr = Rth; Rin_s = (1.75+2.4)*1e-3; Rin_f = (1+6.5)*1e-3; Rsw_s = 2.4e-3; Rsw_f = 6.5e-3; Rsrc = 5e-3; T_fast = 1/5e6; %fast switching period T_slow = 1/150000; %slow switching period Ma_r = 0.7; %relationship of Ma to off-time slope of inductor current Kdc = 1/Rth; Kp = 1/Rth; tau1 = 1/(2*pi*3000); tau2 = T_fast*0.1; %.001478; D_filter = 10;

140

navp_corner = 200; % simulation parameters Pload_step = 160; s_t = 1e-6; %rise time of step r_t = 0.2; %length of rise time of ramp %Calculated parameters % clear Vterm; % Vterm = fzero(@(Vterm) Vterm_fcn(Vterm,Vin,Voc,Rbatt,Kp,T,L,Ma_r),Voc); Vterm = Vc; D = Vterm/Vin; Dp = 1 - D; M2dc = Vterm/Ldc; %slope of rising inductor current; is equal to (Vin-Vswitch)/L in boost converter M1dc = (Vterm-Vin)/Ldc; %in lossless boost converter Madc = M2dc*Ma_r; M2fast = Vterm/Lfast; %slope of rising inductor current; is equal to (Vin-Vswitch)/L in boost converter M1fast = (Vterm-Vin)/Lfast; %in lossless boost converter Mafast = M2fast*Ma_r; % find initial states of slow inductors h0T = get_f0T_handle(Vc,Vin,1e6,Rin_s,Resr,Ldc,C,D,T_slow); x0 = fsolve(h0T,[-(Vin-Vc)*D*T_slow/(2*Ldc);Vc],optimset('TolFun',1e-10)); Ilmin1 = x0(1); Vcmax = Vc+(x0(2)-Vc)/4; if D < 0.25 h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); hT = get_fDT_T_handle(1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,D*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)],odeset('MaxStep',T_slow/100)); [t2,x2] = ode15i(hT,[D*T_slow,0.25*T_slow],[xDT(end,1);xDT(end,2)],... [-xDT(end,2)/Ldc;(xDT(end,1)-xDT(end,2))/(1e6*C)],... odeset('MaxStep',T_slow/100)); Ilmin2 = x2(end,1); Q2init = 0; else h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,0.25*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)],odeset('MaxStep',T_slow/100)); Ilmin2 = xDT(end,1); Q2init = 1; end if D < 0.5 h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); hT = get_fDT_T_handle(1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,D*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)],odeset('MaxStep',T_slow/100)); [t2,x2] = ode15i(hT,[D*T_slow,0.5*T_slow],[xDT(end,1);xDT(end,2)],... [-xDT(end,2)/Ldc;(xDT(end,1)-xDT(end,2))/(1e6*C)],... odeset('MaxStep',T_slow/100)); Ilmin3 = x2(end,1); Q3init = 0; else h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,0.5*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)],odeset('MaxStep',T_slow/100)); Ilmin3 = xDT(end,1); Q3init = 1; end if D < 0.75

141

h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); hT = get_fDT_T_handle(1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,D*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)],odeset('MaxStep',T_slow/100)); [t2,x2] = ode15i(hT,[D*T_slow,0.75*T_slow],[xDT(end,1);xDT(end,2)],... [-xDT(end,2)/Ldc;(xDT(end,1)-xDT(end,2))/(1e6*C)],... odeset('MaxStep',T_slow/100)); Ilmin4 = x2(end,1); Q4init = 0; else h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,0.75*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)],odeset('MaxStep',T_slow/100)); Ilmin4 = xDT(end,1); Q4init = 1; end % get initial state of slow iref integrator h0DT = get_f0DT_handle(Vin,1e6,Rin_s,Resr,Ldc,C); [~,xDT] = ode15i(h0DT,[0,D*T_slow],[Ilmin1;Vcmax],... [(Vin-x0(2))/Ldc;x0(1)/(1e6*C)]); Iref_init_dc = xDT(end,1)+Madc*D*T_slow; % find initial states of fast inductors clear h0T h0DT hT; h0T = get_f0T_handle(Vc,Vin,1e6,Rin_f,Resr,Lfast,C,D,T_fast); x0 = fsolve(h0T,[-(Vin-Vc)*D*T_fast/(2*Lfast);Vc],... optimset('TolFun',1e-10)); Ilmin5 = x0(1); % Vcmax = Vc+(x0(2)-Vc)/4; if D < 0.5 h0DT = get_f0DT_handle(Vin,1e6,Rin_f,Resr,Lfast,C); hT = get_fDT_T_handle(1e6,Rin_f,Resr,Lfast,C); [~,xDT] = ode15i(h0DT,[0,D*T_fast],[Ilmin5;Vcmax],... [(Vin-x0(2))/Lfast;x0(1)/(1e6*C)],odeset('MaxStep',T_fast/100)); [t2,x2] = ode15i(hT,[D*T_fast,0.5*T_fast],[xDT(end,1);xDT(end,2)],... [-xDT(end,2)/Lfast;(xDT(end,1)-xDT(end,2))/(1e6*C)],... odeset('MaxStep',T_fast/100)); Ilmin6 = x2(end,1); Q6init = 0; else h0DT = get_f0DT_handle(Vin,1e6,Rin_f,Resr,Lfast,C); [~,xDT] = ode15i(h0DT,[0,0.5*T_fast],[Ilmin5;Vcmax],... [(Vin-x0(2))/Lfast;x0(1)/(1e6*C)],odeset('MaxStep',T_fast/100)); Ilmin6 = xDT(end,1); Q6init = 1; end % get initial state of fast iref integrator h0DT = get_f0DT_handle(Vin,1e6,Rin_f,Resr,Lfast,C); [ttt,xDT] = ode15i(h0DT,[0,D*T_fast],[Ilmin5;Vcmax],... [(Vin-x0(2))/Lfast;x0(1)/(1e6*C)]); Iref_init = xDT(end,1)+Mafast*D*T_fast; % find needed C value to keep iref from exceeding il slew il_step = 120; Vin0 = Vin-il_step*Rsrc; NN = 2; %# of phases Cmin = il_step*Lfast*Kp/((0.4)*Vin0*NN^2)

142

Helper functions for fsolve and ode15i function h = get_f0DT_handle(Vin,R,Rin,Resr,L,C) h = @f0DT; function err = f0DT(t,x,xp) err = [0;0]; Vout = x(2) + xp(2)*C*Resr; err(1) = L*xp(1) - (Vin-Rin*x(1)-Vout); err(2) = C*xp(2) - (x(1)-Vout/R); end end

function h = get_fDT_T_handle(R,Rin,Resr,L,C) h = @fDT_T; function err = fDT_T(t,x,xp) err = [0;0]; Vout = x(2) + xp(2)*C*Resr; err(1) = L*xp(1) + (Rin*x(1)+Vout); err(2) = C*xp(2) - (x(1)-Vout/R); end end

function h = get_f0T_handle(Vc,Vin,R,Rin,Resr,L,C,D,T) h = @f0T; function err = f0T(x0) % integrates systems f0DT and FDT_T from time 0 to T % initialize vars and function handles err = [0;0]; hDT = get_f0DT_handle(Vin,R,Rin,Resr,L,C); hT = get_fDT_T_handle(R,Rin,Resr,L,C); [t,x] = ode15i(hDT,[0,D*T],x0,[(Vin-x0(2))/L;x0(1)/(R*C)],odeset('MaxStep',T/100)); [t2,x2] = ode15i(hT,[D*T,T],[x(end,1);x(end,2)],[-x(end,2)/L;(x(end,1)-x(end,2))/(R*C)],odeset('MaxStep',T/100)); % find area under Vc(t) t_shift = [0;t;t2(1:end-1)]; ddt = [t;t2]-t_shift; vc_area = [x(:,2)' x2(:,2)']*ddt; % These metrics are valid when the converter is sourcing no power. % Note that the square of a small number is even smaller - fsolve % tolerance needs to be very small for these equations to be % useful. err(1) = 2*(x0(1)+x(end,1)-Vc/R)^2 + (x0(1)-x2(end,1))^2; err(2) = 1000*(vc_area-Vc*T)^2 + (x0(2)-x2(end,2))^2; end end

143

APPENDIX C

SCHEMATICS FOR BIDIRECTIONAL PCM BOOST CONVERTER

This section lists the schematics for the scaled-down hardware. Figure C.1 is the

schematic for parts on the power converter board, and Figure C.2 is the schematic for a

second board with signal conditioning circuitry. In Figure C.1, parts with 9000-series

reference designators were added after the PCB was made, and pads do not exist for

them. The connection of these parts to the rest of the circuit is shown with thick wires.

144

Battery

-Ultra

capacitor

Inte

rface

PC

B50027

A02

UC

+

UC

-

Out +

Out -

(Vin

)

Pow

er

Convert

er

and C

onnections

Batt +

Batt -

Board

sta

ndoffs

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r 3

00

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ers

ion

, in

sta

ll 6

8u

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ap

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12

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chem

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for

pow

er c

onve

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PC

B.

145

Battery

-Ultra

capacitor

Inte

rface

PC

B50027

A02

Gate

Drive a

nd E

nable

Circuit

LE

D S

hin

es w

hen F

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ridge

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Con

tinu

ed.)

146

Battery

-Ultra

capacitor

Inte

rface

PC

B50027

A02

I_batt s

ignal to

AD

C

Gain

: 100 m

V/1

A

Range +

/- 1

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V_in

sig

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C

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= 1

/2

I_L s

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C

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: 100 m

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/- 1

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z

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z

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SA

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pots

to U

8 a

nd U

4,

connect as s

how

n

SA

I: Insta

ll 100k trim

pot to

U3,

connect w

iper

to p

in 7

of U

3

IBA

TT

_IN

V

Analo

g H

PF

of V

out

tau =

3.7

1

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12

34

56

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150

REFERENCES

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