Xilinx ISE 5.2i TutorialCSE 670 – Winter 2004

1. Double click the ISE ‘Project Navigator’ icon on the Desktop to start the Project Navigator, then maximize the window.

2. On the Project Navigator toolbar, click: File => New Project… .

3. In the New Project window, first click the browse button and browse for your directory.

Then select the following:Device Family: Spartan2 (or Spartan)Device: xc2s200Package: pc208 Speed Grade: -6Design Flow: XST VHDL

4. Finally, type Lab1s for Project Name and click OK. (Notice that Lab1s is also automatically added to the Project Location.)

Place the MUX2G.vhd file given on the class website in your C:\CSE378\<last name>\Lab1s directory. This tutorial will guide you through adding that source as an existing source file and creating the LAB1.vhd file given in the lecture as a new file.

5. Select Project => Add Source…

6. Select the file MUX2G.vhd from your original directory C:\CSE378\<your_name>\Lab1\src. Click Open.

7. Select VHDL Module for MUX2G.VHD. Click OK.

8. Now you have successfully added the MUX2G.vhd, an existing VHDL file, to your project. Next, we will create a new source file for LAB1.vhd. Select Project New Source.

9. In the window shown, type the name of the VHDL file that you wish to create. In this case it is Lab1. Select VHDL Module from the file type selection box and click Next.

10. This screen is used to declare the inputs and outputs for your entity. Type in the inputs and outputs as shown for the Lab1 entity and click Next. On the confirmation screen that appears next, click Finish.

11. Type in the component declaration for the MUX2G and the port map statements to connect the component to your LAB1 entity. Be sure to include the ldg <= ‘1’ to enable the prototype board when the design is downloaded for testing.

12. Be sure to comment the beginning of every file in your project with:

-- Name: Ima Student-- File: Filename.vhd-- Date: Month, Day, Year-- Description: Briefly describe the purpose of this file-- CSE 670

13. Now that the source files are created it is almost time to download the design to the board and verify that it works. First, we must simulate the design to make sure that it will function as expected. To simulate the design, we will use ALDEC’s Active-HDL Simulator. Click on the Active-HDL icon on your desktop or from the program menu located in the Start button.

14. From the Getting Started menu, select ‘Create a New Workspace’, then click OK.

15. Enter the Name of the project and the path where the simulation project will be stored. It is important to use the same path as you did in ISE, the synthesis tool. When you are finished, Click OK.

16. Now, select Add Existing Resource Files to add the VHDL files created in ISE to the simulation project in Active-HDL. Click Next.

17. Click on Add Files and select the directory that contains the VHDL files that you created in ISE. You may select multiple files by holding down CTRL while clicking the files to select them. When you are finished, click Add, then click Next.

18. Fill in the information as shown below. Note that if you are using a board with a SPARTAN 2, you must select SPARTAN 2 and if you are using a board with a SPARTAN 2E, then you must select SPARTAN 2E. Click Next.

19. Finally, enter the design name, in this case Lab1, and click Next, then Finish on the confirmation box that will appear.

Xilinx-3.3 Spartan II

20. If you click the ‘+’ sign next to Lab1, you will see your files. The green check mark signifies that the files have been compiled by the simulator and are correct. Click the New Waveform icon on the toolbar.

21. Click on the Structures tab then Click on Lab1 and drag it to the waveform window.

Click on lab1anddrag it to here.

22. Setup the stimulators for the input signals.

Right-click on SW and select Stimulators.

Select Value and type in 16#A5.Click Apply.

Click on BTN4.

Select Clock.

Click Apply.

23. Run the simulation

Set the simulation time to 300 ns.

Click Run For

24. If the output was not as expected, you may edit the VHDL files directly in Active-HDL by clicking on the Files tab, double-clicking on the file you wish to edit and making the changes. When you save the changes in Active-HDL, they will be reflected in ISE since the files that you are editing are the same files. If you edit files in the simulator, be sure to regenerate a new programming file in ISE for downloading if you already have generated one from the previous source file. Print out the waveform by selecting File -> Print from the menu bar.

25. Now that we have simulated the design and it will operate correctly, we are ready to synthesize the design. Switch back to ISE. Before we can generate a programming file, we must create a constraints file that will associate the inputs and outputs of our circuit with the correct pin numbers on the board. You will find the pin numbers on the class website. Make sure that you download the correct pin number document, depending on whether your board has a Xilinx Spartan 2 or 2E. Make sure that Lab1.vhd is selected in the Sources in Project window.

26. Select Project New Source from the menu bar. Select Implementation Constraints File from the source type selection box and type Lab1 in the File Name box. Click Next.

27. Associate the constraints file with the top-level of the design. In this case that is Lab1. Click Next, then Finish on the confirmation screen.

28. Double-click the new constraints file, Lab1.ucf, shown in the Source in Project window.

29. Click on the Ports tab and enter the correct pin assignments based on the pin assignments given in the document on the class website. Notice that in our lab, the peripheral board is connected to the C-Connector so be sure to use that column on the chart when selecting pins. Each pin must be preceded by a “p”, for example pin 150 would be p150. When you are finished, close the constraints editor and click ‘Yes’ to save changes.

30. Make sure that Lab1.vhd is selected. Right-click Generate Programming File and select Properties. Click on Startup options and set the Start-Up Clock to JTAG Clock. Click OK.

31. Double-click Generate Programming File.

32. Make sure the printer port from the computer is connected to the FPGA board and power is connected to the board. Click the + sign on Generate Programming File and double-click Configure Device (iMPACT).

33. Click Configure Device from the iMPACT start menu. Click Next.

34. Now select Boundary scan and click Next.

35. Finally, select Automatically connect to cable and click Finish.

36. Select the correct bit file, Lab1.bit to download to the chip from the dialog box. Click Open.

Note: You may receive a warning about the Jtag clock, don’t worry about it, click OK.

37. Right-click on the picture of the chip and select Program…, the design will download.

38. When the chip has been programmed, close iMPACT. If you leave it open and change your design and generate another programming file, you will get an error because it will attempt to open iMPACT again.

39. Remember to print out:

1. Your VHDL files2. Your simulation waveforms3. The Map Report as shown below

Shows how much of the chip you have used with your design