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© Copyright 2015 Xilinx, Inc. X ilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinxin the United States and other countries. All other trademarks are the property of their respective owners.

Xilinx's Low-End Portfolio adds a new perspective to systemcost analysis by offering many unique strategies for overallBOM cost reduction.

White Paper: Low-End Portfolio

WP460 (v1.0) March 31, 2015

Reducing System BOM Cost withXilinx's Low-End Portfolio

By: Cathal Murphy, Ehab Mohsen, and Srinivasa Kolluri

ABSTRACT

System designers face continuous pressure to reduce the total Bill of Materials(BOM) cost of the system. The system’s BOM is made up of several differentbut interdependent component costs, meaning a holistic approach is requiredto ensure that the lowest overall BOM cost is achieved.

While system BOM cost is a concern for nearly all FPGA-based systems, it istypically the high-volume applications that deal with exceptional costpressures. Industrial motor control, portable ultrasound, driver assistancesystems, and hand-held military radio are some examples where cost is asignificant factor.

With a balance of the right features and cost-effectiveness, Xilinx offers anextensive Low-End Portfolio of products that delivers the best value for abreadth of applications. The portfolio features the Spartan®-6 FPGA family,the Artix®-7 FPGA family, and the Zynq®-7000 All Programmable (AP) SoCfamily—each optimized for design requirements.

The diverse capabilities inherent in these product families can offer the systemdesigner numerous cost-reduction strategies, making them an ideal f it forcost-sensitive applications in the industrial, medical, automotive, consumer,

and communication infrastructure markets, among others.While total cost of ownership also involves other factors such as length ofdesign cycles, field upgradability, and development of derivative products, thiswhite paper focuses exclusively on the impact of device selection on systemBOM cost.

http://www.xilinx.com/


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WP460 (v1.0) March 31, 2015 www.xilinx.com 2

Reducing System BOM Cost with Xilinx's Low-End Portfolio

IntroductionThe FPGA is one of the highest-value components in an electronic system; therefore, once it hasbeen determined that specifications can be met, it is naturally the first place to look for reducingoverall system cost. While examining device cost is a worthy (and necessary) exercise in itself,analyzing device densities, speed grades, and packaging against the overall system requirements,

designers are best served with a holistic view, examining the impact that device features mighthave on the design of the whole system, and hence on their effect upon the overall BOM cost.

It starts with an understanding of major cost drivers within a typical system's BOM, which include

• Digital logic components (e.g., FPGAs, ASSPs)

• Processors (e.g., CPUs, MPUs, DSPs)

• Analog Mixed Signal (AMS) components (e.g., amplifiers, ADCs, DACs)

• Sensors (e.g., temperature, pressure, humidity)

• Power supplies and thermal management components

• Volatile and nonvolatile memory components

• Passive components (e.g., resistors, capacitors, inductors)

• Safety, security, and reliability components

• Protocol PHY components

Analysis must include the cost of the printed circuit board (PCB) cost itself, including PCB layers,mechanical components, and connectors.

Low-End Portfolio OverviewThe Xilinx® Low-End Portfolio, consisting of the Spartan-6, Artix-7, and Zynq-7000 device families,targets this cost-sensitive market. As shown in Figure 1, having these three product families withinthe Xilinx All Programmable Low-End Portfolio ensures that Xilinx can deliver optimized value to adiverse set of cost-sensitive end applications and markets over a broad range of densities.

Specifically, the Xilinx Spartan-6 FPGAs deliver I/O optimization; the Artix-7 FPGAs delivertransceiver optimization; and the Zynq-7000 All Programmable SoCs (Z-7010, Z-7015, and Z-7020)deliver system integration and optimization for SoC applications. The Xilinx Low-End PortfolioBackgrounder , available on the Xilinx website[Ref 1], provides an excellent overview of this newlyassembled portfolio of Xilinx product families.



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The Spartan-6 family is the industry's low-cost leader and an ideal f it for simple to moderatelycomplex bridging functions found in a range of applications; this includes such market segments asinfotainment and consumer/industrial automation. In addition to high I/O-to-logic-cell ratios andsmall form-factor package offerings, this device family offers best-in-class DSP and logic fabricperformance that meet the power requirements for many cost-sensitive systems.

For FPGA applications that demand more advanced functionality, however, the 28 nm-basedArtix-7 family offers exceptional performance per watt. The Artix-7 family leads the industry in

nearly every aspect of performance in a low-end device, including logic fabric performance,memory line rates, and signal processing bandwidth.

One of the greatest distinctions of the Artix-7 FPGA is its array of transceivers. With line ratesexceeding 6 Gb/s, the family offers the industry’s smallest and fastest transceiver-based devicesavailable in 10x 10 mm packaging, making it an ideal low-cost alternative for bandwidth-sensitiveapplications that might otherwise require more costly mid-range solutions.

For applications that require more than just bandwidth—e.g., intelligent processing and analyticsto provide the highest levels of system optimization—the Zynq-7000 family is an ideal solution. Ona single-chip platform, these devices bring together hardware, software, analog mixed signal, and

connectivity capabilities, both within the platform and outward to external devices. Fusing Artix-7FPGA fabric to a dual-core ARM® Cortex™-A9 processor, the low-end Zynq-7000 AP SoCs (Z-7010,Z-7015, and Z-7020) provide the highest level of system integration of the three families; this, inturn, has downstream effects, reducing system power and maximizing performance.

While designers must select a device family based on these characteristics, equally important is theimpact their device selection has on system BOM cost. In Xilinx's product def inition process, thecomplete system cost for a huge variety of applications was analyzed to ensure that the overallsystem BOM cost was specifically addressed across many different use cases. X ilinx’s focus is ondelivering the highest functionality at the right price point while reducing system cost from

X-RefTarget- Figure 1

Figure 1: Xilinx's Low-End Portfolio Value

Value

Broadest Cost Effective Low-End Portfolio

TransceiverOptimization

SoCOptimization

I/OOptimization

PowerEfficiency

PowerEfficiency

Performance

Performance

Integration

PowerEfficiency

Performance

WP460_01_033115



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multiple perspectives. See Figure 2.

Bill of Materials Cost Reduction StrategiesSeveral elements impact and contribute to overall BOM cost in a system—i.e., the costs of thecomponents and the board itself. Devices in the Xilinx Low-End Portfolio mitigate these costs by:

• Eliminating components through systems integration

• Reducing the cost of other components on the board through diverse functionality

•

Minimizing PCB development cost through best-in-class device packaging

Eliminating Components through System Integration

The advantage of a programmable device is not just customizable digital logic; it is, rather, thebroad array of functions—in some cases, non-digital—available in today's technology. A system'shigh-value digital components can comprise processors, DSPs, ASSPs, FPGAs, or a combination ofthese; its non-digital components can include ADCs, sensors, and PHY interfaces, among others.Devices from Xilinx's Low-End Portfolio can integrate much of this functionality on a single chip.

High-density system integration like this not only lowers BOM cost, but because this process

reduces board space and overall power consumption, it lowers the cost of the PCB itself, as well asthe system's power and thermal management solutions.


Figure 2: Low-End Portfolio by Logic Cell Density

System Integration and Optimization

Z-7010 Z-7015 Z-7020 Mid-Range

Transceiver Optimization

A35TA15T A50T

I/O Optimization

DENSITY: 20K 40K 60K 80K 100K +

LX16LX9

A75T A200TA100T

LX4 LX25 LX45 LX75 LX100 LX150 I n c r e a s i n g c a p a b i l i t i e s a n d p e r f o r m a

n c e

WP460_02_033115



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Processor Integration

Many applications require a processor to simplify the interaction of the system with a widernetwork, with a human-machine interface (HMI), or with an observation-and-maintenancesolution. In the past, systems needed to contain both an FPGA and a discrete processor to meetsuch requirements. However, Xilinx offers a range of processor-included solutions to meet a diverseset of application requirements. External processors are no longer needed.

MicroBlaze IP Core Processors

All devices in the Xilinx Low-End Portfolio have access to the FPGA-based MicroBlaze™ softprocessor IP cores:

• The MicroBlaze CPU is a 32-bit RISC Harvard architecture soft-processor core. A block diagramof this IP is shown in Figure 3. It contains over seventy user-configurable options, enablingimplementation of virtually any processor use case, from a very-small-footprint state machineor microcontroller to a high-performance, compute-intensive microprocessor-based systemrunning Linux. The IP can be configured to operate in either a three-stage pipeline mode (to

optimize for size), or in a f ive-stage pipeline mode (to optimize for speed)—thus deliveringfaster DMIPs performance than any other FPGA-based soft processing solution. For detailedinformation and links to documentation, visit the MicroBlaze processor page on the Xilinxwebsite.[Ref 2]


Figure 3: MicroBlaze Soft Processor IP Block Diagram

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Optional MicroBlaze Processor Feature

Instruction-sideBus Interface

Data-sideBus Interface



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The Zynq-7000 Family: Full-Featured FPGAs with On-Chip Dual-Core ARM Cortex Processors

The Zynq-7000 family offers even more in the way of processing options. Each Zynq-7000 AP SoCcontains a processor system, as shown in Figure 4. The processor system contains a 1 GHzdual-core hardened implementation of the ARM Cortex-A9 MP Core microprocessor with extensiveOS, middleware, and stack ecosystem availability.

This extensive array of processing options ensures that, in the vast majority of applications, no

additional processor is required in the system, resulting in a significant BOM cost reduction. Thisalso enables massive performance improvements due to the data transfer speeds that can beachieved between the on-chip processor and logic, as well as the hardware acceleration ofprocessing and analytics functions that can be performed in the programmable logic space.

Analog Mixed Signal

Because analog mixed signal components (e.g., analog-to-digital converters, amplifiers) continueto be major contributors to a system's BOM, the 28 nm-based Artix-7 and Zynq-7000 familiesprovide an integrated analog mixed signal block called the Xilinx Analog-to-Digital Converter(XADC),[Ref 3] containing:

• A dual 1 MSPS 12-bit analog-to-digital converter (ADC)

• Seventeen external voltage inputs

• On-chip temperature and supply sensors

• JTAG and zero-latency DRP interfaces

Not only can this block replace discrete ADC components—but when coupled with the signalprocessing resources of the FPGA or AP SoC, the XADC can simplify and reduce the costs of the


Figure 4: 1 GHz Dual-Core Hardened Implementation of the ARM Cortex-A9 MP Core Microprocessor

WP460_04_033115

Processing SystemStatic Memory ControllerQuad-SPI, NANO, NOR

AMBA ® Switches

AMBA ® Switches

ARM ® CoreSight™ Multi-core & Trace Debug

NEON™/ FPU Engine

Cortex™-A9 MPCore™

32/32 KB I/D Caches

512 KB L2 Cache

Timer Counters

General Interrupt Controller DMA Configuration

S_AXI_HP0

S_AXI_HP1

S_AXI_HP2

S_AXI_HP3

S_AXI_ACP

ProgrammableLogic:

System Gates,DSP, RAM

256 KB On-chip Memory

Snoop Control Unit (SCU)

Cortex™-A9 MPCore™

32/32 KB I/D Caches

NEON™/ FPU Engine

AMBA ® Switches2x SPI

2x SDIOwith DMA

2x USBwith DMA

2x GigEwith DMA

EMIO S_AXI_GP0/1 M_AXI_GP0/1XADC

Multi-standards I/Os (3.3V & High Speed 1.8V) Serial Transceivers

M u l t i - s t a n d a r d s I / O s ( 3 . 3

V & H i g h S p e e d 1 . 8

V )

PCIe

2x I2C

2x CAN

2x UART

GPIO I / O

M U X

Dynamic Memory ControllerDDR3, DDR2, LPDDR2



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entire AMS signal chain. For more information on this topic, see the Xilinx white paper Efficient

Implementation of Analog Signal Processing Functions in Xilinx All Programmable Devices .[Ref 4]

For applications like motion control, power conversion, and distributed control systems, the XADCcan be used to directly replace discrete ADCs and cost-reduce or eliminate other elements in themain control path. This results in a highly integrated, high-performance, yet low-cost solution,similar to the motor control example shown in Figure 5.

For applications that demand high reliability, security, or functional safety, the XADC providesenvironmental monitoring capabilities, such as junction temperature and on-chip supply sensing,eliminating the need for external monitor solutions, while at the same time meeting industrystandards such as IEC61508 and FIPS140-2.

PHY Integration

Given the growing array of interface standards and protocols, an external device (sometimes calleda PHY) might be required to physically translate the electrical signals to a form that can beinterfaced to an existing integrated circuit.

For a diverse number of protocols, Xilinx's Low-End Portfolio families offer interface support and IPto help remove the requirements for external components. For example, HDMI video IP (compliantup to HDMI 2.0) is available for all Artix-7 and Zynq-7000 devices. This IP removes the requirementand associated cost of an external HDMI transmitter/receiver and replaces it with resistors on thereceive side and simple drivers/level-shifters on the transmit side.

Other interfaces supported by the Low-End families include DisplayPort, XAUI, V-by-One, 3G-SDI,and JESD204B. For many of these protocols, multiple components are eliminated and overallsystem cost is reduced.


Figure 5: Integrated High-Performance Motor Control Solution

Zynq-7000 AP SoC

Network

Interface

GPIO

(PWM)

3-Phase

Inverter

PMSM

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la lb

Processor

ADC 1

ADC 2

VBUS

ControlAlgorithm

(DSP)

laV

BUS

lb

AMS



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Safety and Security Components

A growing number of applications are required to meet industry standards for security, functionalsafety, and reliability. As the world becomes more automated and interconnected, designers ofautomation equipment must ensure that their systems operate in a safe manner that cannot beinterfered with, either by accident or by intentional adversaries.

Achieving the appropriate functional safety, security, and reliability standards is not a trivial task,and it is ultimately one that significantly impacts the BOM of the overall system. The mostsignificant impact to BOM cost is the requirement for physical separation of certain functionalblocks, resulting in expensive multi-chip solutions. For functional safety and high reliability,physical separation is required both for redundancy and for separation of safe and “not safe”functions. For security, physical separation is required to ensure separation of encrypted andunencrypted data.

Xilinx offers a unique Isolation Design Flow (IDF) tool (available for all Low-End Portfolio families)that can be used to guarantee physical separation of functions within a single device. Thissubstantially reduces the number of components required on the board. The BOM cost savings

made possible by IDF is illustrated by the single-chip solution for a software-defined radioapplication shown in Figure 6. IDF is one of the key enablers of this design model because it allowsencrypted and non-encrypted functions to share the same device.

This tool has been approved for use by the National Security Agency of the United States in Type 1Cryptographic Systems. (For detailed information, see the Xilinx press release announcing thisapproval.)[Ref 5] IDF is also certified by TÜD SÜD as a “Software Tool for Safety RelatedDevelopment” for ISO26262 and IEC61508, up to ASLID and SIL3 respectively. Additional details onIDF can be found in the Xilinx white paper The Xilinx Isolation Design Flow for Fault-Tolerant

Systems[Ref 6] and in the Xilinx application note Developing Secure and Reliable Single FPGA

Designs with Xilinx 7 Series FPGAs or Zynq-7000 AP SoCs Using the Isolation Design Flow .[Ref 7]



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Reducing Component Cost

Many components on the board make up the infrastructure that ensures the core system elementscan perform to specification. Examples of these include components related to power delivery,

thermal management, and both volatile and nonvolatile memory. The cost of these functions isoften overlooked, resulting in higher BOM cost—and in lower system performance. However,careful FPGA or SoC selection can simplify these infrastructure requirements and provide the mostcost-effective solutions.

Power and Thermal Management Components

Every device has unique power requirements (i.e., voltage levels, load currents, and number ofrails), typically requiring a DC/DC conversion solution optimized for the device. The cost of such apower supply solution varies widely depending on a number of factors. The two main cost driversthat the integrated circuit device manufactures can influence are:

• The number of unique power rails required by the device

• The amount of current flowing through (or power being consumed by) each rail

The effect that these factors have on power supply solution costs is shown in Figure 7.


Figure 6: System Integration for Software-Defined Radio

WP460_06_033115

Digital RFAnalogFront End

Processor

Receiver

Modem

Cryptographic Subsystem

Transmitter

Key Management:SHA-2, HMAC, TRNG

Crypto Engine 1, AES

Supports DataSeparation and Isolation

Single ChipCrypto Enabled

Crypto Engine 2, AES

DataFramer

PL PS

Zynq-7000 AP SOC



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Another key driver of power supply solution cost are the actual manufacturer/vendor and devicechosen. Their cost, efficiency, and PCB area requirements vary widely, so consideration needs to begiven to f inding the optimum solution for each system requirement.

Furthermore, the power dissipation of the system and the eff iciency of the power conversionsystem directly impact thermal management requirements, which (depending on power dissipationneeds) can range from nothing at all to an actively cooled system comprising large, expensive heatsinks and fans. In many instances (e.g., industrial motor control), expensive thermal managementsolutions are not an option for reasons of cost and reliability. Therefore, if a design cannot achievecertain power targets, it cannot proceed.

Number of Unique Power Rails

Integrated circuits typically require a number of unique power rails (e.g., 1V, 1.8V). Each of theserails requires a unique DC/DC converter. In some instances, different integrated circuits have thesame requirements; therefore, the DC/DC converters can be shared between components. In thecase of a programmable device, primary voltage requirements include those shown in Table 1.


Figure 7: DC/DC Converter Cost

Table 1: Power Rail Requirements for a Typical Programmable Device

VoltageSupply

Purpose

VCCINT Core logic (e.g., CLBs, DSP blocks)

VCCBRAM Block RAMs (normally shared with VCCINT)

VCCAUX Auxiliary logic (e.g., clock managers, configuration pins)

VCCO I/O banks

MGTAVCC Transceivers (analog)

MGTAVTT Transceiver termination circuits (analog)

VCCINTPS For processor subsystem (AP SoCs)

0

0.5

1

1.5

2

2.5

3

3.5

4

0 1 2 3 4 5 6 7

N o r m a l i z e d A v e r a g e C o s t

Max Current (A)

Cost per Rail

Cost per Ampere

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As illustrated in Figure 7, pricing of DC/DC converters has a f ixed element, meaning that everyunique rail in the system adds cost. Therefore, reducing the number of DC/DC converters on theboard always has a reduction impact on the overall BOM cost. This is especially true when thecurrent consumption of that rail is less than 2A, as the cost per rail dominates.

To help reduce the number of unique rails in the system, Xilinx minimizes the number of differentrails required to power its devices. Where this is not possible, Xilinx uses rail voltages that are most

likely to be already available in the system; alternatively, it tries to ensure that current requirementsare low enough so that, in many instances, inexpensive linear regulators can be used.

This strategy was implemented in the Spartan-6 FPGA, whose power supply requirements areshown in Figure 8.

• For designers not using transceivers, only two rails are required, 1.1V and 2.5V:

o In many instances, 2.5V is already being used in the system for other components;therefore, it can be shared.

o In many other instances, the current requirement is so low that a low-cost linear regulator

can be used to provide 2.5V power to the Spartan-6 device.• If transceivers are to be used:

o One additional 1.2V regulator is required. Given the tight ripple requirements on MGAV CC

and MGAV TT , it is not recommended to share it with other components.

In the case of Artix-7 and Zynq-7000 devices—even for the lowest-power -1LI speed grade—theVCCINT and VCCBRAM voltages can be tied together and their voltage taken down to 0.95V. Thiseliminates the need for a unique voltage rail for VCCBRAM.


Figure 8: Spartan-6 FPGA Power Supply Requirements

WP460_09_110514

VCC

LXT Only

*Spartan-6 LX/LXT FPGAs assume VCCO = 2.5V or 3.3Vfor minimum supply count

Voltage Regulator(VCCINT) (1.2V or 1V*)

Voltage Regulator(V

CCAUX) (2.5V)

Voltage Regulator(V

CCO) (2 5V)

Voltage Regulator(AVCC

and AVTT

(1.2V)

ReferenceVoltage (VREF)

D

1

2

3

VCCAUX D

VCCO D

AVCC A

AVTT

VREFA

Spartan-6 FPGA Power Supply Connections

VCCINT



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Low Power Dissipation

Power is increasingly becoming a key differentiator for the small-form-factor, high-performancespace that requires tight thermal and power budgets. Through the combination of innovativeproduct architectures and by leveraging the best foundry processes in the industry (such as theTSMC 28 nm High Performance Low Power (HPL) process), Xilinx is able to deliver highperformance with up to a 30% power savings, versus the nearest competitor, for all 7 series devices.

Refer to the Xilinx white paper Lowering Power at 28 nm with Xilinx 7 Series FPGAs.[Ref 8]

Architectural innovations include:

• Transceivers to granularly balance power and performance trade-offs

• Multi-mode I/O control to dynamically disable input and output buffers as needed duringmemory interface write, read, and idle states

• Intelligent clock gating of unused components

• Power binning and voltage scaling of screened parts for lower operating voltage

These power-saving features are shown in Figure 9.

While voltage scaling and the low-power device options are available for all 7 series FPGAs (Artix-7,Kintex®-7, and Virtex®-7), as well as for Zynq-7000 AP SoCs, low-end devices in particular offerextensive voltage scaling options that reduce overall power by an additional 30% while retainingneeded performance (see Figure 10 and Table 2).

This is made possible by the headroom (i.e., flexibility permitting performance and powertrade-offs) gained with the 28 HPL process. While normal operating voltage is 1.0V, low-enddevices can offer a 0.95V option for -1 industrial speed grade (-1LI ) devices while retainingidentical performance.


Figure 9: Xilinx Power Reduction at 28 nm v. Previous Generation



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Given the dependency on DC/DC converter pricing for the amount of current being consumed byeach power rail (see Figure 7), the substantial power savings offered by Xilinx devices reducespower supply cost.

In addition, the cost of the passive components (inductors, capacitors, etc.) required by the DC/DCconverter vary greatly with their size, which in turn often tracks closely with the amount of currentthe device must be capable of handling. For example, using a power supply calculator [Ref 9]

provided by one major vendor, the total cost of a 1.0V rail decreases 33% by reducing its maximumcurrent rating from 3A to 2A. (In this example, the large cost differential is driven mainly by the costof the inductor.)


Figure 10: Total Power Reduction with Voltage Scaling for Low-End Industrial-Grade Devices

Table 2: Additional ~20-30% Total Power Reduction with Voltage Scaling (-1LI)

VCCINT(1) Static Power Savings Dynamic Power Savings

-1I, -2I 1.0V 0% 0%

Artix-7 -1LI 0.95V 50% 10%

Zynq-7000Low-End -1LI

0.95V 50% 10%

1.0V(2) 45% 0%

Notes:

1. For Zynq-7000 devices, voltage change is limited to programmable logic.

2. At 1.0V, one voltage rail can be used for both FPGA logic and processor sub-system.



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Optimum Power Supply Solutions

The cost effectiveness of power supply solutions varies widely depending on the vendor and thespecific device chosen. Xilinx partners with leading power supply vendors in the industry to meetdiverse requirements at the most attractive price, with the smallest board area, and at maximalefficiency. In addition, given their broad view of complete system power requirements for variousapplications, power control vendors are in a unique position to be able to offer the best solutions

The diverse range of use cases makes it difficult to create a one-size-fits-all solution. However, anumber of highly integrated solutions offer compelling value for a vast array of end use cases. TheAnalog Devices ADP5050/1/2/3 and the Texas Instruments TPS65261/2 are two such system powercontrol devices that provide outstanding flexibility and performance while requiring minimal boardspace.

The Avnet Artix-7 50T FPGA Evaluation Kit (AES-A7EV-7A50T-G) uses one of these parts, the AnalogDevices ADP5052; given a 5V input, this one device provides a complete power solution for theentire board. For more information on this evaluation kit, visit the Xilinx website.[Ref 10]

Solutions like these offer excellent value, as they provide a large number of rails that, in manyinstances, can provide a complete power supply solution for the entire system, not merely for theprogrammable device itself. In addition, they require only a small amount of board space and areroutable on two layers.

Configuration Memories

Programmable devices typically require storage for device configuration while processors requirestorage for their program instructions. This means system designers must factor in componentssuch as conf iguration memory.

While some currently available programmable solutions have integrated nonvolatile memory

(NVM) within the device, they are typically designed on older processing technologies. Therefore,they often cannot deliver the signal processing capabilities, high clock speeds, and gigabittransceiver rates required by many of today's equipment manufacturers. In addition, storagerequirements for many applications (e.g., protocol stacks) often exceed the capacity of theseintegrated NVMs.

Other programmable solutions support only their own conf iguration device, forcing systemdesigners to use their own, often very expensive, configuration solution.

Xilinx's Low-End Portfolio supports the most popular open-market flash interfaces, ensuring that alow-cost, commonly used configuration device can be chosen. Also supported are many options

for remote configuration via an external processor, making use of a centrally located NVM that isshared across the complete system. For more details on this type of application, see the Xilinxapplication note Using a Microprocessor to Configure 7 Series FPGAs via Slave Serial or Slave

SelectMAP Mode.[Ref 11]

Table 3 gives a brief overview of flash implementation approaches.



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Volatile Memory

Xilinx's low-end products contain a significant amount of integrated dynamic storage in the formof block RAM, distributed memory, processor caches, and on-chip memory (OCM). In many cases,the memory available within the device, either directly or via innovative methods,[Ref 12] is

sufficient for many applications, therefore eliminating the need for off-chip dynamic memorydevices like SDRAM.

However, a number of applications require additional external memory (e.g., frame buffering invideo processing applications). System designers must factor in the cost of these externalmemories for the entire product life cycle. Xilinx supports SDRAM DDR3 across its completeLow-End Portfolio, including the Spartan-6 family. DDR3 is currently the lowest cost per Mb/soption, and is likely to continue to be for the foreseeable future.[Ref 13]

Ensuring the Smallest, Lowest-Cost Programmable Device

High Utilization

One of the primary criteria when selecting a programmable solution is device density. Designersnaturally want the smallest, lowest-cost device possible for their applications. Historically, thechallenge with programmable solutions is maximizing utilization of logic resources for any givendesign without sacrificing performance. By nature of traditional architectures and implementationtools, imperfect design packing is inevitable, leading to significantly less than 100% utilization andpotential performance degradation.

With the 28 nm families, Xilinx leveraged its next-generation design environment, the Vivado®Design Suite, to ensure maximum device utilization and performance from its silicon architecture.

With the tool's hierarchical implementation and analytical engine, Xilinx low-end 28 nm devicescan deliver the following advantages over the competition:

• A full speed grade of performance improvement

• 20% better device utilization

Table 3: External Flash Support

ConfigurationMode

ConfigurationDevice

Relative CostEffectiveness

Slave Serial Microprocessor Most Cost-Effective

Master SPI SPI Flash(1)

Master BPI BPI Flash

Master Serial Xilinx PROM

Slave SelectMAP,Slave Parallel

Microprocessor Least Cost-Effective

Notes:

1. Competitive advantage over leading FPGA vendors



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The Vivado Design Suite realizes the potential of a device's programmable logic fabric anddedicated on-chip functional blocks through architecture and software integration to yieldmaximally efficient results. The speed grade and utilization improvements directly impact the costof the device because small, lower-speed-grade devices can be used to perform the same task.

Partial Reconfiguration

Xilinx partial reconfiguration extends the inherent flexibility of the FPGA by allowing specif icregions of the FPGA to be reprogrammed with new functionality while applications continue to runin the remainder of the device. In many designs, there can be a number of mutually exclusivefunctions. Partial reconfiguration can be used to configure the FPGA with only the functions thatare required at that particular instance in time. An example of this is illustrated in the Xilinxapplication note Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable

SoC Devices.[Ref 14]

Partial reconfiguration offers very unique benefits from a BOM cost perspective because it has thepotential to substantially reduce the device density requirement and power consumption of thedesign.

Reducing Printed Circuit Board (PCB) Costs

In the absence of adequate care, attention, and planning, the cost of the PCB can become a verysignificant part of the overall system cost. The key drivers for PCB cost are the number of layersrequired, the size of the board, and the need for cutting-edge PCB technology like laser vias andfine trace widths.[Ref 15]

Reducing PCB Layers with Innovative Packaging Solutions

Innovative packaging in Xilinx's Low-End Portfolio products ensures that the lowest-cost PCBsolution can be found. An excellent example of this is the Artix-7 FPGA CPG236 package. Thepackage itself is a 10x 10 mm, 0.5 mm pitch BGA, with more than 100 usable I/Os. In general,routing to a 10x 10 mm, 0.5 mm pitch BGA requires many PCB layers and the use of fine-geometrydesign rules. However, the innovative ball-grid pattern allows all of the balls to be routed on onlytwo layers using standard spacing and via sizes.

Board Area Reduction via System Integration

PCB costs are also substantially reduced by system integration, choice of an optimum power supplyand distribution method, component size, and so forth—because they all affect the size of the PCB

as well as the level of interconnect required. This can directly affect the number of PCB layersrequired, which in itself a huge cost factor.

BOM Cost Savings in End Applications

To further illustrate the BOM cost savings possible in end applications with Xilinx's low-endproduct family, a number of typical application examples have been analyzed from a BOM costperspective relative to competitive products.



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Sensor Interface with Artix-7 Devices

A range of end markets, e.g., industrial process control and in-service monitoring systems in largemechanical equipment, use FPGAs such as the Artix-7 XC7A35T device to aggregate and processsensor data and transmit critical information to a central host. The type of sensors used can varywidely depending on the application, but can include temperature, pressure, strain, position, andvibration sensors.

The block diagram shown in Figure 11 represents a typical circuit architecture and BOM for asensor interface board using a a non-Xilinx FPGA.

In contrast, the block diagram in Figure 12 illustrates the Xilinx Artix-7 solution, using an Artix-7XC7A15T FPGA.

Figure 13 illustrates that the X ilinx Artix-7 FPGA solution provides a BOM cost saving of up to 30%,relative to the most comparable competitive FPGA. These savings are realized by leveraging theArtix-7 FPGA’s lower-power, two-layer PCB routing that is made possible by its 10x10mm BGAconnection technology. Additionally, the Artix-7 device works with inexpensive off-the-shelfconfiguration devices, and features a fully integrated, on-chip X ilinx analog-to-digital converter(XADC).


Figure 11: Sensor Interface (Competing FPGA)


Figure 12: Sensor Interface (Artix-7 XC7A35T)

Competing FPGA Vendor

ADCMUX to host

Receiver

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Machine Vision with Spartan-6 Devices

Machine vision cameras are another common application niche for low-end FPGAs. Devices, suchas the Spartan-6 XC6LX45 FPGA, interface with an image sensor, perform complex image signalprocessing, implement custom IP, and transmit the recovered data to a central controller by way ofvarious communications protocols. A typical block diagram using a Spartan-6 FPGA is shown inFigure 14.

Some competitors’ FPGAs, especially those manufactured using larger process geometries likeembedded 55 nm, simply cannot perform the necessary digital signal processing required by thisapplication. When this is the case, the only option is to use an external DSP or ASSP (as shown inFigure 15) to perform the intensive image signal processing—or, use a more powerful FPGA, likethe Spartan-6 device.


Figure 13: Sensor Interface BOM Cost Savings


Figure 14: Machine Vision with Spartan-6 FPGA

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As can be seen from Figure 16, highly significant BOM cost savings (up to 34%) can be realized bychoosing the higher-performance Spartan-6 device, when compared to low-performancealternatives that require additional ASSP/DSP functionality to perform the complex imageprocessing required of this application.

Industrial Ethernet for Motor Control Using a Spartan-6 FPGA

FPGAs are widely used to realize industrial Ethernet interfaces for motors and similar equipment. A

block diagram for a typical Ethernet-based motor control application is illustrated in Figure 17.


Figure 15: Machine Vision Using a Low-Performance FPGA and ASSP


Figure 16: Machine Vision BOM Cost Comparison

Another FPGA

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An alternate approach to an industrial motor controller implementation is to use an industrial

Ethernet ASIC and MCU, as shown in Figure 18. However, as shown in Figure 19, the X ilinx solution,which uses a Spartan-6 FPGA, offers a substantial BOM cost saving of up to 27% over competitivenon-FPGA design models.


Figure 17: Spartan-6 FPGA Ethernet Industrial Motor Control Solution


Figure 18: Typical Non-FPGA ASIC/MCU Solution for Ethernet-Based Motor Control

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Motor

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Integrated Programmable Logic Controller (PLC) Using Zynq-7000 Z-7010 SoC

A very common application for the Xilinx Zynq-7000 Z-7010 AP SoC is for a PLC, e.g., in amotion-control system. A typical block diagram is shown in Figure 20.

Figure 21 shows that Xilinx is able to realize up to 23% BOM cost saving relative to its nearestcompetition for this PLC application. This saving is realized by leveraging the Zynq-7000 AP SoC’slarger OCM capacity, as well as its XADC and PCB area savings.


Figure 19: BOM Cost Savings, ASIC/MCU Solution vs. Xilinx Spartan-6 FPGA


Figure 20: Block Diagram of Motor Drive Using Zynq-7000 Z-7010 SoC

WP460_19_033115

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ConclusionWhen opting for a high-value component like an FPGA or AP SoC, designers must look beyondcomponent unit cost to instead consider its overall impact on total BOM cost.

Xilinx's Low-End Portfolio solutions can impact cost savings across major system design categories,including processor elements, power supplies, analog mixed signal components, safety andsecurity components, memories, and PCB boards, among others. Enabled by three diverse families,the Xilinx Low-End Portfolio adds a new perspective to system cost analysis and offers uniquesolutions to overall system cost reduction.

For additional details on the Xilinx All Programmable Low-End Portfolio, visit the Xilinxwebsite.[Ref 16]


Figure 21: Motor Drive BOM Cost Savings: Competitive SoC vs. Xilinx Zynq-7000 Z-7010 AP SoC

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References1. Xilinx Backgrounder, Low-End Portfolio

2. Xil inx website, MicroBlaze Soft Processor Core

3. Xil inx website, Analog Mixed Signal

4. Xilinx white paper WP442, Efficient Implementation of Analog Signal Processing Functions in Xil inx All Programmable Devices.

5. Xilinx press release, August 31, 2011: NSA Approved Defense-Grade Spartan-6Q FPGA inProduction for Highest Level Cryptographic Capabilities Strengthens Xilinx Secure Leadership

6. Xilinx white paper WP412, The Xilinx Isolation Design Flow for Fault-Tolerant Systems.

7. Xilinx application note XAPP1086, Developing Secure and Reliable Single FPGA Designs with Xil inx 7 Series FPGAs or Zynq-7000 AP SoCs Using the Isolation Design Flow.

8. Xilinx white paper WP389, Lowering Power at 28 nm with Xilinx 7 Series FPGAs.

9. Texas Instruments website, WEBENCH Power Designer:www.ti.com/lsds/ti/analog/webench/power.page

10. Xilinx website, Artix-7 50T FPGA Evaluation Kit11. Xilinx application note XAPP583, Using a Microprocessor to Configure 7 Series FPGAs via Slave

Serial or Slave SelectMAP Mode.

12. Xilinx Tech Tip, Zynq-7000 AP SoC Boot—Booting and Running W ithout External Memory.

13. EETimes, “DDR4 Ramps Up, Enterprise First” Hilson, G., 9/9/2014:www.eetimes.com/document.asp?doc_id=1323826

14. Xilinx application note XAPP1159, Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices .

15. Staci Corporation white paper, Printed Circuit Board Cost Drivers:www.stacicorp.com/white_papers/PCB-Cost-Drivers-White-Paper.pdf

16. Xilinx website, All Programmable Low-End Portfolio


http://www.xilinx.com/publications/prod_mktg/low-end-backgrounder.pdf

http://www.xilinx.com/tools/microblaze.htm

http://www.xilinx.com/products/technology/analog-mixed-signal.html

http://www.xilinx.com/support/documentation/white_papers/wp442-analog-sig-proc.pdf

http://press.xilinx.com/2011-08-31-NSA-Approved-Defense-Grade-Spartan-6Q-FPGA-in-Production-for-Highest-Level-Cryptographic-Capabilities-Strengthens-Xilinx-Secure-Leadership/

http://www.xilinx.com/support/documentation/white_papers/wp412_IDF_for_Fault_Tolerant_Sys.pdf

http://www.xilinx.com/support/documentation/application_notes/xapp1086-secure-single-fpga-using-7s-idf.pdf

http://www.xilinx.com/support/documentation/white_papers/wp389_Lowering_Power_at_28nm.pdf

http://www.ti.com/lsds/ti/analog/webench/power.page


http://www.xilinx.com/products/boards-and-kits/AES-A7EV-7A50T-G.htm

http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

http://www.eetimes.com/document.asp?doc_id=1323826




http://www.xilinx.com/support/documentation/application_notes/xapp1159-partial-reconfig-hw-accelerator-zynq-7000.pdf

http://www.stacicorp.com/white_papers/PCB-Cost-Drivers-White-Paper.pdf




http://www.xilinx.com/products/silicon-devices/low-end-portfolio.html


http://www.xilinx.com/products/silicon-devices/low-end-portfolio.html


http://www.xilinx.com/support/documentation/application_notes/xapp1159-partial-reconfig-hw-accelerator-zynq-7000.pdf


http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf

http://www.xilinx.com/products/boards-and-kits/AES-A7EV-7A50T-G.htm


http://www.xilinx.com/support/documentation/white_papers/wp389_Lowering_Power_at_28nm.pdf

http://www.xilinx.com/support/documentation/application_notes/xapp1086-secure-single-fpga-using-7s-idf.pdf

http://www.xilinx.com/support/documentation/white_papers/wp412_IDF_for_Fault_Tolerant_Sys.pdf

http://press.xilinx.com/2011-08-31-NSA-Approved-Defense-Grade-Spartan-6Q-FPGA-in-Production-for-Highest-Level-Cryptographic-Capabilities-Strengthens-Xilinx-Secure-Leadership/

http://www.xilinx.com/support/documentation/white_papers/wp442-analog-sig-proc.pdf

http://www.xilinx.com/products/technology/analog-mixed-signal.html

http://www.xilinx.com/tools/microblaze.htm

http://www.xilinx.com/publications/prod_mktg/low-end-backgrounder.pdf

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Revision HistoryThe following table shows the revision history for this document:

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Automotive Applications DisclaimerXILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRINGFAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF AVEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFT WARE INTHE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR(III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OFANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

Date Version Description of Revisions

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