welcome to ee 130/230a integrated circuit devices
DESCRIPTION
Welcome to EE 130/230A Integrated Circuit Devices. Instructors: Prof. Tsu-Jae King Liu ([email protected]) TA: Peng Zheng ([email protected]) Web page: http://www-inst.eecs.berkeley.edu/~ee130/ bSpace: EE 130/230A Fall 2013 - PowerPoint PPT PresentationTRANSCRIPT
Welcome to EE 130/230AIntegrated Circuit Devices
Instructors: Prof. Tsu-Jae King Liu ([email protected])TA: Peng Zheng ([email protected])
Web page: http://www-inst.eecs.berkeley.edu/~ee130/bSpace: EE 130/230A Fall 2013Piazza: https://piazza.com/berkeley/fall2013/ee130230a/home
Objectives: •Fundamental understanding of the working principles of semiconductor devices used in modern ICs. •An ability to design a transistor to meet performance requirements within realistic constraints.
Schedule• Lectures (241 Cory): TuTh 2-3:30 PM • Discussion Section (beginning Tuesday 9/3):
– Section 101 (247 Cory): Mo 10-11 AM– Section 102 (247 Cory): We 12-1 PM
• Office Hours:– Prof. Liu (225 Cory): Mo 4-5 PM– Peng Zheng (288 Cory): Tu 9-10 AM
and We 4-5 PM
EE130/230A Fall 2013 Course Overview, Slide 2
Relation to Other Courses• Prerequisite:
– EECS40: Basic properties of semiconductors; basic understanding of transistor
operation – Familiarity with the Bohr atomic model
• Relation to other courses: – EE230A is prerequisite for EE230B (Solid State Devices)– EE130 is also helpful (but not required) for IC analysis
and design courses such as EE140 and EE141, as well as for the microfabrication technology course EE143
Course Overview, Slide 3EE130/230A Fall 2013
Reading Material• Textbook:
Semiconductor Device Fundamentals by R. F. Pierret(Addison Wesley, 1996)
• Reference:– Modern Semiconductor Devices for Integrated
Circuits by C. Hu (Prentice Hall, 2009)
Course Overview, Slide 4EE130/230A Fall 2013
Grading– Homework (posted online)
• due Th (beginning of class) • late homeworks not accepted!
– Design project• assigned by 11/7, due by 12/12• You may work in pairs
– 6 Quizzes •25 minutes each• closed book (notes allowed)• no make-up quizzes
– Final exam• Tu 12/17 8AM to 11AM• closed book (7 pages of notes allowed)
10%
20%
30%
40%
Letter grades will be assigned based approximately on the following scale:
A+: 98-100A: 89-98A-: 87-89B+: 85-87B: 76-85B-: 74-76C+: 72-74C: 63-72C-: 61-63D: 50-61F: <50
Course Overview, Slide 5EE130/230A Fall 2013
Miscellany• Special accommodations:
– Students may request accommodation of religious creed, disabilities, and other special circumstances. Please meet with Prof. Liu to discuss your request, in advance.
• Academic (dis)honesty– Departmental policy will be strictly followed– Collaboration is encouraged
• Classroom etiquette:– Arrive in class on time! – Bring your own copy of the lecture notes.– Turn off cell phones, etc.– Avoid distracting conversations
Course Overview, Slide 6EE130/230A Fall 2013
The Integrated Circuit (IC)• An IC consists of interconnected electronic components
in a single piece (“chip”) of semiconductor material.
The first planar IC(actual size: 0.06 in. diameter)
• In 1959, Robert Noyce (Fairchild Semiconductor) demonstrated an IC made in silicon using SiO2 as the insulator and Al for the metallic interconnects.
• In 1958, Jack S. Kilby (Texas Instruments) showed that it was possible to fabricate a simple IC in germanium.
Course Overview, Slide 7EE130/230A Fall 2013
300mm Si wafer
From a Few, to Billions of Components• By connecting a large number of components, each performing simple
operations, an IC that performs complex tasks can be built. • The degree of integration has increased at an exponential pace over
the past ~40 years.Moore’s Law: The # of devices on a chip doubles every ~2 yrs,
for the same chip price.Intel Ivy Bridge Processor1.4B transistors, 160 mm2
Course Overview, Slide 8EE130/230A Fall 2013
Impact of Moore’s Law#
DEV
ICES
(MM
)
YEAR
Market Growth
Investment
Transistor Scaling
Higher Performance,Lower Cost
CMOS generation: 1 um • • 180 nm • • 22 nm
http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf
Course Overview, Slide 9EE130/230A Fall 2013
The Nanometer Size Scale
Carbon nanotube
MOSFET
1 micrometer (1 m) = 10-4 cm; 1 nanometer (nm) = 10-7 cm
Course Overview, Slide 10EE130/230A Fall 2013
Course Overview
1. Semiconductor Fundamentals – 3 weeks
2. Metal-Semiconductor Contacts – 1 week
3. P-N Junction Diode – 3 weeks
4. MOS Capacitor – 2 weeks
5. MOSFET – 2 weeks
6. Modern CMOS Technology – 1 week
7. Bipolar Junction Transistor – 2 weeks
Metal-Oxide-Semiconductor (MOS)Field-Effect Transistor (FET)
Course Overview, Slide 11EE130/230A Fall 2013