Weekly Group Meetingon 18-06-2008

Project: Software Defined Radio Development using Network-On-Chip based Rapid Prototyping Platform

By

Assad Saleem

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Agenda

• Kernel Design Methodology

• NoC @ KTH

• REXAPP architecture and Kernels

• NOC design methodology

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Kernel Design Methodology

• Kernel Identification

• Kernel Definition (Kernel inputs and outputs, operation/s on inputs)

• Kernel Design (Kernel Hardware Architecture)

• Kernel Implementation

• Kernel Verification

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Kernel Identification

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Kernels for TDM (GSM) Tx/Rx baseband Processing

• Modulation• Burst forming &

Multiplexing• Encryption• Bit interleaving• Channel Coding• Speech Coding

• Demodulation• De-multiplexing

• Decryption• Bit De-interleaving• Channel Decoding• Speech Decoding

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Kernels for CDMA Tx/Rx baseband Processing

• Multiplexer• Mapper

• Block interleaver• Viterbi Encoder

• Correlator• De-multiplexer• Symbol Extraction,

Demapping• De-interleaver• Viterbi Decoder• CRC Detector

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Kernels for OFDMA Tx/Rx baseband Processing

• Append Cyclic Prefix• IFFT• Sub-channelization &

Pilot Insertion

• Symbol Mapping• Interleaving• FEC Coding• Randomization

• Remove Cyclic Prefix• FFT• De-subchannelization

& Pilot Extraction• Channel Estimation,

Equalization and CFO Correction

• Symbol De-mapping• De-interleaving• FEC Coding• De-randomization

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Common Kernels

• Multiplexer• Symbol Mapping• Interleaver

• De-multiplexer• Symbol De-mapping• De-interleaver

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NoC @ KTH

• Project and objectives– Network On Chip Architectures: NOCARC project is a three-

year research effort of 11 person between VTT Electronics, Oulu and Royal Institute of Technology, Stockholm. The project has been funded also by TEKES, VINNOVA, Nokia and Ericsson [1].

– The main challenge has been to study how to exploit efficiently the one billion transistors silicon capacity available within next five years. The main focus has been in the architectures, e.g. coarse-grain parallelism and clustering, and in design methods, e.g. separation of infrastructure and application development and supporting reuse [1].

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NoC @ KTH

• Two architecture approaches– Nostrum: an application specific NOC platform.

– Eclipse: a general purpose NOC platform

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NoC @ KTH• Nostrum: an application specific NOC platform.

A Nostrum chip is a matrix of resource slots containing integrated embedded systems connected to each other via a two-dimensional mesh network using deflection routing with congestion detection. The resources are heterogeneous and their computing and storage capacity is designed according to application-domain characteristics. The Nostrum design methodology is a combination of platform based design and distributed system design. It emphasizes the reuse and the separation of infrastructure and application functionality [1].

Figure 1. The high-level architectureof Nostrum. (P=processorcore, D=DSP core, C=cache memoryblock, M=embeddedmemory, L=dedicated logic block,re=reconfigurable logic block,rni=resource network interface, andS=switch.) [1]

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NoC @ KTH• Eclipse: a general purpose NOC platform

An Eclipse chip consists of a set of super-pipelined multithreaded processors attached to separate instruction memory modules, interleaved data memory modules connected to each other via a double acyclic two dimensional sparse mesh network with output-buffered greedy routing with two intermediate targets. The design methodology for Eclipse is a variant of computing engine based design and happens completely via software. The functionality is described as a set of sequential and parallel application programs communicating externally and internally via a single step accessible synchronous shared memory [1].

Figure 2. The high-level architecture of

Eclipse. (P=processor,I=instruction memory module,

I/O=I/Odevice, M=data memorymodule, S=switch) [1].

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NoC @ KTH

• Results:– The main results have been Nostrum and Eclipse

architectures and related design methodologies that are covering widely the NOC design space. The NOC concept is a promising approach for extensive reuse and management of complex communication patterns of future systems [1].

– The NOCARC project has produced more than 30 scientific publications. The NOCARC project home page at http://www.imit.kth.se/info/FOFU/NOC/ describes the project and researchers briefly and gives the complete list of publications [1].

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REXAPP architecture and Kernels [3]

Figure-9(a): Conceptual view of a NOC tile

External Memory Interface

RFFront End Interface

Memory DataNOC Switch

Control DataNOC

Switch

Kernel

Inter-chip NOCReplicator

ScratchPadMemory

ControllerRISC Processor

External Memory Interface

RFFront End Interface

Memory DataNOC Switch

Control DataNOC

Switch

Kernel

Inter-chip NOCReplicator

ScratchPadMemory

ControllerRISC Processor

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REXAPP architecture and Kernels [3]

Figure 9(b): An example REXAPP System

MAC APPL.

PHY PHYPHY

A NOCtile

RF Front End

External MemoryDDR2/Flash

REXAPP System Controller

MAC APPL.

PHY PHYPHY

A NOCtile

RF Front End

External MemoryDDR2/Flash

REXAPP System Controller

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A NOC Design Methodology

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Resource development

Fun

ctio

n d

evel

opm

ent

System exists

monitoring

estimation

cosimulation

benchmarking

performanceanalysis

simulation emulation

prototyping

profiling

performancesimulation

mappability estimation

synthesis

design

capacity estimation

modelling

mathematicalanalyses

workloadanalysis

complexityanalysis

System does not exist

Design Flow Space [2]

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Extremely short introduction to existing design flows [2]

– Algorithm on Chip (AoC)• ASIC design flow

• FPGA design flow

– System on Chip (SoC)• Codesign flow

• IP based design flow

• Platform based design flow (Resources on Chip, RoC)

– Configuration design flow

– Software design flow

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Resource development

Fun

ctio

n d

evel

opm

ent

Chip exists

simulation emulationprofiling synthesis

HW design

modelling

mathematicalanalyses

complexityanalysis

System does not exist

AoC Design Flow [2]

Algorithms exists

Algorithm design

feasibility studies

changes into functionality

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Resource development

Fun

ctio

n d

evel

opm

ent

System exists

monitoring

cosimulation

simulation emulation

prototyping

profiling

mappability estimation

synthesis

modelling

mathematicalanalyses

workloadanalysis

System does not exist

CoDesign Flow [2]

SW/HW partitioning

capacity estimation

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Resource development

Fun

ctio

n d

evel

opm

ent

System exists

monitoring

cosimulation

emulation

prototypingmappability estimation

modelling

mathematicalanalyses

workloadanalysis

System does not exist

IP Based Design [2]

Architecturetemplate

estimation

IP block integration

capacity estimation

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Resource development

Fun

ctio

n d

evel

opm

ent

System exists

SW design

modelling

System does not exist

Software Design [2]

Computer exists

monitoring

estimation

benchmarking

prototyping

performancesimulation

Computer design

performance analysis

RTOS services

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10 computers

10 c

ompu

ters

Capacity of Network on Chip [2]

Average SoC design 1 million gates1 billion transistors 250 million gates1 NoC > 200 SoCs

1 GHz clock with RISC computer 1000 MIPS performance

1 NOC capacity 100-10000 GIPS

Applicability of capacity is limited by communication

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“Applications” for NOC [2]

• Multistandard terminal

• Next generation base station

• Simulation of human brain

• Virtual reality creation

• Telepresence

• Holodeck (Star Trek)

• Purpose of Life (Hitch Hikers Guide to Galaxy)

• Simulation of universe

• Commercial operating system :-)

Piece of cake

Realistic applications

Maybe not even for NOC

Real challenges for every archtitecture

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Application characteristics [2]

NOC capacity will be shared by several simultaneous applications

NOC must be adaptable to different workload patterns

Different applications have very different requirement profile

Presentation

Search

Analysis

Communication

Computation

Storage

Communication

Stream-based processing

Parallel processing

tn

tn+

p

Real-time processing

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Network on Chip alternatives [2]

NOC = Network of computation and storage resources

NOC parameters: Number of resourcesTypes of resources

GPUDSPMemoryConfigurable HWCoprocessorsAny combination

Communication capability

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Network on Chip alternatives [2]

Regions are used to encapsulate application requirements

Parallel high-performance datapaths

WCDMA bit-stream processing

OFDM bit-stream processing

Data compression, encryption,decompression, decryption

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Network on Chip alternatives [2]

Memory area

Memorymanagement

Applications

DATABASENOC

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Network on Chip alternatives [2]

Parallel processing engine

IO

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NoC SoC

NOC design challenges [2]

Physical limits -> Architecture basics -> GALS -> Communication principles

Application requirements -> Region concepts ->Heterogenuous resources types -> Multilanguageand method design flows

Overall complexity -> Architecture reuse -> Platform type of design flow

Overall complexity -> Basic control principles -> System services

Manufacturability problems -> Structured approach

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Performance

CostVariability

SystemQuality

Capacity

Energyconsumption

Implementation

Development

ModifiabilityVolume

Flexibility

Complexity

Functionality

Modularity

Cohesion

Coupling

Configurability

Programmability

Applicability

StructuralFunctional

Control

LifetimeManufacturability

Usability

EffortTimeRisk

MaterialsLicencingProduction

ComputationStorage

CommunicationFault toleranceResult quality (accuracy)Responsiveness

ScalabilityEfficiencyUtilisation

Figure of Merit for NOC based systems [2]

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Basic requirements for NOC design methodology [2]

• Reuse

– of intellectual property blocks

• best performance/energy ratio

• best mapping to application characteristics

• Reuse

– of hardware (and architecture)

• best complexity/cost and performance/cost ratio

• only way to even dream of achieving time-to-profit requirements

• Reuse

– of design methods and tools

• only way to deal with heterogenuous application set

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NOC Design Methodology [2]

Generic backbone

NoC system

Optimised Virtual ComponentsDefinition of NOC platform

Optimised Intellectual Property

Features

Applications

Algorithms

Cores

Memories

Accelerators

Instantiation of NoC platform

Code and configuration

“Application area specific IPR”

Product area specific platform

“Product specific IPR”

Communicationstructure

Processors and hardware

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Communication

Structural layers of NOC [2]

Regions

Resources

Hardware units

Executables

Functions

Applications

Configuration

Product

Channels and protocols

Processors, memorires, configurable HW, logic

System control, product behaviour

Resource types, buses, IO

Region types, switches, network interfaces

RTOS, code, HW configurations

Resource management,diagnostics, applications

Execution control, functions

Network management, allocation, operation modes

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Logical layers of NOC [2]

• Backbone– Communication resources

– Basic set of system services

– Architecture design methods and tools

• Platform– Computation and storage resources

– System services

– Application design methods and tools

• System– Functionality of computation(code, configuration)

– Control (OS, NetOS)

– Validation and verification support

Communication

Regions

Resources

Hardware units

Executables

Functions

Applications

Configuration

Product

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Development of NOC based systems [2]

BACKBONE

PLATFORMS

SYSTEMS

Baseband platform

Database platform

Multimedia platform

High-perforrmance communication systems

High-capacity communication systems

Virtual reality games

Entertainment devices

Personal assistant

Data collectionsystems

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Resource development

Fun

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opm

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NOC System

System does not exist

Using Design Space for NOC [2]

Platform

Backbone

Architecturedesign

Applicationmapping

System Services

Operation principles

Communicationchannels

Non-configurable hardware

Product differentiation

Product area specialisation

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System Services [2]• Purpose to hide implementation

details from application developer– Execution services

• Communication, resource allocation and conversion services

– Control services• Power management, reconfiguration,

load migration, fault detection and recovery, data collection and analysis

– Development support services• Language interfacing, compilers,

libraries, optimisations, debugging, testing, validation, etc.

• System services are part of backbone and platform

NOC Platform Chip

System Services

Applications

Thickness of service layersP

erfo

rman

ce

ASIC

SW

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NOC Platform development [2]

• Scaling problem– How big NOC is needed? What are the application area requirements?

• Region definition problem– What kind of regions are needed? What kind of interfaces between

regions? What are the capacity requirements for the regions?

• Resource design problem– What is needed inside resources? Internal computation type and internal

communication?

• Application mapping flow problem– What kind of languages, models and tools must be supported? How to

validate and test the final products?

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NOC Application Development [2]

• Mapping problem– How to partition applications for NOC resources? How to allocate

functionality effectively? Is the performance adequate? Is the resource usage in balance?

• Optimisation problem– How to perform global optimisation of heterogenuous applications? How

to define right optimisation targets? How to utilise application/resource type specific tools?

• Validation problem– Are the contraints met? Are the communication bottlenecks or power

consumption hot spots? How to simulate 10000 GIPS system? How to test all applications?

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Methods & Tools [2]

• Analysis of applications (characterisation)– analysis of complexity,

computation type, communication requirement, storage, etc.

– for scaling, region and resource type selection, and application mapping

– Different abstraction levels: workload model, application model, execution model

• Validation of decisions– network simulations at various

abstraction levels (effects of mapping)

• Estimation of quality characteristics– global vs. local optimisation of

the system

• SW architecture vs. HW architecture– computation vs. engine

• Development support– virtual execution platforms for

application developers

– integration of existing design tools for resource level design

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Conclusions [2]

• Development of NOC systems will be a huge effort– reuse in all levels is a must

• reuse of architecture, hardware and software in product

• reuse of different languages, methods, tools and practices during development

• Backbone, platform, system based design methodology apporach– provides variability and performance

• Analysis, decision, estimation and validation methods are the cornerstones of NOC development – complexity, functionality, workload vs. capacity, performance, efficiency

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References

1. Kari Tiensyrjä (Kari.Tiensyrja@vtt.fi), Axel Jantsch “NOCARC: Network On Chip Architectures (Poster)” Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden

2. Juha-Pekka Soininen (VTT Electronics Oulu, Finland), “Part V: A NOC Design Methodology” NOCARC project, System on Chip workshop, villach, Austria, 17.9.2001

3. N. D. Gohar, Ahmed Hemani, “National ICT R&D Fund Proposal / Application for Technical Development and Research Grant”

Thank You.