WEBENCH® Clock Architect

Design And Simulate Clock Circuits And Complex Clocking Trees

1

Clocks are Everywhere

2

If a system has….

Processors(FPGA, DSP, ASIC, ARM/MIPS-based processor, etc.)

I/O(USB controller, backplane SERDES, etc.)

Connectivity(Switch ASIC, Ethernet MAC/PHY, WiFi, 3G/LTE modem, etc.)

Clock IC

Data Converters(High speed & precision ADC, DAC, Analog Front-Ends)

… there are certainly multiple crystals or oscillators used as clock sources

…THAT CAN BE REPLACED BY

A REFERENCE & CLOCK IC FOR LOWER BOM COST & BETTER RELIABILITY

or

or

or

or

25 MHz

General Purpose Clocking Application

3

FPGA

10/100

PHY

(MII)

USB

Controller

10/100 PHY

(RMII)

Crystals + OscillatorsCrystals: 4

Oscillator: 2

Clock: None

Example Case

25 MHz

50 MHz

48 MHz

100 MHz

25 MHz

Industrial & Consumer Crystal & Oscillator Replacement

General Purpose Clocking Application

4

FPGA

USB

Controller

CDCE(L)9xx

Clock

1 x Crystal + 1 x ClockCrystals: 1

Oscillator: None

Clock: 1

Example Case

Crystals + Oscillators Disadvantage

→More complex & expensive BOM

→Lower reliability (startup issues with crystals due

to board-to-board variation)

25 MHz

Industrial & Consumer Crystal & Oscillator Replacement

Crystals + OscillatorsCrystals: 4

Oscillator: 2

Clock: None

10/100

PHY

(MII)

10/100

PHY

(RMII)

Performance Clocking Applications

Wireless RRU

Wired/Optical Communications Networking

Wireless/Wired/Optical Comms, Networking, and Test & MeasurementTest & Measurement

Overview of WEBENCH® Clock Architect

Advanced

Selection

Algorithm

Input Frequencies

Fixed Output Frequencies

Tunable Output Frequencies

Phase Noise Bode Plot Lock Time

Tool Capabilities

Industry’s first Clock & Timing tool that does it all

– Recommends a system clock tree solution with one or more parts

– Allows users to customize PLL Loop Filter Design

– Simulates phase noise, spurs, and lock time

– Cascades noise from a device upstream in the clock tree solution to a downstream device

Provides quick and hassle-free experience for a user looking for an optimized clock tree solution. Output clock phase noise simulations match real silicon performance

New Features

• Custom Phase Noise Profile for XOs, VCOs, and VCXOs

• Part Filters

• Spurs & Lock Time

• Share Design

• Advanced Loop Filter Configuration

• Active Filters

Accessing from TI.com Launch Panel

Click on Clocks tab

Click Start Design

Accessing from Product Folder

Click to Launch

Clock Architect

Save Trace Data

11

PDF Design Report

Click Print

Resources

• Try the WEBENCH Clock Architect tool ti.com/clockarchitect

• Find out more about TI clock and timing products, applications tools

and support, visit ti.com/clocks

• Visit ti.com

• Video

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