Upload File

clock domains & divider clock & reset distribution

  • Home
  • Documents
  • Clock domains & divider Clock & reset distribution
30
Clock domains & divider Clock & reset distribution A. Kluge Feb 5 & 6, 2013

Upload: zudora

Post on 24-Feb-2016

74 views

Category:

Documents


0 download

Report

Tags:

DESCRIPTION

Clock domains & divider Clock & reset distribution. A. Kluge Feb 5 & 6, 2013. clk domains. pixel_hit clk_config clk_dll clk_sync ( hronous ) clk_serial clk_multi_serial. clk_config. clk_multi_serial. clk_sync. clk_serial. clk_dll. Clk distribution: serial 3.2 Gbit /s. - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: Clock domains & divider Clock & reset distribution

Clock domains & dividerClock & reset

distributionA. Kluge

Feb 5 & 6, 2013

Page 2: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clk domains pixel_hit clk_config clk_dll clk_sync(hronous) clk_serial clk_multi_serial

A. Kluge 2

Page 3: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

A. Kluge 3

clk_syncclk_serial

clk_multi_serial

clk_config

clk_dll

Page 4: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Clk distribution: serial 3.2 Gbit/s

A. Kluge 4

Page 5: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Clk distribution: serial 3.2 Gbit/s

A. Kluge 5

30 bit shift register

every 6th clock cycle one word is sent to serializer

every 53 MHz new word of 48 bits on 4 outputs 48/4 ports * 53 MHz = 640 MHz

Page 6: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clk domain crossingpixel_hit clk_sync

hitArbiterclk_sync clk_serialclk_sync clk_multi_serialclk_config clk_syncclk_dll clk_sync tdc,

qchip

A. Kluge 6

Page 7: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

A. Kluge 7

clk_syncclk_serial

clk_multi_serial

clk_config

clk_dll

Page 8: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clk_sync clk_serial clock_enable_generator frequ_clk_sync =

6 * frequ_clk_fifo_read = 6 * frequ_enable_clk_sync 12 * for modes 1, 4, 6

qchip runs on clk_sync flip flops are enabled only upon enable_clk_sync TDC is read-out only every 6th (12th) clk_sync cycle serializer is loaded only every 6th (12th) clk_sync

cycle

A. Kluge 8

Page 9: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clock_enable_generator

Serializer provides sync signal - clk_fifo_read frequency = parallel_word_freqency falling edge + 3 (3.5) serial_frequ/2 marks parallel

load time

clk_enable_generator synchronizes clk_fifo_read to clk_sync domain waits for time-out measures position of clk_fifo_read, once

does not re-adjust later-on produces enable_clk_sync pulse around rising edge

of clk_fifo_read marks safe parallel_word change time

A. Kluge 9

Page 10: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clk_sync clk_serial

A. Kluge 10

first_enable_after_delay

Page 11: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clock_enable_generator

hold/setup [ns] mode 0: 11.6-9.5 / 13.4/15.5 mode 1: 15.7-13.6 / 9.3 – 11.4 mode 2: 10.3 – 7.2 / 8.5 – 11.6

A. Kluge 11

Page 12: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clk_enable_generator

A. Kluge 12

Page 13: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

A. Kluge 13

clk_syncclk_serial

clk_multi_serial

clk_config

clk_dll

Page 14: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

multi_serial_synchronisationclk_sync clk_multi_serial

synchronizes enable_clk_sync into clk_multi_serial domain

measures the position of enable_clk_sync once

locks parallel_load time in middle of two enable_clk_sync pulses

hold/setup time of ~ 9 ns

A. Kluge 14

Page 15: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

multi_serial_synchronisationclk_sync clk_multi_serial

A. Kluge 15

Page 16: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

multi_serial_synchronisationclk_sync clk_multi_serial

A. Kluge 16

Page 17: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

A. Kluge 17

clk_syncclk_serial

clk_multi_serial

clk_config

clk_dll

Page 18: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clk_config clk_sync

A. Kluge 18

CLK_SYNC

CLK_SYNC

CLK_SYNC

CLK_SYNC

Page 19: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Operation modes

A. Kluge 19

serialPLL2.4lowClkSync

serialPLL2.4highClkSync

serialPLL3.2

ext320lowClkSync

ext320highClkSync

ext480lowClkSync

ext480highClkSync

pllOverride

# 0 1 2 3 4 5 6 7code 00111

0000110 001100 H110H

0H100H0

H110H1

H100H1

1011H0

clkInDigital 320 320 320 320 320 480 480 320clkPLL 2400 2400 3200 - - - - 320clkSync 240 480 320 160 320 240 480 32clkFIFOread

40 40 53 27 27 40 40 5.3clkMultiSerial

480 480 640 320 320 480 480 64clkConfig 320 320 320 320 320 240 240 320

Page 20: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

PLL & clock divider

A. Kluge 20

Page 21: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013A. Kluge 21

Page 22: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013A. Kluge 22

Page 23: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013A. Kluge 23

Page 24: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013A. Kluge 24

Page 25: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

clock distribution Clock_sync on 5 outputs @PLL&Serializer

block 4 x quarter chip + 5 x TDC & 1 x configuration

block distributed on the top level with clock tree

TDC distributes clock to dll_state_machine_and_lock_detector internally

A. Kluge 25

Page 26: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Reset distribution Reset signal arrives from from two sources

externally from a low active input pad internally from the configuration block reset_synchronizer_asynchron

synchronizes the asynchronously arriving external reset_global_i signal to clk_sync in the config block and in the 4 quarter chips blocks

A. Kluge 26

Page 27: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013A. Kluge 27

reset_synchronizer_asynchron

Page 28: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Reset distribution quarter chip distributes reset signal to TDC blocks

In TDC reset is synchronized using reset_synchronizer block.

Internally TDC forwards reset to dll_state_machine_and_lock_detector block

where again a reset_synchronizer is used. Staged reset distribution allows simpler

propagation delay management Drawback that all TDCpix blocks are reset in

stages of 3 clock cycles no impact on functionality All synchronizers triplicated and internal reset

signals are forwarded as high active signals whereas external reset_global_i input is low active

A. Kluge 28

Page 29: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Reset coarse counter External signal which sets the coarse counter to 0

Connected to dll_clk_fanout fowards it to TDC as a one clock cycle long pulse

to the quarter chip as a two cycle long pulse Two cycle long pulse is needed as the copy of the

coarse counter in the qchip is running on clk_sync on not on clk_dll as in the TDC

If clk_sync is slower than clk_dll one clk_dll long pulses might not be registered by the qChip

Synchronisation of reset_coarse_count uses reset_synchronizer_asynchron

Reset_coarse_counter also can be initiated by software via the configuration block

A. Kluge 29

Page 30: Clock domains & divider Clock & reset distribution

Feb 5 & 6, 2013

Clock and reset distribution

A. Kluge 30


1-to-8 Differential to Universal Output Clock Divider

Design of a Single Phase Clock Multiband Flexible Divider ... · divider is implemented using an injection-locked di- ... The proposed wideband multi-modulus prescaler is similar

DECADE COUNTER/DIVIDER WITH DECODED - … in display applications where low power dissipation and/or low package count are important. This device has CLOCK, RESET, CLOCK INHIBIT, DISPLAY

Using Redundant Data Paths and Clock Domains in Ethernet …...Using Redundant Data Paths and Clock Domains in Ethernet TSN for Mission-Critical Network Reliability Presented by: Shrikant

Multiple Clock and Voltage Domains for Chip Multi Processorspeople.cs.pitt.edu/~kirk/cs3150spring2010/Multiple_Clock... · 2010. 4. 12. · Multiple Clock and Voltage Domains for

Chapter 3 Design of Clock dividers - Shodhgangashodhganga.inflibnet.ac.in/bitstream/10603/117846/11/11... · 2018-07-04 · ing the power consumption of the clock divider circuit

Chapter 4 Design of Fractional-N clock dividershodhganga.inflibnet.ac.in/bitstream/10603/117846/12/12... · 2018. 7. 4. · Design of Fractional-N clock divider 4.1 INTRODUCTION The

5. Clock Networks and PLLs in Stratix IV Devices · clock structures that provide up to 236 unique clock domains (16 GCLKs + 88 RCLKs + 132 PCLKs) within the Stratix IV device and

March 4, 2009L13-1 Multiple Clock Domains Arvind Computer Science & Artificial Intelligence Lab Massachusetts Institute of

MTBF Estimation in Coherent Clock Domainsran/papers/MTBFCoherentCDC-beer-AS… · MTBF Estimation in Coherent Clock Domains Salomon Beer 1, Ran Ginosar 1, Rostislav (Reuven) Dobkin

A hybrid CMOS Clock Divider for PLL of 60GHz Transceiverpeople.sutd.edu.sg/~kiatseng_yeo/wp-content/... · A hybrid CMOS Clock Divider for PLL of 60GHz Transceiver ... A hybrid multi-mode

Dough Divider B / V 300 - wpbakerygroup.org · B / V 300 1/2 Dough Divider 26.08.2010 Dough Divider B / V 300 Universal Dough Divider Specification This dough divider is suitable

LTC6954 - Low Phase Noise, Triple Output Clock ...cds.linear.com/docs/en/datasheet/6954f.pdf · Triple Output Clock Distribution Divider/Driver ... l 640 775 950 mVPK Differential

Dec-2009Chip with Multiple Clock and Voltage Domains 1 Multiple Clock and Voltage Domains for Chip Multi Processors December - 2009 Efraim Rotem Intel

Multiple Clock Domains (MCD) Continued … Arvind with Nirav Dave Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology November

Issues Multiple clock domains Multiple frequencies Clock skew between clock domains On-chip PLL generated clocks Multiple PLLs for deskewing

Multiple Clock Domains

LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 ... · Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. Power

LC863532B, LC863528B CMOS IC FROM …pdf.dzsc.com/LC8/LC863528.pdfBus cycle time Instruction cycle time Clock divider System clock oscillation Oscillation frequency Voltage 0.424 µ

AD9522-x Evaluation Board - Analog Devices · noise PLL clock synthesizer featuring an ... divider and channel divider increases the VCO frequency to ... allowing you to select which

Rotating Clock Divider Eurorack Module User Manual PCB version … · 2020. 7. 7. · Rotating Clock Divider Eurorack Module User Manual PCB version 1.2 (released November 2014) Firmware

Clock and Synchronization - Cleveland State University · – Partition a system into multiple clock domains – Design and verify subsystem in same clock domain as a synchronous

E cient Self-Timed Interfaces for Crossing Clock …...E cient Self-Timed Interfaces for Crossing Clock Domains by Ajanta Chakraborty B.Eng. Bhopal Engineering College, 2001 A THESIS

Frequency Divider 2 - perdrix.co.ukperdrix.co.uk/FrequencyDivider/Frequency Divider 2.1.pdfThe main divider circuit requires a 10MHz square wave input clock signal at CMOS signal levels

Clock Skew Scheduling with Delay Padding for Prescribed ...€¦ · Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains Chuan Lin and Hai Zhou Jan 25, 2007 (2) Outline

Dough Divider V 700 - africanbakery.comafricanbakery.com/PDFs/V700UK.pdfV 700 1/2 Dough Divider 26.08.2010 Dough Divider V 700 Dough Divider Specification Universal dough divider,

Multi-Domain Verification: When Clock, Power and Reset ... · Multi-Domain Verification: When Clock, Power and Reset Domains Collide ... I/O interfaces, ... or reset domain crossing

BMC 004. Voltage Controlled Clock/Divider Revision 2.0 ... · 3.Random Clock/Divider mode. Section II. Building The Module 1.Decide before you build. 2.Board Layout 3.Bill of Materials

ECE 448: Lab 5 Serial Communications. Part 1: Serial Communications Part 2: Clock Management Part 3: Clock Domains Part 4: User Constraint File (UCF)

Trabon Divider Valves - C&C Industrial Sales (CCIS)divider valve is the first divider valve downstream from the lube pump. A secondary divider valve is any divider valve receiving

MSP430 Clock System and Timer · MSP430 Basic Clock Module zClock Signals: zACLK: Auxiliary clock. The signal is sourced from LFXT1CLK with a divider of 1, 2, 4, or 8. (The calibration

Rotating Clock Divider - 4ms Company · Rotating Clock Divider Eurorack Module User Manual v1.0.1 to 1.0.3 4ms Pedals Features •Divide-by-1 to Divide-by-64, on 8 output jacks •CV

Dough divider Parta U - Bakery EquipmentPPartaUspec.pdf · Parta U 1/2 Dough divider 15.11.2013 Dough divider Parta U Universal dough divider Specification A unique dough divider,

Synchronous Serial Controller (SSC)sewoon.com/icmaster/Semi/atmel/pdf/doc1762.pdf · 2003. 12. 11. · Synchronous Serial Controller (SSC) 1762A–11/01 Clock Divider The Clock Divider

Floorplanning Algorithm for multiple clock domains - · PDF fileFloorplanning Algorithm for multiple clock domains Changhong Zhao, Jian Chen, Dian Zhou, Xiaofang Zhou, Xuan Zeng ASIC