wave pipe lining

WAVE PIPELININGWAVE PIPELINING

Aneesh.RBroadcast and Communication Group

Centre for development of Advance ComputingThiruvananthapuram

[email protected]

http://www.pdfcomplete.com/cms/hppl/tabid/108/Default.aspx?r=q8b3uige22

Usual determination of Clock Period

ØClock period taken to be greater than or equal to critical path delay (delay of path with longest computation time).ØFor a non critical path, delay may be much smaller

than critical path delay. ØSo, on clocking system, gates along non critical path

remain idle for a major portion of clock period.

Wave pipelining Aneesh.R


Usual determination of Clock Period (contd)

ØOnly 1 wave of data between register stages.ØInputs to output register remain stable for a

significant portion of clock cycle.ØCombinational block not operating at maximum rate.



What is Wave Pipelining?ØAlso called maximum rate pipelining.ØClock speed increased by reducing idle time of

non critical paths.ØClock frequency increased without increasing

number of internal storage elements (latches or registers). ØTechnique for pipelining digital system by

equalizing delays in combinational logic circuit.ØUse of multiple coherent waves of data between

storage elements by clocking system faster than propagation delay between registers.



What is Wave Pipelining? (contd)



What is Wave Pipelining? (contd)ØNew inputs can be applied to a combinational

block before results of current inputs are available at output. ØData values at first set of registers changed before

old values have propagated to next set of registers.ØSystem and circuit level analysis done to

determine time of application of new data.ØSystem level analysis accounts for clock period

and clock skew.




ØCircuit level analysis estimates minimum and maximum delays through combinational logic circuit.ØClock period can be reduced as long as data from a

clock cycle does not overwrite data from the previous clock cycle.ØClocking at a frequency greater than maximum

pipeline rate mixes the waves of data.




Wave pipelined system and data flowNon pipelined system and data flow




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ieholdsetup ttttttttTclk ∆+∆+∆+∆+++−≥ min)max(




Ø(t max - t min) reduced for higher throughput.ØRequires balanced propagation paths for

t max = t min.ØBalancing delays difficult in large circuits due to:§ Path variation due to logic depth in the architecture.§ Unequal rise/ fall times.§ Delay variations in the basic building blocks.§ Temperature and process variations.



Requirements of an efficient wave pipelined system

ØA logic which provides equal propagation delay and rise / fall times for all input combinations.ØA delay element which perfectly emulates

combinational logic block delay.ØAn architecture having identical propagation paths.ØIdentical effect of temperature and process

variations on all the propagation paths of the architecture.



Implementation of Wave Pipelined Systems

ØChoice of appropriate logic style crucial.ØMismatches in propagation delay at building blocks

can cause system failure.ØStatic CMOS offers good packing density but

propagation delay is highly data dependent.ØNPCPL seems to be a better alternative for

implementing wave pipelined system due to symmetric nature.



NPCPL (Normal Process Complementary Pass Transistor Logic)



NPCPL (contd)

ØUses NMOS pass transistors.ØTrue and complementary inputs.Ø2 pass blocks generating true and complementary

outputs.ØLevel restoring inverters to restore degraded

voltage levels at output of pass transistors to full CMOS levels.ØThreshold voltage of inverter (Vth) is most critical

parameter in design.



NPCPL (contd)ØIncrease in Vth increases fall time and transition

delay of NPCPL building block, thereby affecting performance of wave pipelined circuit.

ØVth controlled by adjusting



NPCPL (contd)ØW ratio determined to get equal 0->1 and 1->0

delays and equal rise/fall times.ØCan realize all the major 2-input boolean

functions with identical propagation delays.ØProvides identical logic depth and hence equal

delay for all logic gates, due to symmetric nature.ØUse as delay element to mimic delay of 2 – input

gates. ØAdvantages: high throughput, low latency, low

area.ØDisadvantage: poor noise margin.



NPCPL (contd)



Advantages of Wave Pipelining

ØAbsence of pipeline latches leads to decrease in area and decrease in power consumption.ØSimpler clock distribution.ØHigher throughput, compared to corresponding

synchronous designs.



Disadvantages of Wave Pipelining

ØRequires special design algorithms to equalize lengths of all paths.ØData dependent delay fluctuations cannot be fully

eliminated, which degrade performance.ØLayout is critical for delay balancing and hence,

an automatic layout cannot be used.



THANK [email protected]



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