vn0104 n-channel enhancement-mode vertical dmos fet data …

2021 Microchip Technology Inc. DS20005975A-page 1

VN0104

Features• Free from Secondary Breakdown• Low Power Drive Requirement• Ease of Paralleling• Low CISS and Fast Switching Speeds• Excellent Thermal Stability• Integral Source-Drain Diode• High Input Impedance and High Gain

Applications• Motor Controls• Converters• Amplifiers• Switches• Power Supply Circuits• Drivers (Relays, Hammers, Solenoids, Lamps,

Memories, Displays, Bipolar Transistors, etc.)

General DescriptionThe VN0104 Enhancement-mode (normally-off)transistors use a vertical DMOS structure and awell-proven silicon-gate manufacturing process. Thiscombination produces a device with the powerhandling capabilities of bipolar transistors and the highinput impedance and positive temperature coefficientinherent in MOS devices. Characteristic of all MOSstructures, these devices are free from thermalrunaway and thermally induced secondary breakdown.Microchip’s vertical DMOS FETs are ideally suited for awide range of switching and amplifying applicationswhere very low threshold voltage, high breakdownvoltage, high input impedance, low input capacitanceand fast switching speeds are desired.

Package Type

See Table 3-1 for pin information.

GATE

SOURCEDRAIN

3-lead TO-92(Top view)

N-Channel Enhancement-Mode Vertical DMOS FET

VN0104

DS20005975A-page 2 2021 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings†Drain-to-Source Voltage ...................................................................................................................................... BVDSSDrain-to-Gate Voltage ......................................................................................................................................... BVDGSGate-to-Source Voltage ......................................................................................................................................... ±20VOperating Ambient Temperature, TA ................................................................................................... –55°C to +150°CStorage Temperature, TS ..................................................................................................................... –55°C to +150°C

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only, and functional operation of the device at those or any other conditions above thoseindicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions forextended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICSElectrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle

Parameter Sym. Min. Typ. Max. Unit Conditions Drain-to-Source Breakdown Voltage BVDSS 40 — — V VGS = 0V, ID = 1 mAGate Threshold Voltage VGS(th) 0.8 — 2.4 V VGS = VDS, ID = 1 mA

Change in VGS(th) with Temperature ΔVGS(th) — –3.8 –5.5 mV/°C VGS = VDS, ID = 1 mA (Note 1)

Gate Body Leakage Current IGSS — — 100 nA VGS = ± 20V, VDS = 0V

Zero-Gate Voltage Drain Current IDSS

— — 1 µA VGS = 0V, VDS = Maximum rating

— — 100 µAVDS = 0.8 Maximum rating,VGS = 0V, TA = 125°C (Note 1)

On-State Drain Current ID(ON)0.5 1 — A VGS = 5V, VDS = 25V2 2.5 — A VGS = 10V, VDS = 25V

Static Drain-to-Source On-State Resistance RDS(ON)— 3 5 Ω VGS = 5V, ID = 250 mA— 2.5 3 Ω VGS = 10V, ID = 1A

Change in RDS(ON) with Temperature ΔRDS(ON) — 0.7 1 %/°C VGS = 10V, ID = 1A (Note 1)Note 1: Specification is obtained by characterization and is not 100% tested.


VN0104

AC ELECTRICAL CHARACTERISTICSElectrical Specifications: TA = 25°C unless otherwise specified. All AC parameters are not 100% sample tested.

Parameter Sym. Min. Typ. Max. Unit Conditions Forward Transconductance GFS 300 450 — mmho VDS = 25V, ID = 500 mAInput Capacitance CISS — 55 65 pF VGS = 0V,

VDS = 25V,f = 1 MHz

Common-Source Output Capacitance COSS — 20 25 pFReverse Transfer Capacitance CRSS — 5 8 pFTurn-On Delay Time td(ON) — 3 5 ns

VDD = 25V,ID = 1A,RGEN = 25Ω

Rise Time tr — 5 8 nsTurn-Off Delay Time td(OFF) — 6 9 nsFall Time tf — 5 8 nsDIODE PARAMETERDiode Forward Voltage Drop VSD — 1.2 1.8 V VGS = 0V, ISD = 1A (Note 1)Reverse Recovery Time trr — 400 — ns VGS = 0V, ISD = 1ANote 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty

cycle

TEMPERATURE SPECIFICATIONSParameter Sym. Min. Typ. Max. Unit Conditions

TEMPERATURE RANGEOperating Ambient Temperature TA –55 — +150 °CStorage Temperature TS –55 — +150 °CPACKAGE THERMAL RESISTANCE3-lead TO-92 JA — 132 — °C/W

THERMAL CHARACTERISTICS

PackageID (Note 1)

(Continuous)(mA)

ID(Pulsed)

(A)

Power Dissipation at TA = 25°C

(W)

IDR (Note 1)(mA)

IDRM(A)

3-lead TO-92 350 2 1 350 2Note 1: ID (continuous) is limited by maximum rated TJ.

VN0104


2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: Output Characteristics.

FIGURE 2-2: Transconductance vs. Drain Current.

FIGURE 2-3: Maximum Rated Safe Operating Area.

FIGURE 2-4: Saturation Characteristics.

FIGURE 2-5: Power Dissipation vs. Case Temperature.

FIGURE 2-6: Thermal Response Characteristics.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g. outside specified power supply range) and therefore outside the warranted range.

VDS (volts)

I D (a

mpe

res)

0 10 20 30 40

2.5

2.0

1.5

1.0

0.5

0

VGS = 10V

8.0V

6.0V

4.0V

3.0V

5.0V

7.0V

9.0V

GFS

(sie

men

s)

ID (amperes)

1.0

0.8

0.6

0.4

0.2

00 0.2 0.4 0.6 0.8 1.0

VDS = 25V

TA = -55OC

25OC

125OC

VDS (volts)

I D (a

mpe

res)

0.1 1.0 10 100

10

1.0

0.1

0.01

TO-92 (DC)

TC = 25OC

VDS (volts)0 2.0 4.0 6.0 8.0 10

2.5

2.0

1.5

1.0

0.5

0

I D (a

mpe

res)

VGS = 10V

8.0V

6.0V

4.0V

3.0V

5.0V

7.0V

9.0V

TC (OC)

P D (w

atts

)

2.0

1.0

00 25 50 75 100 125 150

TO-92

Ther

mal

Res

ista

nce

(nor

mal

ized

)

tP (seconds)

1.0

0.8

0.6

0.4

0.2

0

TO-92PD = 1.0WTC = 25OC

0.001 0.01 0.1 1.0 10


VN0104

FIGURE 2-7: BVDSS Variation with Temperature.

FIGURE 2-8: Transfer Characteristics.

FIGURE 2-9: Capacitance vs. Drain-to-Source Voltage.

FIGURE 2-10: On-Resistance vs. Drain Current.

FIGURE 2-11: V(th) and RDS Variation with Temperature.

FIGURE 2-12: Gate Drive Dynamic Characteristics.

-50 0 50 100 150

1.1

1.0

0.9

BVD

SS (n

orm

aliz

ed)

Tj (OC)

VGS (volts)

I D (a

mpe

res)

0 2 4 6 8 10

2.5

2.0

1.5

1.0

0.5

0

TA = -55OC

25OC

VDS = 25V

125OC

100

75

50

25

0

C (p

icof

arad

s)

0 10 20 30 40

f = 1.0MHz

CISS

COSS

CRSS

VDS (volts)

RD

S(O

N) (Ω

)

ID (amperes)0 0.5 1.0 1.5 2.0 2.5

5.0

4.0

3.0

2.0

1.0

0

VGS = 5.0V

VGS = 10V

V GS(

th) (n

orm

aliz

ed)

RD

S(O

N) (n

orm

aliz

ed)

1.6

1.4

1.2

1.0

0.8

0.6-50 0 50 100 150

V(th) @ 1.0mA

RDS @ 10V, 1.0A

1.9

1.6

1.3

1.0

0.7

0.4

Tj (OC)

RDS @ 5.0V, 0.25A

QG (nanocoulombs)

V GS (v

olts

)

10

8

6

4

2

00 0.2 0.4 0.6 0.8 1.0

VDS = 10V

40 pF

40V

80 pF

VN0104


3.0 PIN DESCRIPTIONThe details on the pins of VN0104 are listed inTable 3-1. Refer to Package Type for the location ofthe pins.

TABLE 3-1: 3-LEAD TO-92 PIN FUNCTION TABLEPin Number Pin Name Description

1 Source Source2 Gate Gate3 Drain Drain


VN01044.0 FUNCTIONAL DESCRIPTIONFigure 4-1 illustrates the switching waveforms and testcircuit for VN0104.

FIGURE 4-1: Switching Waveforms and Test Circuit.

90%

10%

90% 90%

10%10%

PulseGenerator

VDD

RL

OUTPUT

D.U.T.

t(ON)

td(ON)

t(OFF)

td(OFF)tr

INPUT

INPUT

OUTPUT

10V

VDD

RGEN

0V

0V

tf

TABLE 4-1: PRODUCT SUMMARY

Device BVDSS/BVDGS(V)

RDS(ON)(Maximum)

(Ω)

IDSS(Minimum)

(A)VN0104 40 3 2

VN0104


5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for product code or customer-specific information. Package may ornot include the corporate logo.

3e

3e

3-lead TO-92

YWWNNN

XXXXXXXX e3

Example

122957

VN0104N3 e3


VN0104

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

VN0104


NOTES:


VN0104APPENDIX A: REVISION HISTORY

Revision A (September 2021)• Converted and merged Supertex Doc#

DSFP-VN0104 to Microchip DS20005975A• Added a pin function table• Changed the package marking format• Removed the 3-Lead TO-92 N3 P002, P003,

P005 and P014 media types for VN0104 to align packaging specifications with the actual BQM

• Made minor text changes throughout the document

VN0104


PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Examples:

a) VN0104N3-G: N-Channel Enhancement-Mode, Vertical DMOS FET, 3-lead TO-92, 1000/Bag

b) VN0104N3-G-P013: N-Channel Enhancement-Mode, Vertical DMOS FET, 3-lead TO-92, 2000/AMMO Pack

PART NO.

Device

Device: VN0104 = N-Channel Enhancement-Mode Vertical DMOS FET

Package: N3 = 3-lead TO-92

Environmental: G = Lead (Pb)-free/RoHS-compliant Package

Media Types: (blank) = 1000/Bag for an N3 Package

P003 = 2000/Reel for an N3 Package

P013 = 2000/AMMO Pack for an N3 Package

XX

Package

- X - X

Environmental Media Type Options


Information contained in this publication is provided for the solepurpose of designing with and using Microchip products. Infor-mation regarding device applications and the like is providedonly for your convenience and may be superseded by updates.It is your responsibility to ensure that your application meetswith your specifications.

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IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KINDWHATSOEVER RELATED TO THE INFORMATION OR ITSUSE, HOWEVER CAUSED, EVEN IF MICROCHIP HASBEEN ADVISED OF THE POSSIBILITY OR THE DAMAGESARE FORESEEABLE. TO THE FULLEST EXTENTALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ONALL CLAIMS IN ANY WAY RELATED TO THE INFORMATIONOR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IFANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIPFOR THE INFORMATION. Use of Microchip devices in life sup-port and/or safety applications is entirely at the buyer's risk, andthe buyer agrees to defend, indemnify and hold harmlessMicrochip from any and all damages, claims, suits, or expensesresulting from such use. No licenses are conveyed, implicitly orotherwise, under any Microchip intellectual property rightsunless otherwise stated.

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© 2021, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-8863-7

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vn0104 n-channel enhancement-mode vertical dmos fet data …

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