VLSI Digital Systems Design

• Layout of:• Standard Cells• Gate Arrays• Sea of Gates• Rules of Thumb• Pass Gates• Multiplexers

Standard Cells

● Different cells need different areas● Fix one dimension: height

– VDD and VSS busses traverse the cell– At top and bottom– Connect by abutment– Internal area for connecting transistors

● Vary width● Also called polycells

Standard Cell Transistor Sizing

● All pMOS same size: maximum allowed● All nMOS same size: maximum allowed● Further optimization:

– Adjust individual transistor sizes– Larger transistors

● Pro: Larger drive● Con: Larger input and output capacitance, area

– Smaller transistors● Con: Smaller drive● Pro: Smaller input and output capacitance, area

Standard Cell

aa bb cc zzddddddaaddddddbbddddddccddddddzzdddddddddddddd-Vdd aa dd bb cc dd zz pppp--ppddpp--pppppp--ppdd zz **pp--pp**pp--pp**pp--pp** zz mmpp--pppppp--ppmmpp--pppp zz mm aa bb mm cc zz mmmmaammmmmmbbmmmmmmccmmmmmm** aa bb cc zz aa bb cc zz aa bb cc zz aa bb cc zz aa bb cc zz nnnn--nnnnnn--nnnnnn--nnnn zz **nn--nnnnnn--nnnnnn--nn**mm** ssnn—-nnnnnn--nnnnnn--nnss zz ss aa bb cc ss zzssssssaassssssbbssssssccsssssszzssssssssssssss-Vss aa bb cc zz

Standard Cell with Reduced nMOS Capacitance

aa bb cc zzddddddaaddddddbbddddddccddddddzzdddddddddddddd-Vdd aa dd bb cc dd zz pppp--ppddpp--pppppp--ppdd zz **pp--pp**pp--pp**pp--pp** zz mmpp--pppppp--ppmmpp--pppp zz mm aa bb mm cc zz mmmmaammmmmmbbmmmmmmccmmmmmm** aa bb cc zz aa bbbbbb cc zz aa bb cc zz aa bb cccccccccc zz aa bb cc zz nnnn--nn--nn--nnnn zz **nn--nn--nn--nn**mmmmmmmmmm** ssnn—-nn--nn--nnss zz ss aa bb cc zzssssssaassbbssccsssssssssssssszzssssssssssssss-Vss aa bb cc zz

Standard Cell with Metal2 Ports

aa 22 bb 22 cc 22 22ddddddaadd22ddbbdd22ddccdd22dd22dddddddddddddd-Vdd aa 22 bb 22 cc 22 22 pppp--pp22pp--pp22pp--pp22 22 **pp--pp22pp--pp22pp--pp22 22 mmpp--pp22pp--pp22pp--pp22 22 mm aa 22 bb 22 cc 22 22 mmmmaamm22mmbbmm22mmccmm22mm** aa 22 bb 22 cc 22 22 aa ** bb ** cc ** 22 aa mm bb mm cc mm 22 aaaa** bbbb** cccc** 22 aa 22 bb 22 cc 22 22 nnnn--nn22nn--nn22nn--nn22 22 **nn--nn22nn--nn22nn--nn22mm** ssnn—-nn22nn--nn22nn--nn22 22 ss aa 22 bb 22 cc 22 22ssssssaass22ssbbss22ssccss22ss22ssssssssssssss-Vss aa 22 bb 22 cc 22 22

Gate Arrays

● Fixed layers– Well– Diffusion– Polysilicon

● Programmed layers– Contact– Metal1– Via– Metal2

Gate Array Cell Site

** ** ** dd**ddaadd**ddbbdd***dccdd**dddddddddddddddddd-Vdd aa bb cc pppp--pppppp--pppppp--pppp **pp--pp**pp--pp**pp--pp** pppp--pppppp--pppppp--pppp aa bb cc aa bb cc aa bb cc ** ** ** ** ** ** aa bb cc nnnn--nnnnnn--nnnnnn--nnnn **nn--nn**nn--nn**nn--nn** nnnn--nnnnnn--nnnnnn--nnnn aa bb cc ss**ssaass**ssbbss**ssccss**ssssssssssssssssss-Vss ** ** **

Programmed Gate Array Cell

** ** ** dd**ddaadd**ddbbdd**ddccdd**dddddddddddddddddd-Vdd mm aa bb mm cc mmpp--pppppp--ppmmpp--pppp **pp--pp**pp--pp**pp--pp** pppp--pppppp--pppppp--ppmm aa mm bb cc mm aa mmmmbbmmmmmmccmmmm aa bb cc mm ** ** ** mm mm mm mm mm ** ** ** mm aa bb cc mm nnnn--nnnnnn--nnnnnn--nnmm **nn--nn**nn--nn**nn--nn** mmnn--nnnnnn--nnnnnn--nnnn mm aa bb cc ss**ssaass**ssbbss**ssccss**ssssssssssssssssss-Vss ** ** **

Gate Array Parameters

● For all chips:– Fixed number of transistors in each logic cell

● Fragmentation if need fewer in a logic cell● Can gang cells

– Fragmentation if need fewer than even multiple

– Fixed transistor size– Fixed number of tracks in routing channel

Sea of Gates

● Continuous row of nMOS across master chip● Continuous row of pMOS across master chip● Consume one transistor-pair site

to isolate logic gate from its neighbor– Tie pMOS transistor gate to V

DD

– Tie nMOS transistor gate to VSS

● Also called CMOS Cell Array

Sea of Gates Advantages

● Logic gate cells are variable in size– Consume transistor pair to isolate logic gate– No need to set as parameter for all chips

● Devote area to gates or routing as required– Route over unused transistors– No need to set as parameter for all chips

Sea of Gates Transistor Array

ddddddeeddddddaaddddddbbddddddccddddddffdddddd-Vdd ee aa bb cc ff pppppp--pppppp--pppppp--pppppp--pppppp--pppppppp**pp--pp**pp--pp**pp--pp**pp--pp**pp--pp**pppppppp--pppppp--pppppp--pppppp--pppppp--pppppp ee aa bb cc ff ee aa bb cc ff ee aa bb cc ff ** ** ** ** ** ** ** ** ** ** ee aa bb cc ff nnnnnn--nnnnnn--nnnnnn--nnnnnn--nnnnnn--nnnnnnnn**nn--nn**nn--nn**nn--nn**nn--nn**nn--nn**nnnnnnnn—-nnnnnn--nnnnnn--nnnnnn--nnnnnn--nnnnnn ee aa bb cc ff sssssseessssssaassssssbbssssssccssssssffssssss-Vss

Programmed Sea of Gates

dddddd**ddddddaaddddddbbddddddccdddddd**dddddd-Vdd ee dd aa bb dd cc ff pppppp--ppddpp--pppppp--ppddpp--pppppp--pppppppp**pp--pp**pp--pp**pp--pp**pp--pp**pp--pp**pppppppp--pppppp--ppmmpp--pppppp--pppppp--pppppp ee aa mm bb cc ff ee aa mmmmmmmmmmmmmmmmmm ff ee aa bb cc mm ff ** ** ** ** mm ** mm mm mm mm-Z ** ** ** ** mm ** ee aa bb cc mm ff nnnnnn--nnnnnn--nnnnnn--nnnnnn--nnmmnn--nnnnnnnn**nn--nn**nn--nn**nn--nn**nn--nn**nn--nn**nnnnnnnn--nnssnn--nnnnnn--nnnnnn--nnnnnn--nnnnnn ee ss aa bb cc ff ssssss**ssssssaassssssbbssssssccssssss**ssssss-Vss

Layout Rules of Thumb, Page 1

● Timing Rules of Thumb, cmpe222_05full_complement_ppt.ppg,pages 12 and 13

● Run VDD

in metal at top of cell

● Run VSS

in metal at bottom of cell

● Run gate input in polysilicon vertically for each transistor

Layout Rules of Thumb, Page 2

● Create diffusion segmentsby ordering transistors to maximizesource-drain connections by abutment

● Place pMOS segments close to VDD

● Place nMOS segments close to VSS

● Minimize internal node capacitance

Transistor-Level v. Gate-Level

● 10 – 100 transistor logic block● 25 – 75 % reduction in area● More source-drain connections by abutment● Less fragmentation● Labor intensive

–Reserve for frequently-occurring structures

●Standard cells●Datapath

Minimize Output Drain Capacitance

● If you have a choice to connectparallel transistors either to:

–output, or

–VDD

or VDD

● Choose source-drain connections by abutmentto connect to output

● Minimize output drain capacitance

–Faster gate● Maximize V

DD or V

DD capacitance

–Less noise

Success at Minimizing Nor Output Drain Capacitance

**dddddddddddddddddddddddddddddddddddddddddddd-Vdd dd **pp--pp**pp--pp** aa bb mm aa mmmmbbmmmmmm-Z aa mm bb **nn--nn**nn--nn** ss aa bb ss**ssssaassssssbbssssssssssssssssssssssssssssss-Vss aa bb A-aa B-bb

Failure at Minimizing Nor Output Drain Capacitance

**dddddddddddddddddddddddddddddddddddddddddddd-Vdd dd **pp--pp**pp--pp** aa bb mm mmmmaammmmmmbbmmmmmm-Z mm aa bb mm **nn--nn**nn--nn** aa ss bb **ssssaassssssbbssssssssssssssssssssssssssssss-Vss aa bb A-aa B-bb

Success at Minimizing Output Drain Capacitance

**dddddddddddddddddddddddddddddddddddddddddddd-Vdd dd dd **pp--pp**pp--pppppp--pppppp--pp** aa mm bb cc ee Z-mmmmaammmm bb cc ee mm aa bb cc ee mm aa mmmmbbmmmmmmccmmmm ee mm aa mm bb cc mm ee **nn--nn**nn--nn**nn--nn**nn--nn** aa bb ss cc ee ss aa bb ss cc ee ss aa bb ss cc ee ss**ssssaassssssbbssssssccsssssseessssssssssssss-Vss aa bb cc ee A-aa B-bb C-cc D-ee

Failure at Minimizing Output Drain Capacitance

**dddddddddddddddddddddddddddddddddddddddddddd-Vdd dd **pp--pp**pp--pppppp--pppppp--pp** mm aa bb cc ee mm mmmmaammmmmmbbmmmmmmccmmmmmmeemmmmmmmmmmmmmm-Z aa bb cc ee mm aa bb mmmmccmmmmmmeemmmm aa bb mm cc ee **nn--nn**nn--nn**nn--nn**nn--nn** ss aa mm bb cc mm ee ss aa mmmmbbmmmmmmccmmmm ee ss aa bb cc ee **ssssaassssssbbssssssccsssssseessssssssssssss-Vss aa bb cc ee A-aa B-bb C-cc D-ee

Pass Gate Layout

1.Minimal area• No horizontal metal pass-through

2.Allow horizontal metal pass-through• Larger area

3.Allow horizontal metal pass-through• Using metal2

Pass Gate Layout

aa **pp--pp** mm mm mm mm mm mm mm mm mm mm mm mm mm mm **nn--nn** bb

Pass Gate Layout w Metal Pass-Throughs

aa **mm**pp--pp**mm** cc eemmccmmmmmmmmmmmmmmeemm cc eemmccmmmmmmmmmmmmmmeemm cc eemmccmmmmmmmmmmmmmmeemm cc ee **mm**nn--nn**mm** bb

Pass Gate Layout w Pass-Thru Using Metal2

aa **pp--pp** mm mm ** ** 22 22mmmmmm22mmmmmm22mmmmmm 22 22 ** ** mm mm **nn--nn** bb

Route Select Signals to Array

1.Run horizontally in metal, outside transistors

2.Run vertically in polysilicon

3.Run vertically in polysilicon strapped by metal1

Pass Gate with Select Run Outside

mmmmmmmmmm**mmmmmmmmmm aa **pp--pp** mm mm mm mm mm mm mm mm mm mm mm mm mm mm **nn--nn** bbmmmmmmmmmm**mmmmmmmmmm

Pass Gate with Offset Transistors

aa bb **pp--pp**mmbbmmmm mm aa bb mm mm aa bb mm mm aa bb mm mm aa bb mm mm aa bb mm mm aa bb mm mm aa bb mm mmmm—mm**nn--nn** aa bb

Pass Gate with Poly-Metal1 Strap

** mm aa mm **pp--pp** mm mm aa mm mm ** mm ** mm 22 mm 22 mm 22 mm 2222222222 22 mm mm 22 22222222** mm ** mm mm bb mm mm **nn--nn** mm bb mm **

Multiplexer Select Lines

1.Select lines continuous

2.Select lines crossed inside

3.Select lines crossed outside

Multiplexer with Continuous Select Lines

mm mm ** ** ee ff **pp--pp**pp--pp** mm ee mm mm mmA-mmmm ee **22mm22mm22-Z mm ee mm mm mm mm eeeeeeeeee mmmm-B mm mm mm ee mm **nn--nn**nn--nn** ff mm ffffffff** mm mm C-mm -C-mm

Multiplexer with Crossed Select Lines

ff ee **pp--pp**pp--pp**mmmm mm ff mm ee mmA-mmmm ff mmmmeemmmm mm mm ff ee mm mm mm ffffff ee mm mmmm-B mm ff ee mm mm mm **mmmmmm** mm mm mm ee ff mm mm mm ee ffffff mm mm mm ee ff mm mm mm ee mmmmffmmmm mm mm ee mm ff mm **nn--nn**nn--nn**mmmm ee ff C-ee -C-ff

Multiplexer with Select Crossed Outside

ee ffffffffffffffffffee ff ffee **pp--pp**pp--pp** ffee mm mm ee mm ffeeeemmeeeeeemmeeee mm ffee mm mm mm ffee mm mm mm ffee mm mm mm ffee **nn--nn**nn--nn** ffee ee ff ffeeeeeeeeee ffffffffff ff ff C-ff -C-ff