visual state machine

7/31/2019 Visual State machine

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Prsentation afIAR visualSTATE

Lars Kornbek

[email protected]


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Agenda

Lidt historie samt firma prsentation

visualSTATE

Grundlggende visualSTATE opbygning Designeren og UML

Formel verifikation

Test / Validering samt prototyping

Kodegenerering og RealLink Dokumentation

Kunderne og deres applikationer

Nste visualSTATE release

Demo af visualSTATE


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Lidt historie samt firma

prsentation


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visualSTATE and IAR A/S History

1985 1987 1989 1991 1993 1995 1997 1999 2001

University

B&O R&D

B&O Technology

Beologic A/S

Baan

IAR

Today


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IAR Systems World wide

San Francisco

San Jos

Boston

Munich

London

Uppsala

Jonkoping

Aarhus

Tokyo

Sales

App. Dev. Services

R&D

App. Dev. Services

R&D

Sales Sales

App. Dev. Services

Sales

R&D


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VisionTo radically improve the software

development process for embedded

application development. We are creatingnew leading edge embedded solutions that

drastically shorten the entire development

process while still achieving more efficientresults.

FromFrom ideaidea toto targettarget !!


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visualSTATE

programming tool for Design, Prototyping, CodeGeneration, Test & Documentation


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Different ArchitecturesDifferent Architectures.. OneOne Solution.Solution.The IAR Solut ion is now available for more than 30 chip

architectures!

8-bit 16-bit

32-bit

Intel

Atmel

MotorolaNEC

National

Semiconductor

Hitachi

ToshibaZilog

Sharp

Samsung

Texas Instruments

OKI

ITT

Microchip Technologies

Mitsubishi

DSP

Embedded Workbenchdevelopment toolkit based on C/C++ compilers


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The IAR Embedded Workbench

A complete development suite for embedded development:

Project management functionality

Editors for source code and binary files

ANSI C & Embedded C++ compilers

Assembler

Linker & librarian

Debugger (Simulator, Emulator & ROM-monitor)


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IAR MakeAppautomatic code generators for device drivers


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BlueTooth

StarterKitMakeApp for BlueTooth

PreQual


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Other Products / Services

Consultant services

Project startup Project preview

project development

Training Product training

Technology training (C++, EC++, UML, BT, etc)

Technical Support Services

Application development Services


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Hvad er vigtigt for embeddede

systemer?


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Krav til embeddede systemer

Tidskrav

Eksekverings-tid / Real-time Deterministisk

Ressource forbrug / Kodestrrelse

RAM

ROM

Kvalitet / plidelighed


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Grundlggende visualSTATE

opbygning


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High-levelAnalysis &Design Tool

strictly formal

Analysis

Design

Verification

Coding

Integration

UMLSDL

SAInformal analysis

Incomplete design

Manual

coding

Trial & Error

Traditional Development IAR baseddevelopment

Typical CASE-tool baseddevelopment

Informalmethod

Manual

coding Manual coding

IARIAR

visualSTATE

MakeApp

Embedded

Workbench

From idea to target

FromDesign ToFinal Tested Code in anEasy Way


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IAR visualSTATE notations

State machines designed in IAR visualSTATE can be designed using two

notations :

S/E notation based on the Mealy notation

UML notation for Statecharts

Hierarchy

Concurrency

Memory in state machines

S1

S2

S3

E1 / A2A3

E1!S4/A2A3

E1 / A1

SE_RESET


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Hvad er en tilstandsmaskine ?

En maskine/system med en tilstands-orienteret dynamisk opfrsel

Et dynamisk system, der reagerer p pvirkninger afhngig af tid

og tilstand

Et tilstandsdiagram beskriver

Livs-forlbet af et system

Hvordan systemet reagerer p pvirkninger i alle situationer

Eksempler

Mobiltelefoner

Automater (kaffe, slik, cigaretter, Dankort, ...)

Operatr-paneler

Symaskiner

Reguleringer (varme, lys, fugtighed, ...)


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De centrale elementer i tilstandsmaskiner er :

Events

States

Actions

Events

Hndelser, der pvirker tilstandsmaskinen

Har i princippet ingen tidsmssig udstrkning

(forekommer momentant og asynkront)

States

Beskriver systemets tilstand mellem to events

Har tidsmssig udstrkning

Actions

Beskriver systemets pvirkning p omgivelserne

Har i princippet ingen tidsmssig udstrkning (udfres

momentant og uden afbrydelser)


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TraditionelTraditionel implementationimplementation af tilstandsmaskineraf tilstandsmaskiner

Manuel kodning med switch-case

Manuel kodning med tabeller

Manuel kodning med tilstandsklasser

Arv og polymorfe operationer (C++/Java)

switch ( current_state ) {

case ALARM :

if ( event == ALARM_KVITTERING ) {

StopAlarm();

current_state = INGEN_ALARM;

}

break;

case ...

:

}

Hvordan hndterer viHvordan hndterer vihierarki,hierarki,

concurrencyconcurrency

ogog

synkroniseringersynkroniseringerved manuel kodningved manuel kodning

??


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Rule notation

CSV = current state vector

NSV = next state vector

AV = action vector

Each state machine is always in one and only one

state

State changes (transitions) are triggered by one and

only one event

event CSV : NSV AV


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visualSTATE

Fundamentals

visualSTATEenigne

Device Driver

convert inputsto events

Real Life

x=port(0); port(1) = 1;

Real Life

Device Driver

convert actionsto outputs

Events Action functions

Event Queue


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Mathematical proof of correct code through binary arrayswith unique interpretation

Kernel functionality verified in millions of applications

since 1987

Modeling

Well definedset of mathematical

operations

Run-time

Technological concept

State analysis

Patented

Patented


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Hvad kan visualSTATE?

Fejl hvis Event1 og state1 og state2

A

C

B

D

Event1() /

Event2() /

Event5() /

Event6() /Event3() /

Event4() /

Design vha.grafisk

programmering

Prototype pbaggrund af

designA

C

B

D

Event1() /

Event2() /

Event5() /


Event4() /

Event1Event3Event7Event4

...

Manuel

test

Automatisktest

Kodegenerering Dokumentation

A

C

B

D

Event1() /

Event2() /

Event5() /


Event4() /

{if (SEM.CSV [4] == 0x05)SEM.WSV [3] = 0x0F;

....

}

A

C

B

D

Event1() /

Event2() /

Event5() /


Event4() /

This TV set has been

developed for a

Motorola platform...


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Designer / UML


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Hvad er UML

UML, Unified Modeling Language

UML er en metode / notation der prver at samlenogle af de forskellige objekt orienterede

metoder.

OMG godkendte UML som standard i 1997.

3 modeller

Kravmodeller (USE-case diagram og sekvensdiagram)

Strukturer (klassediagrammer)

Opfrsel (tilstandsdiagrammer)


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Hvorfor UML

Veldefineret objekt model

Uafhngig af implementerings sprog Mulighed for genbrug

Samme platform uafhngig af type applikation

Bred vifte af vrktjer

Bred vifte af litteratur, trning og

konsulentydelser Efterhnden udbredt p undervisnings

institutioner


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Designing a stereo...

Either the tape recorder orthe radio orthe CD

player is active...


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Events are added...

Transition

Event


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A new hierarchical level is introduced

Substate

Super

state

The states STOPPED, PLAYING and RECORDING

are only active when state TAPE is active


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Concurrency is introduced

State PLAYING orstate STOPPED

and

state CD orstate NO_CD are active

Composite

state

Concurrent

substate


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Actions are added

Action


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Entry and Exit actions

Entry action

Exit action

Entry actions are activated each time a state in entered

Exit actions are activated each time a state is left


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Initial statesInitial

state

Initial states are used to initialize the statecharts and as default

states in superstates


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History states

Historystate

History states are used to apply memory to the statecharts


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Variables

Variable


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Signals

Signal

Signals can be used to send a message to another state

machine


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Internal transitions

Internal

transition

An internal transition does not cause any state change


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InIn thethe realreal worldworld......

Events could be interrupts, a button press,

timeouts, reset...

States represents whatever the product is doing

right now...

Actions could control valves, displays, a CAN

bus...

Variables could be used to representtemperatures, counters, flags...

Summary - UML and visualSTATE Rules :


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Each state machine is always in one and

only one state

State changes (transitions) are triggeredby one and only one

event / event group / signal

Upon receipt of a trigger, all statecombinations are frozen until all

transitions have been handled,and all variables are double buffered (if

necessary)

Summary UML and visualSTATE, Rules :

S UML d i lSTATE T iti


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Summary - UML and visualSTATE, Transition :

A B

EV(p) S1 [(x < 7) || (y > 10)]

[z = MAX] A2(x, y) S4 ^SIG

/

Condition side

Action side

Trigger State

condition

Guard

expression

Assignment Action

function

Forcestate

Signal


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Design / metodeDesign / metodeDe 6 trin :

1. Identificr events og actions

2. Identificr states

3. Gruppr efter hierarki

4. Gruppr efter concurrency

5. Tilfj transitioner

6. Tilfj synkroniseringer


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Trin 1 : Identificr events og actions

Events er omgivelsernes pvirkning p

systemet

= input til tilstandsmaskinen

Events er eksterne hndelser

Signalerer interne hndelser frasystemet selv

Actions er systemets pvirkning p

omgivelserne= output fra tilstandsmaskinen

Actions er systemets reaktion p de

eksterne pvirkninger

T i 2 Id ifi


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Trin 2 : Identificr states

States identificeres udfra kravspecifikation samtviden om problem-domnet.

Dren kan vre ben eller lukket

Dren kan vre lst eller ulst

Switchen kan vre i en af de tre positioner

Lyset kan tndt eller slukket

T i 3 G ft hi ki


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Trin 3 : Gruppr efter hierarki

Undersg hvilke states, der i sig selv har dynamisk

opfrsel, samt om visse tilstande kun vil optrde i

bestemte situationer

Med denne gruppering modelleres, at dren ikke kan

vre ben eller lukket, nr den er lst.

Modellen indkapsler muligheden for at bne en dr

kun muligt, nr dren er ulst

T i 4 G ft


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Trin 4 : Gruppr efter concurrency

Undersg hvilke tilstande, der kan vre aktive p samme tid

Opdel i flere parallelle aktive tilstandsmaskiner

Det skal vre muligt at bne, lukke og lse dren

samtidigt med at switchen ndres og

samtidigt med at lyset skifter

Trin 5 : Tilfj transitioner


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Trin 5 : Tilfj transitioner

Identificr hvilke tilstandsskift og udfrelse af actions, der skal foreg, nr events forekommer

Beskriv scenarier (sekvenser af pvirkninger) og tilfj transitioner, der understtter disse

Bemrk, at der er indfrt yderligere hierarki

af design hensyn

n transition til hver switch-position

Trin 6 : Tilfj synkroniseringer


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Trin 6 : Tilfj synkroniseringer

Identificr hvilke transitioner, der er betingede og tilfj evt. yderligere transitioner

Identificr hvilke transitioner, der har brug for at sende interne beskeder

Nr dren bnes mens switchen er i sensitive,

s skal lyset tndes....

.... etc.


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IAR visualSTATE Designer

Graphical overview

of system behavior

Hierarchical state

systems Multiple and inter-

related state

machines

Parallel threads ofcontrol

UML Statecharts

State Transition

Diagrams


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Formel verifikation

IAR visualSTATE Testing


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Interrelationships

between state-machines arechecked

All combinations

are checked

S11

S13

S12

KEY1

KEY1

S14

KEY2[S21 && S22]

S21

S22


Dynamic Formal Verification

KEY3

ConflictingTransition

Dead end

UnreachableTransition

Verificator settings


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Verificator settings

Exhaustive computation

7 different checks

Use of elements

Reachable transitions

Conflicting transitions

Activation of elements

State dead end Local dead end

System dead end

Forward / Backward mode

Backward = no dead-end check


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Test / Validering samtprototyping

IAR i lSTATE T ti


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Simulation

Sending events

Monitoring

Current States

Active events Guards

Triggered actions

Timers

Variables

Signals

AA AB

AD AC

E1() /

E2() /

E3() /

E4() /E3() /


Manual validation



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Record test sequences Static analysis, use of

Events

Actions

Signals Internal & External-

variables

Dynamic analysis

Test coverage analysis

Non-activated elements

Most frequently used


Log & Animation


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Prototyping

Why prototyping


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You can build a model that looks and behave likeyour final product

You can get feedback from marketing, sales and

customers and therefore make corrections in amuch earlier state in your development process

and therefore save money.

It will help you increase the awareness andknowledge of your product before it is launched

With visualSTATE your final product will

behave in a way 100% identical to that of your

prototype.

y p yp g


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Prototyping with Altia FacePlate

Altia integration to visualSTATE


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g

Other Prototype possibilities


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y

Visual C / C++

App note 10743: Prototyping in Visual C++ with IARvisualSTATE

Borland C++ builder

IAR DK can provide you with an example. Visual Basic

App note 45079: Prototyping in Visual Basic with

visualSTATE expert DLL.

Delphi

App note 45079: Prototyping in Visual Basic with

visualSTATE expert DLL.


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Kodegenerering og RealLink

IAR visualSTATE Code generation


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IAR visualSTATE Code generation

Features Automatic Code Generation based on the design

Generation of very compact code for 8/16/32-bitmicroprocessors

integrates with any ANSI-C Compiler

Integrates with any RTOS

Advantages SW-consistency between design and actual code

is guaranteed

Avoid manual coding, spaghetti coding and

reverse engineering

Flexible realization in any target


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Design + Test+ Prototyping

Automaticcode-generation

Real-Link Hardware

^ RTOSDevice Drivers

v

API*

Application CompleteTargetA

pplication

8-/16-/32-bit*) Foot print: 600 bytes to 2K

Model

Connectivity via Real-Link


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Host

Wire

Target

*) Foot print: ~1K (RS232 interface)

Real-Link Agent*Real-Link Server

TCP/IP Direct

Validator

Application

Model


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Documentation

IAR visualSTATE Documentation


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Features Automatic generation of

design/test/code

documentation

Customized generation of

documents

Advantages 100% consistent with current

implementation

Customized

documentation/manual

Up-to-date documentation

Our customers


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One genericOne generic

productproduct

for a varietyfor a variety

of industriesof industries

Automotive

Telecom

Medical

Electronics

Aerospace & Defense

Financial

Industrial machinery

Industrial instruments

Consulting & Education

Multimedia & Entertainment

Case Stories


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Husqvarna Viking, MMI for sewing machine

Grundfos Group, Pumps Bang & Olufsen, TV, video and stereo

Danfoss A/S, MMI for flow meters

P.I.V. Eldutronik, frequency controller

Spark Holland, laboratory equipment

Wittenborg A/S, Vending machines

http://www.iar.com/Products/vS/References

Other Customers


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Canon Inc.

LG Electronics

Digianswer A/S

DE-VI A/S

DEIF A/S

Migatronic A/S

FBI laboratory

KONE Corporation

Lego Systems A/S

Novo Nordisk A/S

Scanvgt International A/S

Siemens Elema AB

Siemens AG

Terma Elektronic A/S

Next visualSTATE release


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Hierarchical Coder

C++ wrapper

Verification of guard and assignments

Trace generation w/ Validator integration

New UML modeling constructs

Team work (+VCS)

New Navigator

Graphical breakpoints and transitions

General bug fixing, performance and stabilityimprovements

Future: More UML support ???

Questions


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visual state machine

Documents