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Virtual Prototyping
Alexander Fasching
Vienna University of TechnologyMatr. Nr.: 1225900
Email: [email protected]
HW/SW Codesign WS 2016/17
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Overview
What is Virtual Prototyping?
Why are they used?
Advantages compared to physical prototypes
Abstraction levels
Determinism and system state
Tools, limits and requirements
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What is virtual prototyping?
A virtual prototype is an executable software model of ahardware system that runs on a host computer.
Possible constraints on the definition:
Binary compatible to physical hardware (instruction set,memory map, registers)
Runs the full software stack, from boot-code to operatingsystem and application
Provides the same debugging utilities as the physical hardware(debugger, profiler, . . . )
Ideally, testcases for functional verification can be executed onthe virtual and the physical prototype.
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Why the effort?
Usual development cycle:
12-15 months hardware development
9-12 months software development
6-9 months system integration, verification and validation
Grand total of 36 months
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Why the effort?
Usual development cycle:
12-15 months hardware development
9-12 months software development
6-9 months system integration, verification and validation
Grand total of 36 months
Desired product window usually 24 months or less
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The solution
Develop HW and SWin parallel
Verified softwarereduces integrationtime
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Advantages to physical prototypes
Shifts the start of software development ”left”: Developmentcan start well before a physical prototype is available, evenbefore RTL design is finished.
Deterministic (e.g. simulate user input)
Additional debugging and monitoring capabilities (faultinjection, tracing, profiling)
Verified firmware available before physical prototype reduceshardware bringup time
Test special conditions without damaging hardware(short/open connections, memory corruption)
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Abstraction
Tradeoff between accurracy and simulation speed
Consistency between VP and hardware
Using formal specification as golden reference
Proving equivalency of specification, VP and hardware
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RTL Simulation
Cycle-accurate
Bit-exact
Speed: 1/100000 realtime
Interactive debugging possible, but very slow and not widelysupported
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TLM - Instruction set of target
Firmware executed through instruction-set-simulator (ISS)
Bit-exact
Cycle-approximate
Speed: 1/100 realtime
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Source-level/host-compiled simulation
Firmware and processor modelexecuted as native binary onhost
Timing approximation throughstatic analysis of source codeand binary
Original source code annotatedwith delays
Speed: ≈ realtime
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Source-level simulation stack
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(Non)Determinism and system state
Clock A and Basynchronous
Timing betweencommands on Debug Aand B unknown
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(Non)Determinism and system state
Subsystem B can’t bestopped (might beanalog)
Timeouts might occur
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(Non)Determinism and system state
Full control over clocks
Synchronous debugcommands to allsubsystems
Global time
Global event ordering
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Generic test-environment
Same testsuite for physicaland virtual prototype
Abstraction layer fordebugging tools andtestsuite
Interface to signalgenerators, digital I/O andmeasurement equipment,both physical and virtual
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Drawbacks and limits
Changes in development flow
Additional costs
ToolsDevelopersComputational resources
Incompatible interfaces between different tools
High effort to integrate models of different vendors
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Available tools
Free
SystemCQemu (allows the creation of virtual devices)Android SDK
Commercial
Matlab/Simulink for high level modelsSynopsys: Virtualizer (ARM, Automotive and ARC HS38)Mentor: Vista Virtual Prototyping (ARM)Cadence: Virtual System Platform
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