A .GII THIU V VI IU KHIN 89S521. Tng quan v 89S52AT89S52 l h IC vi iu khin do hng Atmel sn xut. Cc sn phm AT89S52 thch hp cho nhng ng dng iu khin. Vic x l trn byte v cc ton s hc cu trc d liu nh c thc hin bng nhiu ch truy xut d liu nhanh trn RAM ni. Tp lnh cung cp mt bng tin dng ca nhng lnh s hc 8 bit gm c lnh nhn v lnh chia. N cung cp nhng h tr m rng trn chip dng cho nhng bin mt bit nh l kiu d liu ring bit cho php qun l v kim tra bit trc tip trong h thng iu khin. AT89S52 cung cp nhng c tnh chun nh: 8 KByte b nh ch c c th xa v lp trnh nhanh (EPROM), 128 Byte RAM, 32 ng I/O, 3 TIMER/COUNTER 16 Bit, 5 vect ngt c cu trc 2 mc ngt, mt Port ni tip bn song cng, 1 mch dao ng to xung Clock v b dao ng ON-CHIP. Cc c im ca chip AT89S52 c tm tt nh sau: 8 KByte b nh c th lp trnh nhanh, c kh nng ti 1000 chu k ghi/xo Tn s hot ng t: 0Hz n 24 MHz 3 mc kha b nh lp trnh 3 b Timer/counter 16 Bit 128 Byte RAM ni. 4 Port xut /nhp I/O 8 bit. Giao tip ni tip. 64 KB vng nh m ngoi 64 KB vng nh d liu ngoi.

4 s cho hot ng nhn hoc chia

S khi ca AT89S52

2. M t chn 89S522.1. S chn 89S52 Mc d cc thnh vin ca h d 8751, 89S52, 89C51, DS5000) u c cc kiu ng v khc nhau, chng Line Pakage), dng v dt vung QPF (Quad Flat Pakage) v dng chip khng c chn LLC (Leadless Chip Carrier) th chng u c 40 chn cho cc chc nng khc nhau nh vo ra I/O, c RD , ghi WR , a ch, d liu v ngt. Cn phi lu mt hng cung cp mt phin bn 8051 c 20 chn s vi s cng hn nh hai hng chn DIP (Dual In8051(v

vo ra t hn cho cc ng dng yu cu thp hn. Tuy nhin v hu ht cc nh pht trin s dng chp ng v 40 chn vi hai hng chn DIP nn ta ch tp trung m t phin bn ny. 2.2. Chc nng ca cc chn 89S52 Port 0: t chn 32 n chn 39 (P0.0 _P0.7). Port 0 c 2 chc nng: trong cc thit k c nh khng dng b nh m rng n c chc nng nh cc ng IO, i vi thit k ln c b nh m rng n c kt hp gia bus a ch v bus d liu. Port 1: t chn 1 n chn 9 (P1.0 _ P1.7). Port 1 l port IO dng cho giao tip vi thit b bn ngoi nu cn. Port 2: t chn 21 n chn 28 (P2.0 _P2.7). Port 2 l mt port c tc dng kp dng nh cc ng xut/nhp hoc l byte cao ca bus a ch i vi cc thit b dng b nh m rng. Port 3: t chn 10 n chn 17 (P3.0 _ P3.7). Port 3 l port c tc dng kp. Cc chn ca port ny c nhiu chc nng, c cng dng chuyn i c lin h n cc c tnh c bit ca 89S52 nh bng sau:

AT89S52

Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

Tn RXD TXD INT0 INT1 T0 T1 WR RD

Chc nng chuyn i Ng vo d liu ni tip. Ng xut d liu ni tip. Ng vo ngt cng th 0. Ng vo ngt cng th 1. Ng vo TIMER/ COUNTER th 0. Ng vo ca TIMER/ COUNTER th 1. Tn hiu ghi d liu ln b nh ngoi. Tn hiu c b nh d liu ngoi.

PSEN (Program store enable): PSEN l tn hiu ng ra c tc dng cho php c b nh chng trnh m rng v thng c ni n chn OE ca Eprom cho php c cc byte m lnh. PSEN mc thp trong thi gian 89S52 ly lnh. Cc m lnh ca chng trnh c c t Eprom qua bus d liu, c cht vo thanh ghi lnh bn trong 89S52 gii m lnh. Khi 89S52 thi hnh chng trnh trong ROM ni, PSEN mc cao. ALE (Address Latch Enable): Khi 89S52 truy xut b nh bn ngoi, Port 0 c chc nng l bus a ch v d liu do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30 dng lm tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni chng vi IC cht. Tn hiu chn ALE l mt xung trong khong thi gian port 0 ng vai tr l a ch thp nn cht a ch hon ton t ng.

EA (External Access): Tn hiu vo EA (chn 31) thng c mc ln mc 1 hoc mc 0. Nu mc 1, 89S52 thi hnh chng trnh t ROM ni. Nu mc 0, 89S52 thi hnh chng trnh t b nh m rng. Chn EA c ly lm chn cp ngun 21V khi lp trnh cho Eprom trong 89S52. RST (Reset): Khi ng vo tn hiu ny a ln mc cao t nht 2 chu k my, cc thanh ghi bn trong c np nhng gi tr thch hp khi ng h thng. Khi cp in mch phi t ng reset. Cc gi tr t v in tr c chn l: R1=10, R2=220, C=10 F. Cc ng vo b dao ng X1, X2: B to dao ng c tch hp bn trong Khi s dng 89S52, ngi ta ch cn ni thm anh v cc t. Tn s thch anh ty thuc vo ch ca ngi s dng, gi tr t thng chn l 33p. 89S52. thch mc c

3. T chc b nh bn trong 89S52B nh trong 89S52 bao gm ROM v RAM. RAM trong 89S52 bao gm nhiu thnh phn: phn lu tr a dng, phn lu tr a ch ha tng bit, cc bank thanh ghi v cc thanh ghi chc nng c bit. AT89S52 c b nh c t chc theo cu trc Harvard: c nhng vng b nh ring bit cho chng trnh v d liu. Chng trnh v d liu c th cha bn trong 89S52 nhng 89S52 vn c th kt ni vi 64K byte b nh chng trnh v 64K byte d liu bn ngoi.

a ch byte

Bn b nh Data bn trong a ch 89S52 c t chc nh sau: Chipa ch bitbyte

a ch bit

RAM bn trong AT89S52 c phn chia nh sau:

Cc bank thanh ghi c a ch t 00H n 1FH. RAM a ch ha tng bit c a ch t 20H n 2FH. RAM a dng t 30H n 7FH. Cc thanh ghi chc nng c bit t 80H n FFH 3.1. RAM a dng RAM a dng c a ch t 30h 7Fh c th truy xut mi ln 8 bit bng cch dng ch nh a ch trc tip hay gin tip. Cc vng a ch thp t 00h 2Fh cng c th s dng cho mc ch nh trn, ngoi cc chc nng c bit c cp phn sau. 3.2. RAM c th nh a ch bit Vng a ch t 20h -2Fh gm 16 byte c th thc hin nh vng RAM a dng (truy xut mi ln 8 bit) hay thc hin truy xut mi ln 1 bit bng cc lnh x l bit. 3.3. Cc bank thanh ghi Vng a ch 00h 1Fh c chia thnh 4 bank thanh ghi: bank 0 t 00h 07h, bank 1 t 08h 0Fh, bank 2 t 10h 17h v bank 3 t 18h 1Fh. Cc bank thanh ghi ny c i din bng cc thanh ghi t R0 n R7. Sau khi khi ng th h thng bank 0 c chn s dng. Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c truy xut bi cc thanh ghi R0 n R7. Vic thay i bank thanh ghi c thc hin thng qua thanh ghi t trng thi chng trnh (PSW). 3.4. Cc thanh ghi c chc nng c bit Cc thanh ghi trong 89S52 c nh dng nh mt phn ca RAM trn chip v vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v thanh ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh R0 n R7, 89S52 c 21 thanh ghi c chc nng c bit (SFR: Special Function Register) vng trn ca RAM ni t a ch 80H n 0FFH.

Sau y l mt vi thanh ghi c bit thng c s dng: 3.4.1. Thanh ghi trng thi chng trnh (PSW: Program Status Word) BIT PSW.7 PSW.6 PSW.5 PSW4 PSW.3 SYMBOL CY AC F0 RS1 RS0 ADDRESS D7H D6H D5H D4H D3H Cary Flag Auxiliary Cary Flag Flag 0 Register Bank Select 1 Register Bank Select 0 00=Bank 0; address 00H 07H 01=Bank 1; address 08H 0FH 10=Bank 2; address 10H 17H 11=Bank 3; address 18H 1FH PSW.2 PSW.1 PSW.0 OV P D2H D1H DOH Overlow Flag Reserved Even Parity Flag DESCRIPTION

Chc nng tng bit trng thi chng trnh - C Carry CY (Carry Flag):C nh thng n c dng cho cc lnh ton hc: C =1 nu php ton cng c s trn hoc php tr c mn v ngc li C = 0 nu php ton cng khng trn v php tr khng c mn. - C Carry ph AC (Auxiliary Carry Flag): Khi cng nhng gi tr BCD

(Binary Code Decimal), c nh ph AC c set nu kt qu 4 bit thp nm trong phm vi iu khin 0AH - 0FH. Ngc li AC = 0 - C 0 (Flag 0): C 0 (F0) l 1 bit c a dng dng cho cc ng dng ca ngi dng. - Nhng bit chn bank thanh ghi truy xut: RS1 v RS0 quyt nh dy thanh ghi tch cc. Chng c xa sau khi reset h thng v c thay i bi phn mm khi cn thit.

Ty theo RS1, RS0 = 00, 01, 10, 11 s c chn Bank tch cc tng ng l Bank 0, Bank1, Bank2 v Bank3.

RS1 0 0 1 1

RS0 0 1 0 1

BANK 0 1 2 3

- C trn OV (Over Flag): C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc. - Bit Parity (P): Bit t ng c set hay Clear mi chu k my lp Parity chn vi thanh ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn. V d A cha 10101101B th bit P set ln mt tng s bit 1 trong A v P to thnh s chn. Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu.

3.4.2. Thanh ghi TIMER Vi iu Khin 89S52 c 3 timer 16 bit, mi timer c bn cch lm vic. Ngi ta s dng cc timer : o nh khong thi gian.o

m s kin.

o To tc baud cho port ni tip trong 89S52.

Trong cc ng dng nh khong thi gian, ngi ta lp trnh timer nhng khong u n v t c trn timer. C c dng ng b ha chng trnh thc hin mt tc ng nh kim tra trng thi ca cc ng vo hoc gi s kin ra cc ng ra. Cc ng dng khc c th s dng vic to xung nhp u n ca timer o thi gian tri qua gia hai s kin (v d o rng xung). 3.4.3. Thanh ghi ngt (INTERRUPT) Mt ngt l s xy ra mt iu kin, mt s kin m n gy ra treo tm thi thi chng trnh chnh trong khi iu kin c phc v bi mt chng trnh khc. Cc ngt ng mt vai tr quan trng trong thit k v ci t cc ng dng vi iu khin. Chng cho php h thng p ng bt ng b vi mt s kin v gii quyt s kin trong khi mt chng trnh khc ang thc thi. - T chc ngt ca 89S52: C 5 ngun ngt 89S52: 2 ngt ngoi, 2 ngt t timer v 1 ngt port ni tip. Tt c cc ngt theo mc nhin u b cm sau khi reset h thng v c cho php tng ci mt bng phn mm. Mc u tin ca cc ngt c lu trong thanh ghi IP (Interrupt Priority) hay ni cch khc thanh ghi IP cho php chn mc u tin cho cc ngt (gi tr thanh ghi IP khi reset l 00h).

Bit IP.7 IP.6 IP.5

K hiu _ _ ET2

a ch bit _ _ BDH

M t Khng c m t Khng c m t Chn mc u tin cao (=1) hay thp (=0) ti timer 2

IP.4

ES

BCH

Chn mc u tin cao (=1) hay thp (=0) ti cng ni tip.

IP.3

ET1

BBH

Chn mc u tin cao (=1) hay thp (=0) ti timer 1

IP.2

EX1

BAH

Chn mc u tin cao (=1) hay thp (=0) ti ngt ngoi 1

IP.1

ET0

B9H

Chn mc u tin cao (=1) hay thp (=0) ti timer 0

IP.0

EX0

B8H

Chn mc u tin cao (=1) hay thp (=0) ti ngt ngoi 0 Tm tt thanh ghi IP

Nu 2 ngt xy ra ng thi th ngt no c no c mc u tin cao hn s c phc v trc. Nu 2 ngt xy ra ng thi c cng mc u tin th th t u tin c thc hin t cao n thp nh sau: ngt ngoi 0 timer 0 ngt ngoi 1 timer 1 cng ni tip timer 2. Nu chng trnh ca mt ngt c mc u tin thp ang chy m c mt ngt xy ra vi mc u tin cao hn th chng trnh ny tm dng chy mt chng trnh khc c mc u tin cao hn.

- Cho php v cm ngt: Mi ngun ngt c cho php hoc cm ngt qua mt thanh ghi chc nng t bit c nh a ch bit IE (Interrupt Enable: cho php ngt) a ch A8H.

Bit IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

K hiu EA _ ET2 ES ET1 EX1 ET0 EX0

a ch bit AFH AEH ADH ACH ABH AAH A9H A8H

M t Cho php / Cm ton b Khng c m t Cho php ngt t Timer 2 (8052) Cho php ngt port ni tip Cho php ngt t Timer 1 Cho php ngt ngoi 1 Cho php ngt t Timer 0 Cho php ngt ngoi 0

Tm tt thanh ghi IE - Cc c ngt: Khi iu kin ngt xy ra th ng vi tng loi ngt m loi c c t ln mc cao xc nhn ngt.

Ngt Bn ngoi 0 Bn ngoi 1 Timer 1 Timer 0 Port ni tip Port ni tip

C IE0 IE1 TF1 TF0 TI RI

Thanh ghi SFR v v tr bit TCON.1 TCON.3 TCON.7 TCON.5 SCON.1 SCON.0

Cc loi c ngt - Cc vect ngt: Khi chp nhn ngt, gi tr c np vo PC gi l vector ngt. N l a ch bt u ca ISR cho ngun to ngt, cc vector ngt c cho bng sau : Ngt Reset h thng Bn ngoi 0 Timer 0 Bn ngoi 1 Timer 1 Port ni tip Timer 2 IE0 TF0 IE1 TF1 TI v RI 0003H 000BH 0013H 001BH 0023H 002BH C RST a ch vector 0000H

Vector reset h thng (RST a ch 0000H) c trong bng ny v theo ngha ny, n ging ngt: n ngt chng trnh chnh v np cho PC gi tr mi.

B. IC ghi dch 74HC595 .Hnh dng thc t:

1, Chc nng : L ic ghi dch 8bit kt hp cht d liu , u vo ni tip u ra song song . Chc nng: Thng dng trong cc mch qut led 7 , led matrix tit kim s chn VDK ti a (3 chn) . C th m rng s chn vi iu khin bao nhiu ty thch bng vic mc ni tip u vo d liu cc ic vi nhau . 2,S chn: Gii thch ngha hot ng ca mt s chn quan trng: Chn 14 : u vo d liu ni tip . Ti 1 thi im xung clock ch a vo c 1 bit QA=>QH : trn cc chn (15,1,2,3,4,5,6,7)

Xut d liu khi chn chn 13 tch cc mc thp v c mt xung tch cc sn m ti chn cht 12 Chn 13 : Chn cho php tch cc mc thp (0) .Khi mc cao, tt c cc u ra ca 74595 tr v trng thi cao tr, khng c u ra no c cho php. Chn 9: Chn d liu ni tip . Nu dng nhiu 74595 mc ni tip nhau th chn ny a vo u vo ca con tip theo khi dch 8bit. Chn 11: Chn vo xung clock . Khi c 1 xung clock tch cc sn dng(t 0 ln 1) th 1bit c dch vo ic. Chn 12 : xung clock cht d liu . Khi c 1 xung clock tch cc sn dng th cho php xut d liu trn cc chn output . lu c th xut d liu bt k lc no bn mun ,v d u vo chn 14 dc 2 bit khi c xung clock chn 12 th d liu s ra chn Qa v Qb (ch chiu dch d liu t Qa=>Qh) Chn 10: khi chn ny mc thp(mc 0) th d liu s b xa trn chip) S hot ng ca chp :

3, Bng thng s chip:

y l ic u ra hot ng 2 mc 0 &1 dng ra tm 35mA . in p hot ng ') void}HienThi(unsigned char speed) 0xFF, 0xC7, 0xBB, 0xBB, 0xB7, 0x80,//d {{ } 0xFF, 0xC7, 0xAB, 0xAB, 0xAB, 0xE7,//e unsigned char m,k,t,n; void delay(unsigned SBUF; data_pc[count_data] = int x) //--------------------------------------------------for (origin=0;origin2)colour=0; = point%6; // byte con lai 0xFF, 0x83, 0xF7, 0xFB, 0xFB, 0x87,//n if (bien24=8 0xC7, 0xBB, 0xBB, 0xBB, 0xC7,//o 0xFF, & bien24=16 & bien24