[laptrinh.vn]-vi điều khiển dspic30f4011

H Cng Ngh - HQG H Ni

Kha Lun Tt Nghip

Tm ttBn kha lun tt nghip gm c ba phn ring bit trong phn mt l l thuyt b khuych i lock-in tip theo l tng quan chung cu trc vi iu khin dsPic30F4011 v cui cng l phn thc nghim. Chng 1 v l thuyt b khuych i lock-in trc tin ta s tm hiu ti sao li phi dng b khuych i lock-in trong o lng tn hiu nh v khi nim b khuych lock-in, tip theo l s cu to chung ca mt b khuych i lock-in c in. Cui cng l phn tm hiu cu to v nguyn tc hot ng ca b khuych i lock-in s v tng t. Trong chng 2 v tng quan cu trc ca vi iu khin dsPic30F4011 chng ta s tm hiu chung v h vi iu khin DsPic30F tip l c im chung ca h vi iu khin dsPic30F4011. Cui cng ta s tm hiu su hn v cu trc ca vi iu khin dsPic30F4011. Phn cn li ca bn kha lun s l phn thc nghim, y trnh by ton b qu trnh thit k b khuych i lock-in gm c phn cng, phn mm v kt qu thc nghim. Phn cng c cc khi ring bit, vi mi khi c trnh by l thuyt v c s thit k. Cn phn mm c trnh by di dng s khi ca cu trc chng trnh vi cc modul ring bit. Sau khi thit k c b khuych i lock-in s, ta s th nghim mt h o cho cm bin c nhn l b khuych i lockin va ch to. C th trong bn kha lun s th nghim mt h o p dng cho cm bin p sut MPX2300D do cng ty Motorola cung cp.

Sinh Vin : L Trn Triu Tun


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MC LCM u.............................................................................................................................1 Chng 1. B Khuch i Lock In................................................................................21.1. TNG QUAN V B KHUYCH I LOCK IN...................................................................................................................2 1.1.1. Gii thiu....................................................................................................................................................2 1.1.2. Khi nim lock in amplifier....................................................................................................................6 1.1.3. Cu trc chung ca b khuych i lock in................................................................................................6 1.2. B KHUYCH I LOCK IN TNG T (ANALOG LOCK-IN AMPLIFIERS)..........................................................................7 1.3. B KHUYCH I LOCK IN S (DIGITAL LOCK-IN AMPLIFIERS).....................................................................................9

Chng 2. Vi iu Khin DsPic30F4011.....................................................................111 2.1. GII THIU CHUNG V H VI IU KHIN DSPIC........................................................................................................11 2 2.2. C IM CHUNG CA VI IU KHIN DSPIC30F4011..............................................................................................11 2.2.1. Khi x l trung tm CPU........................................................................................................................11 2.2.2. B chuyn i tng t s ADC...............................................................................................................12 2.2.3. Cc cng vo ra I/O Port v cc ngoi vi ..............................................................................................12 2.2.4. B x l tn hiu s....................................................................................................................................12 2.2.5. Mt s c im khc................................................................................................................................13 3 2.3. CU TRC CA VI IU KHIN DSPIC30F4011........................................................................................................13 2.3.1. Khi x l trung tm CPU........................................................................................................................13 2.3.2. Khi to a ch AGU................................................................................................................................172.3.2.1. Ch a ch lnh............................................................................................................................................17 2.3.2.2. Ch o bit a ch........................................................................................................................................19

2.3.3. T chc b nh v b nh chng trnh...................................................................................................202.3.3.1. Khng gian a ch chng trnh........................................................................................................................20 2.3.3.2. Truy xut d liu t b nh chng trnh s dng cc lnh bng......................................................................21 2.3.3.3. Truy xut d liu t b nh chng trnh s dng khng gian chng trnh...................................................21

2.3.4. Cc cng vo ra I/O Port.........................................................................................................................23 2.3.5. Ngt v c ch ngt...................................................................................................................................25 2.3.6. Cc b nh thi........................................................................................................................................27 Trong vi x l dsPIC40F4011 c ti nm b nh thi (Timer) 16-bit. Trong cc Timer c th hot ng ring bit, ring hai Timer 2, 3 v hai Timer 4, 5 c th kt hp vi nhau tr thnh mt Timer 32 bit.........27 Xung nhp u vo (Fosc/4 hoc xung nhp ngoi) a vo Timer 16-bit v c th c chia tn s theo cc t l sau: 1:1, 1:8, 1:64, 1:256 c xc nh bi cc bit TCKPS ca thanh ghi TxCON. H s chia tn ny (prescaler) c th b xo khi xy ra mt trong cc iu kin sau:................................................................27 2.3.7. B chuyn i tng t s ADC...............................................................................................................302.3.7.1. B m kt qu bin i A/D.............................................................................................................................30

Module ADC s dng RAM lm b m lu kt qu bin i A/D. C tt c 16 v tr trong RAM c s dng lm vic ny, l: ADCBUF0, ADCBUF1, ADCBUF2, ..., ADCBUFE, ADCBUFF. RAM ch c rng 12-bit nhng d liu cha trong n li l mt trong bn dng s 16-bit l: nguyn, nguyn c du, phn s, v phn s c du..................................................................................................................................302.3.7.2. Cc bc thc hin bin i A/D.......................................................................................................................30

Chng 3. Thc Nghim...............................................................................................333.1. PHN CNG.........................................................................................................................................................33 3.1.1. Cc khi ngun.........................................................................................................................................34 3.1.2. Khi cc b lc thng thp.......................................................................................................................35 3.1.3. Khi bin i DAC ...................................................................................................................................363.1.3.1. Hot ng ca DAC v tnh cht ca n............................................................................................................36 3.1.3.2. Cc tham s ca b chuyn i DA ..................................................................................................................38



Kha Lun Tt Nghip

3.1.3.3. Cc mch DAC in hnh..................................................................................................................................39 3.1.3.4. Ghp ni ADC vi vi iu khin........................................................................................................................41 3.1.3.5. B bin i DAC s dng trong kha lun .......................................................................................................41

3.1.4. Khi khuych i tn hiu vo...................................................................................................................433.1.4.1. Tm hiu v mt s mch khuych i thut ton v tnh cht ca n................................................................43 3.1.4.2. B khuych i s dng trong kha lun (AD620)............................................................................................47

3.1.5. Khi LCD..................................................................................................................................................48 3.1.6. Khi x l trung tm.................................................................................................................................49 3.2. PHN MM..........................................................................................................................................................49 3.3. CC KT QU THC NGHIM:...................................................................................................................................51 3.3.1. Mch khuych i lock-in ch to v tn hiu vo ra lock in:.............................................................51 3.3.2.Th nghim b khuych i lock-in vi cm bin p sut MPX2300D:...................................................553.3.2.1. Cm bin p sut MPX2300D:..........................................................................................................................55 3.3.2.2. Kt qu th nghim:............................................................................................................................................56

Kt Lun.........................................................................................................................59 Ph Lc...........................................................................................................................60



Kha Lun Tt Nghip

Bng cc k hiu, ch vit ttVK ADC DAC KTT AC DC : : : : : : Vi iu khin Chuyn i tng t s (Analog digital convert) Chuyn i s tng t (Digital analog convert) Khuych i thut ton Dng in xoay chiu Dng in mt chiu



Kha Lun Tt Nghip



Kha Lun Tt Nghip

M uVi s pht trin mnh hin nay ca vic ng dng cc cm bin th vic thit k nhng h o v kho st cm bin l rt cn thit, n l mt thit b khng th thiu cho bt k mt phng th nghim no. Mt h o nhy v c chnh xc cao cn c ng dng trong y hc, chnh l nhng my xt nghim y sinh. Ngoi ra n cn c ngha quan trng ti nhiu ng dng cn chnh xc cao trong khoa hc k thut (v d nh: o lng chnh xc, robotic, ....) Nhiu cm bin c thit k c li ra in p rt nh, chnh v vy vic pht hin s sai lch v o in p ra l rt kh khn. Do tng thit k mt h o lng c nhy cao cho nhng cm bin ny l rt quan trng, v mt trong nhng tng l h o c s dng b khuych i lock-in. Vi nhn l mt b khuych i lock-in chng ta s c c mt h o sensor kh l tng, n c th cung cp nhng php o phn gii cao nhng tn hiu mt cch tng i sch vi ln v tn s ring bit. Vic thit k mt h o m c nhn l b khuych i lock-in c in cng kh phc tp v trong b khuych i cn c cc b trn knh v b lc c chnh xc cao. Ngoi ra trong b khuych i lock-in tng t th nh hng t vic tri nhit v gi ha ca cc linh kin s gy ra s sai s ln cho h o. Nhng nu ta thit k mt b khuych i lock-in s th kh thi hn nhiu. Vi cng ngh s, mt vi iu khin c th m nhim tt vai tr l b b lc v b trn knh c chnh xc cao. V c s ha nn s khng c hin tng tri nhit v gi ha linh kin gy sai s nh hng ti h o.Chnh v vy mt b khuych i lock-in s l la chn thng minh nht ca ngi s dng. V Trong kha lun ny em s tm hiu thit k mt b khuych i lock-in s da trn vi iu khin DsPic. V t hnh thnh nn mt h o n gin vi nhn l b khuych i lock-in s v s th nghim h o vi cm bin p sut MPX2300D ca Motorola.


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Kha Lun Tt Nghip

Chng 1. B Khuch i Lock In1.1. Tng quan v b khuych i lock in 1.1.1. Gii thiu Trong rt nhiu ng dng o nhng tn hiu AC rt b c th b ti vi nanovolts ngi ta khng th s dng php o thng thng (s dng cc my o vn nng chng hn). chnh l nguyn nhn ra i ca b khuych i lock in (lock-in amplifier). Vy ti sao ta li khng d dng o c nhng tn hiu AC nh (vi nanovolts)? Ta xt cc v d sau.[8] V d 1: Cho mt tn hiu sng sine 10nV tn s 10kHz. R rng l s khuych i cn phi cho ra tn hiu ln hn n. Mt b khuch i tt (low-noise) s c mt n li vo khong 5nV/sqrt(Hz). Nu bng thng ca b khuych i l 100kHz v h s khuych i l 1000 ln, chng ta thu c li ra: Tn hiu li ra: (10nV x 1000) = 10uV100 KH z

Tn hiu nhiu di rng: (5nV x

x 1000)=1,6mV

Nh vy chng ta khng c nhiu c hi o tn hiu ny nu chng ta khng chn ra tn s chng ta mong mun.(Xem minh ha trn Hnh 1.1) V d 2: Nu ta lp thm mt b lc di thng vo b khuych i vi Q=100 (mt b lc cc k tt Q y c xem l h s phm cht ca b lc) tm thng l 10kHz, bt k tn hiu no trong vng 100Hz (10kHz/Q) xung quanh tm cng s c pht hin. Nhiu trong trng hp ny s l (5nV x 100 Hz x 1000) = 50uV, v tn hiu s vn l 10uV. Nhiu li ra vn ln hn nhiu ln tn hiu, v khng th to ra c mt php o chnh xc. Nh vy tng h s khuch i khng th no gip tng t s tn hiu trn n (S/N).(Xem minh ha trn Hnh 1.2) Vy mun o c tn hiu, ta phi thit k mt b lc c h s Q ln, nhng vic ny l rt kh v khng kh thi.Tuy nhin mt b d nhy pha (Phase Sensitive Detector) c th c Q ln c 10000. Nn n trong tn hiu nu 2 v d trn ch cn l 10u.


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Kha Lun Tt Nghip

Hnh 1.1. Nhiu v tn hiu[2]

Hnh 1.2. n b trit tiu sau khi qua b lc thng thp[2] K thut d nhy pha (Phase-Sensitive Detection) : C th ni B d nhy pha - Phase Sensitive Detection (PSD) l tri tim ca b khuych i lock in, n c xem nh l mt b hon iu hay b trn. My d tm c vn hnh bi vic nhn ln hai tn hiu cng nhau. Phn tch sau y ch ra ti sao n cho ta nhng tn hiu mong mun. Hnh 1.3 ch ra v tr u b khuych i lock in pht hin ra mt ng tn hiu khng tp nhiu (noise-free) hnh sin. Xc nh trong s nh Signal In. Thit b


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Kha Lun Tt Nghip

c nui vi ngun tn hiu tham chiu (hay cn gi l tn hiu reference l dng tn hiu hnh sin, c ci t sn).

Hnh 1.3.Tn hiu, tn hiu tham chiu v tch ca hai tn hiu[15] B d nhy pha c vn hnh bi vic nhn hai tn hiu ny v kt qa l ta thu c tn hiu Demodulator Output nh trn hnh. T ta thy khng c s khc pha gia tn hiu vo v tn hiu reference. Demodulator output gi dng hnh sin, nhng tn s th gp 2 ln tn s ca tn hiu reference, mc trung bnh l dng. Hnh 1.4 cng nh hnh 1.3 nhng c s dch pha 90 0 ca tn hiu reference. By gi Demodulator output vn l mt sng sin c tn s bng hai ln tn s tn hiu reference, nhng mc trung bnh th bng 0.

Hnh 1.4. Tn hiu, tn hiu tham chiu dch 90o v tch ca hai tn hiu[15]


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Kha Lun Tt Nghip

T y ta c th nhn thy mc trung bnh l: T l vi tch s ca tn s bin ca tn hiu vo v tn hiu reference. Lin quan ti gc pha gia tn hiu vo v tn hiu reference.

N s c nh gi nu bin tn hiu reference c gi ti mt gi tr c nh v pha ca tn hiu reference c iu chnh m bo mt chuyn dch pha tng i bng zero. Sau c th o xc nh c mc trung bnh bin tn hiu u vo. Mc trung bnh tt nhin l thnh phn DC ca li ra c gii bin iu (demodulator output). ly c thnh phn mt chiu ny rt n gin, ta ch cn cho tn hiu qua b lc thng thp. Sau khi c lc, tn hiu DC c o bng phng php truyn thng (dng vn k). trn ta xt n trng hp tn hiu vo l mt tn hiu sch khng c n. Nhng trong nhng ng dng thc t tn hiu vo lun i km vi n nhiu. n nhiu ny khng c tn s c nh hoc khng c mi quan h pha c nh. n ny cng c nhn ln vi tn hiu reference, nhng khng a ra bt k mc thay i DC no. Xt mt tn hiu vo c dng hnh sin, tn hiu ny khng c n: V in=Acos(t), y =2F, F l tn s tn hiu vo. Trong b khuych i lock in c cung cp mt tn hiu reference c cng tn s vi tn hiu vo c dng sau: Vref = Bcos(t + ), l lch pha gia 2 tn hiu. Nu ta nhn 2 tn hiu ny vi nhau ta c : Vout = A cos (t) . B cos (t + ) = AB cost (cos t cos - sin t sin ) = AB(cos2t cos - cos t sin t sin ) = AB(( + cos 2t)cos - sin 2t sin ) = AB((1+ cos 2t)cos - sin 2t sin ) = AB(cos + cos 2t cos - sin 2t sin ) = ABcos + AB(cos 2t cos - sin 2t sin ) = ABcos + ABcos(2t + )


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Kha Lun Tt Nghip

By gi nu ta cho tn hiu ra Vout qua b lc thng thp th iu hin nhin l thnh phn 2t s b loi b. Vy kt qu l ta ch cn li tn hiu DC (mt chiu). V iu dn ti Vout =ABcos t l vi bin tn hiu vo Vin. Thut ton ny cho ta mt tng v vic bin mt tn hiu AC thnh DC c gi tr bng bin ca AC ban u nhn vi N ln. Trong nhng hon cnh thc t, tn hiu u vo thng i km vi nhiu n, nhng nu chng ta ci t mt b lc thng thp ph hp u ra ca tn hiu th mi tn hiu nhiu vi mi quan h pha khc nhau v vy th bt k tn s khc nhau no c th b loi b tn hiu cui cng. 1.1.2. Khi nim lock in amplifier B khuych i lock in cn bn l thit b vi kh nng kp. N c th khi phc nhng tn hiu trong s c mt ca nhiu n. Ni mt cch khc, n c th cung cp nhng php o phn gii cao nhng tn hiu mt cch tng i sch vi ln v tn s ring bit. Tuy nhin, nhng thit b hin i a ra nhiu hn hai chc nng c bn trn. V d mt b khuych i lock in hin i c th c nhng chc nng sau: - Thit b khi phc tn hiu AC - o pha - o ting n, nhiu. - Vn k vector - B phn tch ph -..v.v......... Chnh v tnh linh hot ny m n c ngha rt quan trng trong bt k mt phng th nghim no. 1.1.3. Cu trc chung ca b khuych i lock in B khuych i lock-in gm c cc thnh phn chnh l : b khuych i tn hiu vo v ra, b lc thng di (bandpass filter), b trn (mixer), b lc thng thp (lowpass filter) v b pht tn hiu reference.(Hnh 1.5)


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Kha Lun Tt Nghip

Hnh 1.5. S b khuych i lock in [15] C hai cch thc thi s trn. Trong phng php c in tt c cc chc nng ca b lock-in u c thc hin bng k thut analog (tng t). Nhng cng c mt phng php khc c th thc thi s trn, l phng php da trn k thut s (digital). Chnh v vy c hai cch ch to b khuych i lock-in : b khuych i lock-in tng t v b khuych i lock-in s s c trnh by di y. 1.2. B khuych i lock in tng t (Analog Lock-In Amplifiers) S khi ca mt b khuych i lock in c in hay b khuych i lock-in tng t c ch ra trn Hnh 1.6. H thng gm c mt my khuych i tng tn hiu u vo cn o n mt mc thch hp cho cc thao tc sau. Mt b lc thng di c dng loi b bt k thnh phn tn hiu no hoc ti mc DC hoc ti nhng ha m ca tn hiu c o. Tip n l mt my d nhy pha (Phase Sensitive Detector), cn c gi l mt b hon iu(gii bin iu) ng b (synchronous demodulator ) hoc b trn (mixer). Mch ny c th c nhiu dng, t b khuych i logarit n cc b nhn four quadrant. Tn hiu vo c nhn vi mt tn hiu reference c a ra t h thng ang c o. Tn hiu reference cn c mt mt tng quan pha c nh vi tn hiu vo. V vy b khuych i lock-in pht ra mt sng sin reference ni ti ca chnh n nh mt vng kha pha (phase-locked-loop) kha vo tn hiu reference ca tn hiu. Trong qu trnh x l tn hiu tip theo ta, thng dng chc nng knh kp. Trong trng hp ny tn hiu vo c trn u vi tn hiu reference, v ngoi ra tn hiu ny cng c trn vi tn hiu reference sau khi c dch pha 900.


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Kha Lun Tt Nghip

Hnh 1.6. S khi b khuych i lock-in tng t[8] Chc nng knh kp ny c tc dng ln ti s tnh ton ln ca tn hiu vo v mi tng quan pha ca n vi tn hiu reference. Hai knh ring bit ny thng c gi l thnh phn cng pha (In-Phase component) v thnh phn vung pha (Quadrature component) hoc tng ng l I v Q. Cui cng, u ra t nhng b trn (mixer) c a vo b lc thng thp c kh nng loi b mi tn hiu khng ng b (non-coherent), li mt tn hiu DC cui cng t l vi bin v pha ca tn hiu vo. C mt s vn vi b khuych i lock-in tng t. c mt s chnh xc cao, tn hiu reference phi c hm lng sng hi rt thp. N phi l mt sng hnh sin thun khit, bt k hm lng sng hi no s gy ra s bin dng ti u ra. Nhng my pht sng hnh sin tng t c th cng chu t nhng bin i bin gy bi s bin i ca nhit . S tri nhit v sai s ca cc linh kin trong h thng cng c th gy ra nhng vn khc na cho h thng tng t. Cui cng, cn ni thm rng bt k mt phi tuyn no trong h s khuych i v pha cng c th dn n cc sai s trong tn hiu ra. Vic khc phc cc vn ny khin cho b khuych i lock-in tng t tr nn mt thit b rt t v c s dng khi i hi cc bng thng li vo cao.


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Kha Lun Tt Nghip

1.3. B khuych i lock in s (Digital Lock-In Amplifiers) S khi ca mt b khuych i lock in s c ch ra trn Hnh 1.7

Hnh 1.7. B khuych i lock in s[8] Trong mt b khuych i lock in s, phn ln cc qu trnh x l c thc hin trong min s s dng phn mm v dng phn cng l b x l tn hiu s (DSP). Hnh 1.7 l mt b khuych i s in hnh, h thng ny cng c mt b khuych i fron-end nhng n c ni bi mt b lc Anti-alias Filter dng lc bt k tn hiu no c tn s ln hn na tn s ly mu. B iu khin tn hiu s (Digital signal controller) y c th s dng nhiu loi chip x l s chuyn dng, v d nh dsPic chng hn (dsPic l mt chip x l s tng i mnh, tc cao). Tn hiu reference trong b khuych i lock in s c th c to ra bn trong hoc bn ngoi. Trong trng hp tn hiu c pht sinh ni ti, nhng im mu ring l ca tn hiu reference c th tnh ton ti mt mc chnh xc cao, v bi vy khng c nhng sai s thng gp khi dng tn hiu reference nh trong cc my lock-in tng t. Tn hiu reference trong b khuych i lock-in s c dch pha 900 rt n gin bng cch tra cu bng hoc bng nhng php ton n gin. Tip theo tn hiu reference v tn hiu dch pha reference c nhn vi tn hiu vo bi DSP v sinh ra ra 2 knh tn hiu,


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Kha Lun Tt Nghip

mt knh tn hiu ng pha I v mt knh tn hiu vung pha Q. Cui cng nhng knh tn hiu ny c cho qua mt b lc thng thp s (c th y l b lc s FIR) thu c nhng kt qa cui cng. Do tn hiu vo c s ha bi b chuyn i ADC nn s khng b mt mt. Hn na, v tn hiu tham chiu (reference) c tnh bng phng php s nn c lng ha m rt thp. iu quan trng na l s lch gy bi tnh phi tuyn ca h s khuych i v pha ca cc linh kin tng t s b trit tiu trong b khuych i lock-in s v s khng c cc sai lch gy bi s tri nhit hoc s gi ha ca cc linh kin. Cui cng b vi x l s tnh ton ln vector ca tn hiu ra v lch pha ca tn hiu li vo so vi tn hiu reference qua cng thc sau :Magnitude = I 2 +Q2

Phase = tan 1 (Q / I )


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Kha Lun Tt Nghip

Chng 2. Vi iu Khin DsPic30F4011Trong bn kha lun ny b x l s ca mch khuych i lock-in s dng mt vi iu khin DsPic vi nhn hiu thng mi l DsPic30F4011 ca hng Microchip. Ton b ni dung chng 2 ny c ly t ti liu [6].

1

2.1. Gii thiu chung v h vi iu khin Dspic

H vi iu khin 16 bit dsPic do cng ty cng ngh Microchip Technology Inc. sn xut, c pht trin trn nn h vi iu khin 8 bit Pic. Vi iu khin dsPic l mt chip x l mnh vi b x l 16 bit (c kh nng x l d liu c di 16 bit). Vi tc tnh ton cao da trn kin trc RISC, kt hp cc chc nng iu khin tin ch ca mt b vi iu khin hiu nng cao 16-bit (highperformance 16-bit microcontroller), c th thc hin chc nng ca mt b x l tn hiu s (DSP) nn dsPIC cn c th c xem l mt b iu khin tn hiu s (Digital Signal Controller DSC). H vi iu khin dsPic c th t ti tc x l 40 MIPS (Mega Instruction Per Second - triu lnh trn mt giy). Ngoi ra dsPic cn c trang b b nh Flash, b nh d liu EEPROM v cc ngoi vi hiu nng cao v rt a dng cc th vin phn mm cho php thc hin cc gii thut nhng vi hiu sut cao mt cch d dng trong mt khong thi gian ngn. Chnh v vy dsPic c ng dng rt rng ri trong cc ng dng x l tn hiu s, o lng v iu khin t ng, .v..v... H vi iu khin dsPic c chia ra lm ba loi ty theo mc ch ca ngi s dng : -

B iu khin s cho iu khin motor v bin i ngun (DSC Motor Control & Power Conversion Family) B iu khin s cho sensor (DSC Sensor Family) B iu khin s a mc ch (DSC General Purpose Family)

-

2

2.2. c im chung ca vi iu khin dsPic30F4011 2.2.1. Khi x l trung tm CPU - Tp lnh c bn gm 84 lnh


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Kha Lun Tt Nghip

- Ch nh a ch linh hot - di lnh 24-bit, di d liu 16-bit - B nh chng trnh Flash 24 Kbytes - B nh RAM ln 1Kbytes - B nh EEPROM - Mng 16 thanh ghi lm vic 16-bit - Tc lm vic ln ti 40 MIPS 2.2.2. B chuyn i tng t s ADC - B chuyn i tng t - s (ADC) 10-bit + Tc ly mu ti a 1 Msps (Mega samples per second) + Ti a 10 knh li vo ADC + Thc hin bin i c trong ch Sleep v Idle - Ch nhn bit in th thp kh lp trnh - To Reset bng nhn din in p kh lp trnh 2.2.3. Cc cng vo ra I/O Port v cc ngoi vi - Dng ra, vo cc chn I/O ln: 25 mA - 3 Timer 16-bit, c th ghp 2 Timer 16-bit thnh Timer 32-bit - Chc nng Capture 16-bit - Cc b so snh/PWM 16-bit - Module SPI 3 dy (h tr ch Frame) - Module I2C, h tr ch a ch t, a ch t 7-bit n 10-bit - UART c kh nng a ch ho, h tr b m FIFO 2.2.4. B x l tn hiu s - Np d liu song song - Hai thanh cha 40-bit c h tr bo ho logic


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- Thc hin php nhn 2 s 17-bit trong mt chu k my - Tt c cc lnh DSP u thc hin trong mt chu k my - Dch tri hoc phi 16 bit trong mt chu k my 2.2.5. Mt s c im khc - B nh Flash: ghi/xo ln ti 10.000 ln (iu kin cng nghip) v trn di 100.000 ln (thng thng) - B nh EEPROM: ghi/xo ln ti 100.000 ln (iu kin cng nghip) v trn di 1.000.000 ln (thng thng) - Kh nng t np trnh di iu khin ca software - Watch Dog Timer mm do vi b dao ng RC ngun thp trn chip. - Ch bo v firmware kh lp trnh - Kh nng t lp trnh ni tip trn mch in (In Circuit Serial Programming ICSP) - C th la chn cc ch qun l ngun: Sleep hoc Idle

3

2.3. Cu trc ca vi iu khin dsPic30F4011 2.3.1. Khi x l trung tm CPU

CPU ca dsPic30F4011 c thit k trn kin trc RISC, nhn ca CPU c mt b x l lnh 24-bit v b m chng trnh Program Counter (PC) rng 23-bit vi bit ngha thp nht lun bng 0, cn bt ngha cao nht th c b qua trong sut qu trnh thc hin chng trnh bnh thng, ch tr khi thc hin cc lnh c bit. Do , b m chng trnh c th nh a ch ln ti 4 triu t lnh ca khng gian b nh chng trnh c s dng. Thit b dsPIC30F cha 16 thanh ghi lm vic 16-bit. Mi thanh ghi lm vic c th c th lm vic vi vai tr nh d liu, a ch hoc thanh ghi a ch offset. Thanh ghi th 16 (W15) hot ng nh l con tr ngn xp mm cho hot ng ngt v gi ngt. Cc ch lnh ca dsPIC30F gm 2 lp: Lp MCU v Lp DSP ca lnh. Hai lp ny c kt hp ng nht vi nhau trong kin trc v thc hin t mt khi thc hin n.


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Kha Lun Tt Nghip

Cc ch lnh bao gm nhiu ch a ch v c ch to nhm tng thch vi trnh bin dch ngn ng C. Khng gian d liu c th c a ch ho thnh 32K words hoc 64 Kbytes v c chia lm hai khi, c gi l b nh d liu X v b nh d liu Y. Mi khi u c khi to a ch - AGU (Adress Generator Unit) ring bit ca n. Tt c cc lnh hot ng n c ch qua b nh X, v khi AGU quy nh s xut hin ca mt vng d liu thng nht. Lp thanh cha php nhn (Multiply-Accumulate) MAC ca lnh DSP hot ng thng qua c hai khi AGU ca b nh X v Y, n chia a ch d liu thnh hai phn. Mi t d liu gm 2-bytes, v tt c cc lnh c th nh a ch d liu theo bytes hoc words (t). C hai cch truy xut d liu trong b nh chng trnh l: - 32 Kbytes cao ca vng nh d liu c th c sp xp trong na thp ca khng gian chng trnh ti bin ca 16K t chng trnh bt k, c nh ngha bi thanh ghi PSVPAG 8-bit (Program Space Visibility Page). Do cc lnh c th truy cp khng gian chng trnh nh khng gian d liu, nhng c mt gii hn l n cn thm mt chu k lnh na. Ch c 16 bt thp ca mi t lnh c th s dng phng thc truy cp ny. - Truy cp trc tip khng tuyn tnh ca cc trang 32K t nm trong khng gian chng trnh cng c th s dng cc thanh ghi lm vic, thng qua bng lnh c v ghi. Bng lnh c v ghi c th c s dng truy cp c 24 bit ca mt t lnh. Khi X AGU (khi AGU ca b nh X) cng h tr vic o bit a ch trn a ch ch kt qu nhm n gin ho ti a d liu vo hoc ra chng thch hp cho thut ton FFT c s 2. Vi tt c cc lnh, nhn ca dsPIC30F c kh nng thc hin vic c b nh d liu hoc b nh chng trnh, c thanh ghi lm vic, ghi vo thanh ghi lm vic v c b nh chng trnh mi chu k lnh. Nh vy, lnh 3 ton hng c h tr, cho php thc hin php tnh C = A + B trong mt chu k lnh.


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Hnh 2.1. S khi DsPic30F4011


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Hnh 2.2. Cc thanh ghi ca khi x l trung tm


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Cng c DSP c tch hp vo vi x l lm tng ngha ca mt CPU mnh v thut ton. c im ca n l thc hin tc cao mt php nhn hai s 17-bit, mt khi s hc v logic (ALU) 40-bit, hai thanh cha c kh nng bo ho 40-bit v mt b dch hai hng 40-bit. D liu trong thanh cha hoc bt k mt thanh ghi lm vic no c th c dch tri 15 bit hay dch tri 16 bit ch trong mt chu k lnh. Cc lnh DSP hot ng thng nht vi tt c cc lnh khc v c thit k nhm thch hp vi vic x l thi gian thc. Lp MAC ca lnh c th ng thi np hai ton hng d liu t b nh trong khi ang nhn hai thanh ghi W. kch hot ch np ng thi ca ton hng, khng gian d liu c chia nh cho cc lnh ny v tuyn i vi cc lnh khc. Vic ny c thc hin r rng v rt linh hot bng cch dnh mt vi thanh ghi lm vic cho mi khng gian a ch cho lp MAC ca lnh. Nhn ca vi x l khng h tr ng ng a tng lnh, nhng mt lnh n tng s s dng k thut tin np, truy cp v gii m tng phn lnh nhm mc tiu mt lnh ch thc hin trong mt chu k. 2.3.2. Khi to a ch AGU Nhn ca vi x l dsPIC cha hai khi to a ch c lp l X AGU v Y AGU. Khi Y AGU h tr c d liu 16-bit cho lp MAC ca lnh DSP. Cc khi AGU trong dsPIC h tr 3 kiu a ch d liu: a ch tuyn tnh. a ch vng. a ch o bit.

Ch a ch tuyn tnh v a ch vng c th p dng cho khng gian d liu hoc khng gian chng trnh. Ch o bit a ch p dng cho cc a ch khng gian d liu 2.3.2.1. Ch a ch lnhCc ch a ch c cung cp trong lp MAC ca cc lnh th c khc nhau i cht cc lnh khc nhau.


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Kha Lun Tt Nghip

Bng 2.1. Cc ch nh a ch c bn c h tr Lnh thanh ghi tp Tt c cc lnh thanh ghi u s dng trng a ch 13-bit trc tip nh a ch d liu 8192 bytes u ca b nh d liu (gn khng gian d liu). Tt c cc lnh thanh ghi tp u tn dng thanh ghi lm vic W0, thanh ghi lm vic trong cc lnh ny. Lnh MCU Cc lnh MCU 3 ton hng c dng nh sau: Ton hng 3 = Ton hng 1 Ton hng 2 Trong Ton hng 1 lun l thanh ghi lm vic (v d: ch a ch ch c th l thanh ghi trc tip). Ton hng 2 c th l thanh ghi W, ly d liu t b nh d liu, hoc 5 bit thng thng. Kt qu c t trong c th l thanh ghi W hoc mt a ch c nh. Lnh di chuyn v tch lu Lnh di chuyn v cc lp DSP tch lu ca lnh lm cho s mm do ca a ch cao hn cc lnh khc. Tt c cc lnh MCU, lnh di chuyn v tch lu u h tr ch a ch, v cng h tr ch thanh ghi gin tip v thanh ghi a ch offset. Ch : i vi lnh MOV, ch a ch c ch r trong lnh c th khc nhau gia ngun v ch. Tuy nhin trng ca 4-bit offset ca thanh ghi Wb c chia s gia ngun v ch. Cc lnh MAC C hai ton hng ngun ca cc lnh DSP (CLR, ED, EDAC, MAC, MPY.N, MOVSAC v MSC) c xem nh cc lnh MAC, tn dng cc lnh c n gin ho


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ca ch a ch nhm cho php ngi s dng c th iu khin con tr d liu thng qua cc bng thanh ghi gin tip. Hai thanh ghi tin np ton hng ngun phi l mt trong cc thanh ghi sau: {W8, W9, W10, W11}. Vi c d liu, W8 v W9 lun tng tc trc tip vi X AGU, W10 v W11 lun tng tc trc tip vi Y AGU. Do a ch hiu dng c to (trc v sau khi hiu chnh) phi hp l vi a ch trong khng gian d liu X cho W8, W9 v trong khng gian d liu Y cho W10, W11. Cc lnh khc Bn cnh cc ch a ch bin i, mt vi lnh s dng cc hng s c nh dng thay i. V d: lnh BRA (branch phn nhnh) s dng d liu 16-bit c du ch ra ch r nhnh trc tip, trong khi lnh DISI s dng trng s 14-bit khng du. Trong mt vi lnh nh ADD hay ACC, ngun ca mt ton hng hoc kt qu c a ra bi chnh m lnh ca n. Tuy nhin, mt vi lnh nh NOR, li khng c ton hng no. 2.3.2.2. Ch o bit a ch a ch c o bit nhm lm n gin ho d liu cho thut ton FFT c s 2. N c h tr bi khi AGU ca X ch cho vic ghi d liu. Thc hin o bit a ch o bt a ch c bt khi cc iu kin sau c tho mn: Cc bit BWM (la chn thanh ghi W) trong thanh ghi MODCON gi tr ln hn 15 (khng th truy cp ngn xp khi ang s dng ch o bit a ch) Bit BREN c t trong thanh ghi XBREV Ch a ch c s dng l ch thanh ghi gin tip

Nu di b m ca cc bit c o l M = 2N bytes, N bit cui cng ca b m d liu bt u c nh a ch bng khng. Cc bit XB l a ch bit c o, hay cn gi l im xoay (pivot point) thng l hng s.


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Hnh 2.3. Mt v d v o bit a ch 2.3.3. T chc b nh v b nh chng trnh 2.3.3.1. Khng gian a ch chng trnh Khng gian a ch chng trnh c ln 4M t lnh. Bn khng gian b nh chng ca dsPic30F4011 c ch ra trong Hnh 2.4. B nh chng trnh c th c a ch ho bi mt gi tr 24-bit bi b m chng trnh (PC), hoc bng lnh a ch hiu dng (EA), hoc khng gian d liu EA khi khng gian chng trnh c sp xp v a ch ho. Ch rng, a ch khng gian chng trnh c tng ln vi bc l 2 gia cc t chng trnh to ra s tng thch vi vic a ch ho khng gian d liu. Truy cp khng gian chng trnh ngi s dng b gii hn trong di 4M a ch ca t lnh (t 0x000000 ti 0x7FFFFE) vi tt c cc lnh truy cp, tr hai lnh TBLRD/TBLWT - s dng bit 7 ca thanh ghi TBLPAG xc nh ngi s dng hoc thit lp cu hnh truy cp b nh.

Hnh 2.4. Bn khng gian b nh chng trnhSinh Vin : L Trn Triu Tun 20


Kha Lun Tt Nghip

2.3.3.2. Truy xut d liu t b nh chng trnh s dng cc lnh bng Kin trc ca dsPIC cho php np d liu rng 24-bit ti b nh chng trnh, do cc lnh lun lun c xp hng tuy nhin kin trc ca n c ci tin so vi kin trc my tnh Hadvard nn d liu cng c th c a ra trong khng gian chng trnh. C hai phng php truy cp khng gian chng trnh, l:(xem hnh 2.5) - Thng qua cc lnh c bit v bng hoc thng qua vic nh a ch v sp xp li 16K trang t khng gian chng trnh trong na cao ca khng gian d liu. Cc lnh TBLRDL v TBLWTL cung cp phng php c v ghi trc tip t t ngha nht (LS Word) ti mt a ch bt k trong khng gian chng trnh m khng cn thng qua khng gian d liu. Hai lnh TBLRDH v TBLWTH ch l phng thc m 8 bt cao ca t khng gian chng trnh c th c truy xut nh d liu. - B m chng trnh (PC) c tng ln hai vi mi t chng trnh 24-bit. iu ny cho php cc a ch b nh chng trnh nh x trc tip ti a ch khng gian d liu. Do b nh chng trnh c th c xem nh hai khng gian t a ch rng 16-bit. Cc lnh TBLRDL v TBLWTL truy cp khng gian cha t d liu t ngha nht (LS Data Word) v cc lnh TBLRDH, TBLWTH truy cp khng gian cha Byte d liu nhiu ngha nht (MS Data Byte). S trn ch ra cch EA c to cho hot ng bng v truy cp khng gian d liu (PSV = 1). Ti y P (t bit 23 ti bit 0) ch th t khng gian chng trnh, cn D (t bit 15 ti bit 0) ch th t khng gian d liu. 2.3.3.3. Truy xut d liu t b nh chng trnh s dng khng gian chng trnh 32 Kbytes cao ca khng gian d liu c th c bn ho trong bt k trang 16K t b nh chng trnh no. N cho php truy cp vo hng s d liu c lu tr t khng gian d liu X m khng cn cc lnh c bit (nh TBLRDL/H, TBLWTL/H). Truy xut khng gian chng trnh thng qua khng gian d liu c thc hin nu bt ngha thp nht ca khng gian d liu EA c t v ch hin th khng gian chng trnh c bt bng cch t bit PSV trong thanh ghi iu khin nhn ca vi x l CORCON.


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Hnh 2.5 Truy cp d liu t khng gian chng trnh Truy xut d liu vng ny s thm vo mt chu k lnh lnh c thc hin, do np d liu vo hai b nh chng trnh l cn thit. Ch rng ch phn cao ca khng gian d liu c kh nng nh a ch thi lun l mt phn ca khng gian d liu X. Do , khi mt thao tc DSP s dng vic bn ho khng gian chng trnh truy cp b nh thi khng gian d liu Y thng thng s lu tr trng thi d liu cho thao tc DSP, cn khng gian d liu X thng s lu gi h s ca d liu. Tuy nhin mi a ch khng gian d liu , t 0x8000 tr ln, bn ho trc tip vo a ch ca b nh chng trnh p ng (Hnh 2.6) ch c 16 bit thp ca t chng trnh 24 bit c s dng lu d liu. 8 bit cao c lp trnh loi b cc lnh khng hp l nhm gi nguyn sc mnh ca b vi x l.


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Hnh 2.6. nh x khng gian d liu vo khng gian chng trnh 2.3.4. Cc cng vo ra I/O Port Cc cng vo ra ca dspic40f4011 u c thit k c u vo l mch Trigger Schmitt nhm ci tin kh nng chng nhiu. Tt c cc cng vo ra u c ba thanh ghi kt hp vi nhau iu khin trc tip hot ng ca cc cng. - Thanh ghi d liu trc tip (TRISx) xc nh cng l Input hay Output. Nu bit d liu trc tip l 1, th cng l Input v ngc li. Cc cng c nh ngha l Input sau khi Reset. - Thanh ghi cng (PORT registers): d liu mt cng I/O c truy xut thng qua thanh ghi PORTx. c gi tr ca thanh ghi PORT cng no s c c gi tr ca cng . Ghi vo thanh ghi PORT ca cng tng ng vic xut d liu ra cng . - Thanh ghi LAT, kt hp vi mt cng I/O s loi b c cc vn c th xut hin khi c-thay i-ghi vo cng . c gi tr thanh ghi LAT s tr v gi tr c gi u ra ca b cht cng , thay cho gi tr cng I/O. Vic ghi vo thanh ghi LATx cng to ra hiu qu nh ghi vo thanh ghi PORTx. Cu hnh tng t cho cng: khi s dng b ADC th cng c cu hnh l li vo tng t. iu ny s c ni k hn phn miu t ADC.


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Hnh 2.7. Cc cng I/O ca dsPic30F4011

Hnh 2.8. S khi ca mt cng I/O dng chung vi ngoi vi khc


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2.3.5. Ngt v c ch ngt Vi iu khin dsPic30F4011 c ti 30 ngun ngt v 4 b x l loi tr (by li), b x l ny s cho php cc ngt theo mc u tin c sp t trc. CPU c th c bng vector ngt v truyn a ch c cha trong vector ngt ti b m chng trnh. Vector ngt c truyn t bus d liu chng trnh vo trong b m chng trnh thng qua b hp knh 24-bit, li vo ca b m chng trnh. Bng vector ngt (Interrupt Vector Table - IVT) v bng vector ngt thay th (Alternate Interrupt Vector Table - AIVT) c t gn im bt u b nh chng trnh (0x000004). IVT v AIVT c ch ra trong Bng 2.2. Cc thanh ghi iu khin ngt v u tin ngt:INT Vector Interrupt Source Number Number Highest Natural Order Priority 0 8 INT0 External Interrupt 0 1 9 IC1 Input Capture 1 2 10 OC1 Output Compare 1 3 11 T1 Timer 1 4 12 IC2 Input Capture 2 5 13 OC2 Output Compare 2 6 14 T2 Timer 2 7 15 T3 Timer 3 8 16 SPI1 9 17 U1RX UART1 Receiver 10 18 U1TX UART1 Transmitter 11 19 ADC ADC Convert Done 12 20 NVM NVM Write Complete 13 21 SI2C - I2C Slave Interrupt 14 22 MI2C I2C Master Interrupt 15 23 Input Change Interrupt 16 24 INT1 External Interrupt 1 17 25 IC7 Input Capture 7 18 26 IC8 Input Capture 8 19 27 OC3 Output Compare 3 20 28 OC4 Output Compare 4 21 29 T4 Timer4 22 30 T5 Timer5 23 31 INT2 External Interrupt 2 24 32 U2RX UART2 Receiver 25 33 U2TX UART2 Transmitter 26 34 Reserved 27 35 C1 Combined IRQ for CAN1 28 - 38 36 - 46 Reserved 39 47 PWM PWM Period Match 40 48 QEI QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA PWM Fault A 44 52 Reserved 45 - 53 53 - 61 Reserved Lowest Natural Order Priority

Cc thanh ghi 16-bit IFS0, IFS1, IFS2

Tt c cc c ngt c lu trong 3 thanh ghi ny. Cc c c t tng ng bi ca ngoi vi hoc tn hiu bn ngoi v c th xo bng phn mm.


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Bng 2.2. Bng vector ngt ca dsPIC30F3012 - Cc thanh ghi 16-bit: IEC0, IEC1, IEC2: Tt c cc bit iu khin cho php ngt u nm trong 3 thanh ghi ny. Cc bit ny c s dng cho php ngt c lp ngoi vi v tn hiu ngoi-

Cc thanh ghi u tin ngt: IPC0 ... IPC10: Ngi s dng c th chuyn i mc u tin ngt kt hp vi mi ngt c gi trong cc thanh ghi ny Nhm bit IPL: Mc u tin ca CPU hin hnh c lu r rng trong cc bit ny. Bit IPL nm trong thanh ghi CORCON, trong khi cc bit IPL nm trong thanh ghi trng thi (SR) Hai thanh ghi 16-bit INTCON1, INTCON2: Chc nng iu khin ngt ton cc c xut pht t hai thanh ghi ny. INTCON1 cha cc c iu khin v trng thi ca b x l loi tr. INTCON2 iu khin tn hiu yu cu ngt v vic bng vector ngt thay th.

-

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Cc ngun ngt c th c ngi s dng sp xp mc u tin t 1 n 7 thng qua thanh ghi IPCx. Mi ngun ngt c kt hp vi mt vector ngt (bng 2.2)


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Hnh 2.9. Cc vector by li 2.3.6. Cc b nh thi Trong vi x l dsPIC40F4011 c ti nm b nh thi (Timer) 16-bit. Trong cc Timer c th hot ng ring bit, ring hai Timer 2, 3 v hai Timer 4, 5 c th kt hp vi nhau tr thnh mt Timer 32 bit. V cu trc cc Timer ny khc nhau v hai Timer 2 v 3 v hai Timer 4 v 5 c th kt hp cn Timer 1 th khng. Timer 1 c cu trc kiu A (Hnh 2.10), Timer 2,4 kiu B v Timer 3,5 kiu C. V hot ng cc Timer c hot ng gn ging nhau do ta s tm hiu v Timer 1, cc Timer cn li l tng t. Timer 1 c th hot ng vi ngun to dao ng tn s thp 32KHz, v ch khng ng b vi ngun to dao ng ngoi. c im ring bit ca Timer 1 l c th dng trong cc ng dng thi gian thc. Phn tip theo s m t chi tit cch thit lp v s dng Timer 1 vi ba ch : - Timer 16-bit: trong ch ny, timer s tng sau mi chu k lnh n khi gi tr ca timer bng gi tr ca thanh ghi chu k PR1 (Period Register) th s reset v 0 v tip tc m.-

Counter ng b 16-bit: trong ch ny, timer s tng mi sn ln ca ca xung nhp ngoi m c ng b vi pha ca cc xung nhp trong. Timer tng n gi tr nm trong thanh ghi PR1 th dng v reset timer v 0 ri tip tc m ln. Counter khng ng b 16-bit: khi hot ng trong ch ny, timer s tng dn sau mi sn ln ca xung nhp bn ngoi tc ng vo. Timer s tng dn n khi gi tr ca n bng thanh ghi PR1 th b reset v 0 ri li tip tc m ln.

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H s chia tn ca b nh thi Xung nhp u vo (Fosc/4 hoc xung nhp ngoi) a vo Timer 16-bit v c th c chia tn s theo cc t l sau: 1:1, 1:8, 1:64, 1:256 c xc nh bi cc bit TCKPS ca thanh ghi TxCON. H s chia tn ny (prescaler) c th b xo khi xy ra mt trong cc iu kin sau: Ghi vo TMR Ghi vo thanh ghi TxCON (tr vic ghi vo bit TxCON)


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Reset thit b, nh POR v BOR DsPic30F4011 c 5 thanh ghi iu khin Timer T1CON..T5CON. Cc thanh ghi ny c chia ra lm 2 kiu. T1CON thuc kiu A, T2CON v T4CON thuc kiu B, T3CON v T5CON thuc kiu C.

Hnh 2.10. S khi ca Timer 1


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Hnh 2.11. S khi Timer 2

Hnh 2.12. S khi Timer 3


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Hnh 2.13. S khi Timer 2/3 - 32bit (S khi Timer 4/5 32 bit v Timer 4,5 16 bit ging nh Timer 2/3 32 bit v Timer 2,3 16 bit) 2.3.7. B chuyn i tng t s ADC Vi iu khin dsPic30F4011 cung cp b chuyn i tng t s 10-bit cho php bin i tn hiu tng t u vo sang s di 10-bit. Module ny da trn thanh ghi SAR (Successive Approximation Register thanh ghi xp x) v cung cp tc ly mu ti a ln ti 100 ksps. ADC ca dsPic30F4011 c ti 10 knh tng t li vo c kt hp c ly mu v gi mu. Li ra ca b ly v gi mu l li vo ca b chuyn i to ra kt qu bin i. in th tng t chun c th l in th ngun cung cp (AVDD/AVSS) hoc mc in th ca cc chn VREF+/VREF-. B bin i ADC ca dsPIC bao gm 6 thanh ghi: Ba thanh ghi iu khin A/D: ADCON1, ADCON2, ADCON3 Chc nng iu khin hot ng ca ADC. Thanh ghi la chn li vo: ADCHS La chn knh vo bin i. Thanh ghi cu hnh cng ADPCFG Cu hnh cng tr thnh li vo tng t hoc vo ra s. Thanh ghi la chn qut 2.3.7.1. B m kt qu bin i A/D Module ADC s dng RAM lm b m lu kt qu bin i A/D. C tt c 16 v tr trong RAM c s dng lm vic ny, l: ADCBUF0, ADCBUF1, ADCBUF2, ..., ADCBUFE, ADCBUFF. RAM ch c rng 12-bit nhng d liu cha trong n li l mt trong bn dng s 16-bit l: nguyn, nguyn c du, phn s, v phn s c du. 2.3.7.2. Cc bc thc hin bin i A/D a) Thit lp cu hnh cho module A/D - Cu hnh cc chn l li vo tng t, in th chun v vo ra s. - Chn cc knh li vo cn bin i.


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Chn xung nhp cho bin i. Cho php module ADC c th hot ng.

b) Cu hnh cho ngt ADC nu cn - Xa c ngt ADIF - La chn mc u tin ngt cho bin i A/D c) Bt u ly mu d) i thi gian cn thit hon thnh e) Kt thc ly mu, bt u bin i f) i bin i kt thc bi mt trong hai iu kin sau: - i ngt t ADC - i bit DONE c set c kt qu t b m bin i A/D v xa bit ADIF nu cn


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Hnh 2.14. S khi c bn ca ADC 10-bit


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Chng 3. Thc Nghim3.1. Phn Cng Phn cng c em thit k da trn s khi ca mt b khuych i lock in s (Digital Lock-In Amplifiers). Phn cng thit k c nhng khi chnh sau y:(Hnh 3.0) - Khi ngun - Khi cc b lc thng thp (lowpass filter, LP Sallen key filter) - Khi bin i DAC - Khi khuych i tn hiu vo - Khi LCD - Khi x l s trung tm

Ngun 5 V

Sensor Khi X L Lowpass Filter Mn Hnh Hin Th LCD S Trung Tm Khuych i dsPic30F4011 (DSP) DAC R/2R Salenkey Filter

Ngun +12V, -12V

Hnh 3.1. S Khi Phn Cng


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3.1.1. Cc khi ngun Cc khi ngun cn thit k cung cp ngun cho ton b cc khi thnh phn ca b khuych i lock in. C th y ta cn c ngun +5V cp cho khi x l s trung tm (Vi iu khin dsPic30F4011) v mn hnh hin th LCD, ngun +12V,-12V cung cp cho khi b lc s v khi khuych i tn hiu vo. S ca cc khi ngun ny c trnh by trn Hnh 3.2.

Hnh 3.2. Cc khi ngun


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3.1.2. Khi cc b lc thng thp Trong kha lun ny, cn s dng 2 b lc thng thp. Mt b lc thng thp c bn v mt b lc thng thp Sallen Key Filter tha mn yu cu ct tn s ti 10kHz. S b lc thng thp Sellen Key c bn c trnh by trn hnh 3.3

Hnh 3.3. S b lc Sallen Key c bn S b lc Sallen Key dng trong kha lun c trnh by trn hnh 3.4

Hnh 3.4. S d b lc Sallen Key c s dng trong kha lun tha mn tn s ct l 10kHz trong kha lun ny em s dng t C2 = 1000pF => C1 = 2C2 = 1000pF


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Kha Lun Tt Nghip

=> R1 = R2 = 0.707 / (2 fo C2) = 0.707 / (2 10kHz 1000pF) = 11.2 K B lc thng thp cn li c thit k lm trn tn hiu sau khi qua b khuych i analog.(xem hnh 3.5)

Hnh 3.5. B lc thng thp low pass 3.1.3. Khi bin i DAC 3.1.3.1. Hot ng ca DAC v tnh cht ca n

Hnh 3.6. V d v b bin i DA 4 bt Mc ch ca b bin i DA, nh nu, l bin i tn hiu nh phn n bt thnh dng hay p tng ng. Hnh 3.6 l mt v d v mt b bin i DA 4 bt n gin. V nguyn tc b chuyn i s-tng t tip nhn mt m s n bt song song hoc ni tip li vo v bin i ra dng in hoc in p tng ng li ra. Dng in hay in p li ra l hm bin thin ph hp theo m s li vo.


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Kha Lun Tt Nghip

Mt b DAC hon chnh bao gm ba phn t c bn:

in p tham chiu n nh bn ngoi (Vref) DAC c s Khuch i thut ton S khi ca b DAC c trnh by trn Hnh 3.7

Hnh 3.7. S khi DAC Nh vy in p u ra ca b bin i V0 s ph thuc vo m nh phn u vo theo cng thc sau:V0 = Vref (B 0 2 0 + B 1 2 1 + ... + B n 2 n )

Trong B0 l bt thp nht v Bn l bt cao nht ca m nh phn u vo, Vref l in p tham chiu. DAC c s cu to bng nhng chuyn mch tng t c iu khin bi m s u vo v cc in tr chnh xc. Cc chuyn mch tng t iu chnh dng in hay in p trch ra t in p tham chiu v to nn dng in hay in p u ra tng ng vi m s u vo. Mch khuch i thut ton dng y chuyn i dng thnh p ng thi c chc nng tng m.


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Kha Lun Tt Nghip

B bin i DAC c c im l i lng ra tng t khng lin tc, ri rc ca u ra ph thuc vo s bt ca b bin i, nhng DAC c s bt u vo ln th tng s nc in p ra cng ln v khong cch gia cc nc cng nh. 3.1.3.2. Cc tham s ca b chuyn i DA - phn gii (Solution): Lin quan n s bt ca mt DAC. Nu s bt l n th s trng thi ca tn hiu nh phn l 2n ngha l s c 2n mc in th (hoc dng in) khc nhau, do c phn gii l 1/2n. phn gii cng b th in th (hoc dng in u ra) cng c dng lin tc, cng gn vi thc t v ngc li. - chnh xc (Accuracy): C th nh gi cht lng ca mt DAC bng sai s ca n. i lng biu din sai s l lch ti a gia i lng ra v mt ng thng ni im 0 vi im FS (Full Scale) trn c tuyn chuyn i DA. - tuyn tnh (Linearity): tuyn tnh ca DAC cho bit lch in p so vi mt ng thng i qua nhng im nt ca c tuyn chuyn i. l c tnh thng gp nht vi DAC. ng cong c tuyn l n iu nu s thay i lch trn l khng i du. c mt DAC n iu, lch ny phi ln hn 0 cho mi nc thang. Ngoi ra mc tuyn tnh ca DAC phi nh hn hoc bng 1/2 LSB n tr nn n iu. Nh vy 1/2 LSB l c trng v gii hn n iu ca mt DAC. - Phi tuyn vi sai: l i lng cho bit lch gia gi tr thc t v l tng cho mt nc in p ra ng vi mi thay i ca m s vo. i lng ny cho bit v nhn ca ng cong c tuyn i vi DAC. - Thi gian thit lp: i vi mt DAC l thi gian cn thit in p ra t ti gi tr ti hn sai s xung quanh gi tr n nh. Gii hn ny thng l = LSB hoc biu din bng gi tr % FS. Thi gian thit lp trc ht ph thuc vo kiu chuyn mch, kiu in tr v kiu khuch i dng xy dng b DAC. Thng thng n c nh ngha bng thi gian t khi in p bt u thay i cho ti khi t ti vng gii hn sai s cho trc. N khng bao gm thi gian tr tnh t khi c s thay i m s u vo cho ti khi in p ra bt u p ng.


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Kha Lun Tt Nghip

3.1.3.3. Cc mch DAC in hnh Cc DAC c th c xy dng theo mt trong nhng kiu mch sau:

Chuyn i DA theo kiu in tr trng lng Chuyn i DA theo kiu mch R-2R 3.1.3.3.1. B chuyn i DA theo kiu in tr trng lng (Weighted resistor DAC)

Mch gm mt ngun in p chun Uch, cc chuyn mch, cc in tr c gi tr ln lt l R, R/2, R/4, ... , R/2n-1 v cc mch khuch i thut ton.(Xem hnh 3.7) Vi mch nh trn, khi mt kho in no c ni vi ngun in th chun th s cung cp cho b khuch i thut ton (KTT) dng in. Dng in ny c lp vi cc kho cn li. Nh vy c th thy ngay rng bin in p ra ph thuc vo cc v tr c ng hay m kho ngha l c ni vi in p chun Uch hay ni cch khc ph thuc vo gi tr cc bt tng ng trong tn hiu s a vo mch chuyn i.

Hnh 3.8. DAC theo phng php in tr trng lng Mt cch tng qut, vi mt DAC c n bt th tn hiu ra c tnh theo cng thc: Ura = U ch .R1 R

(2n-1.Bn-1 + 2n-2.Bn-2 + ... + 21.B1 + 20.B0)

Trong B0 < Bn-1 c gi tr "0" hoc "1".


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Kha Lun Tt Nghip

Mch c u im l n gin, nhng nhc im l chnh xc v tnh n nh ca kt qu ph thuc nhiu vo tr s tuyt i ca cc in tr v s n nh ca chng trong cc mi trng khc nhau. Ngoi ra cn ph thuc vo tnh n nh v chnh xc ca ngun in p chun. 3.1.3.3.2. B chuyn i DA theo kiu thang in tr R-2R (R-2R ladder)

Hnh 3.9. DAC theo phng php mch R-2R DAC vi thang in tr R-2R khc phc c mt s nhc im ca DAC in tr trng lng. Mch ch gm hai in tr R v 2R mc theo hnh thang vi nhiu kho in (mi kho in cho mt bt) v mt ngun in p chun Uch.(Xem Hnh 3.9) i lng cn tm l dng Ith chy vo mch KTT khi c mt s kho in c ni vi Uch. Theo mch in ta c: Ura = -Ith.Rf Xt ti chuyn mch tng ng vi bt th i, nt tng ng trn mch hnh thang l 2 . S dng nh l Thevenin, khi ng chuyn mch vo Uch th in th tng ng Thevenin ti nt 2i s l Uch/2 v ngun tng c ni tr l R, nh vy ti nt 2i+1 (tin v pha mch KTT) ta c ngun tng ng Thevenin c tr s l Uch/4 v ni tr l R.i


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Kha Lun Tt Nghip

T nhng kt qu trn suy ra rng khi di chuyn v pha mch KTT th tr s in th Thevenin ti mi nt bng mt na tr s ti nt k cn bn tri n, v ti nt 2n-1 do c tnh ca b KTT in th c coi bng 0V. Mt cch tng qut, ta c cng thc tnh in p ra ca mt DAC n bt vi in tr hnh thang R-2R nh sau:U ra = U ch Rt ( 2 n1 B n1 + 2 n 2 B n 2 + ... + 21 B 1 + 2 0 B 0 ) n 2 .R

Trong B0 < Bn-1 c gi tr "0" hoc "1". Cc DAC theo thang in tr phi dng s in tr kh ln, v d nu mt DAC n bt th cn dng 2(n-1) in tr trong khi phng php in tr trng lng ch phi dng n thi. Nhng b li chnh xc v tnh n nh ca tn hiu ra c m bo tt hn. 3.1.3.4. Ghp ni ADC vi vi iu khin V nguyn tc mt b DAC c th ghp ni tng thch vi hu ht cc b VK. i vi cc b DAC 8 bt, cng vic thm ch cn rt n gin khi ghp ni vi cc VK, l do l cc VK u c BUS d liu l bi ca 8. i vi cc b DAC 12 hay 16 bt ta phi s dng cc m trung gian c s bt tng ng sau tin hnh trao i s liu nhiu ln. 3.1.3.5. B bin i DAC s dng trong kha lun Trong kha lun, em s dng kiu bin i DAC mng R/2R 4 bt ghp ni vi vi x l. S ca b bin i c trnh by trn Hnh 3.10

Hnh 3.10. B bin i DAC 4 bit


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Kha Lun Tt Nghip

4 bt c ghp ni vi 4 u ra RE0...RE3 ca vi iu khin dsPic30F4011. iu khin b bin i DAC 4 bit ny em vit chng trnh cho VK to sng sin, theo bng c thit lp nh sau: sinTable[] = {5,6,7,8,9,9,10,10,10,10,10,9,9,8,7,6,5,4,3,2,1,1,0,0,0,0,0,1,1,2,3,4} Sau khi c chng trnh ha trn VK tn hiu ra c dng (xem hnh 3.11)

Hnh 3.11. Tn hiu ra b bin i DAC 4 bt Tn hiu ra s khng mn nh mong mun, mun c mn hn ta cn cho tn hiu qua mt b lc thng thp (c th y l b lc salenkey), Sau khi qua b lc salenkey tn hiu ra s c dng nh hnh 3.12

Hnh 3.12. Tn hiu ra b bin i DAC 4 bt khi qua b lc


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Kha Lun Tt Nghip

3.1.4. Khi khuych i tn hiu vo 3.1.4.1. Tm hiu v mt s mch khuych i thut ton v tnh cht ca n Khuch i thut ton l mt trong s nhng linh kin in t thng gp nht trong k thut tng t, v th trong k thut o lng v iu khin cng nghip, khuch i thut ton cng c mt trong rt nhiu thit b v h thng. Kh nng s dng ca cc b khuch i thut ton l rt vn nng, chng c p dng trong nhiu lnh vc nh cc b khuch i mt chiu, cc b khuch i xoay chiu, b lc tch cc, b dao ng, b bin i tr khng, b vi phn, b tch phn... lm ni bt tnh cht ca mt b khuch i thut ton, hy xt tnh nng ca mt b khuch i thut ton l tng:

H s khuch i khi khng c phn hi m ln v cng. in tr li vo ln v cng. rng di thng ln v cng. H s nn ng pha CMRR ln v cng. in tr li ra bng khng Thi gian p ng bng khng.

Trn thc t, khng c b khuch i thut ton l tng m ch tn ti nhng khuch i thut ton thc c tnh cht gn vi nhng tiu chun nu. Cc tham s v cc mch ng dng ca b khuch i thut ton rt nhiu, khng th nu ht trong bn kha lun ny m y di y ch nu ln nhng tham s c bn, cch tnh ton v cc mch c p dng trong h thng iu khin. 3.1.4.1.1. Cc tham s c bn ca mch khuch i thut ton S nguyn tc ca b KTT c trnh by trn hnh 3.13


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Kha Lun Tt Nghip

Hnh 3.13. B khuch i thut ton. Trn hnh 3.13 ta c cc k hiu sau:

Ud in p vo hiu UP , IP in p vo v dng in vo ca thun. UN , IN in p vo v dng in vo ca o. Ur , Ir in p ra v dng in ra.

B khuch i thut ton khuch i hiu in p Ud = UP - UN vi h s khuch i K0 > 0. Do in p ra: Ur = K0. Ud = K0(UP - UN) (*) i) H s khuch i hiu K0 Khi khng ti h s khuych i hiu Ko c xc nh theo biu thc sauK0 = Ur Ur = Ud U p Un

j) H s khuch i ng pha KCM Nu t vo ca thun v ca o ca b khuch i thut ton cc in p bng nhau, ngha l:


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Kha Lun Tt Nghip

UP = UN = UCM = 0 th Ud = 0. Gi UCM l in p vo ng pha. Theo biu thc (*) ta c Ur=0. Tuy nhin, thc t khng phi nh vy, gia in p ra v in p vo ng pha c quan h t l l h s khuch i ng pha KCM :K CM = U r U CM

KCM ni chung ph thuc vo mc in p vo ng pha. k) H s nn ng pha CMRR Dng nh gi kh nng lm vic ca b khuch i thc so vi b khuch i l tng (KCM=0)CMRR = K0 K CM

l) Dng vo tnh L tr trung bnh ca dng vo ca thun v dng vo ca o:It = IP + IN vi UP = UN = 0 2

Dng vo lch khng l hiu cc dng vo tnh hai ca ca b khuch i thut ton I0 = IP - IN vi UP = UN = 0 Thng thng I0 = 0,1IP. Tr s ca dng vo lch khng thay i theo nhit . Hin tng ny gi l hin tng tri dng lch khng. 3.1.4.1.2. Cc s c bn ca b khuch i thut ton i) S khuch i khng o


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Hnh 3.14. S khuch i khng o H s khuch i ca mch lK= 1 1 R2 1 K + R + R 1 CMRR 1 2 0

j) Mch m y l trng hp c bit ca mch khuch i khng o

Hnh 3.15. S mch m Mch c h s khuch i bng 1 v dng phi hp tr khng. k) Mch khuch i o Mch khuych i o c trnh by trn hnh 3.16.


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Kha Lun Tt Nghip

Hnh 3.16. S mch khuch i o H s khuch i ca mch:K= R2 R1

l) S bin i dng in - in p: c trnh by trn hnh 3.17

Hnh 3.17. S bin i dng in - in p

in p ra c tnh theo biu thc: UR = - R.IV 3.1.4.2. B khuych i s dng trong kha lun (AD620) Trong kha lun ny b khuych i xy dng c s dng vi mch AD620, s c th c trnh by nh hnh 3.18


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Kha Lun Tt Nghip

Hnh 3.18. B khuych i thut ton s dng IC AD620

AD620 l loi IC khuych i thut ton kh tt, n c kh nng khuych i tn hiu ti 1000 ln, ty thuc vo in tr phi ghp. Mt n li vo 9nV/ thng ca b khuych i l 120KHz khuych i c tnh theo cng thc:H z

, bng

G=

49 ,4k 49 ,4k 1 RG = RG G 1

Trong kha lun RG chnh l R7.

3.1.5. Khi LCD Trong kha lun ny em s dng LCD hin th 16 k t 2 dng. Giao tip 8 bit. LCD c tc dng hin th kt qu cui cng ca bi ton. Cc chn iu khin ca LCD c kt ni vi cc chn I/O ca vi iu khin dsPic30F4011. LCD c hot ng thng qua s iu khin ca vi iu khin (VK) dsPic30F4011. Hnh 3.19 trnh by s mch LCD s dng trong kha lun.


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Kha Lun Tt Nghip

Hnh 3.19. LCD 16 k t 2 dng 3.1.6. Khi x l trung tm Khi x l trung tm trong kha lun s dng vi iu khin DsPic30F4011. Khi x l trung tm c nhim v bin i tn hiu vo thnh tn hiu s sau n s dng b dsp x l tn hiu cho ta kt qu cui cng a ra LCD(gm c thc hin cc php nhn v s dng b lc s FIR ).. Tht th v trong VK DsPic30F4011 c tch hp b chuyn i AD nh trnh by phn 2.3.7 trong chng 2. Cng vic ca ngi s dng l chng trnh ha cho VK thc hin vic chuyn i AD. B x l s dsp c tch hp sn trong VK DsPic30F4011 lm cho vic thit k cng n gin hn, vi nhng hm th vin c sn do Microchip cung cp. 3.2. Phn Mm Trong kha lun ny em s dng phn mm MPLab ca cng ty Microchip Technology thc hin vit chng trnh cho khi x l trung tm (c th y l vi iu khin dsPic30F4011). V em dng ngn ng C (C30) vit chng trnh. Trong chng trnh c s dng th vin chun ca Microchip cung cp (nh p30fxxx.h, p30f4011.h, dsp.h, ...). S khi chng trnh ngun c trnh by trn hnh 3.20.


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Kha Lun Tt Nghip

Modul chng trnh :

Khi to LCD

Khi To Timer

Khi To ADC

Khi To Reference signal

ref_signal x input_signal = I ref_signal_90 x input_signal=Q FIR Filter I,Q Final MAINM agnitude = I 2 +Q 2

Phase = tan 1 (Q / I )

Display LCD

Hnh 3.20. S khi chng trnh


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3.3. Cc kt qu thc nghim: 3.3.1. Mch khuych i lock-in ch to v tn hiu vo ra lock in: Mch in c thit k trn phn mm portel (xem hnh 3.21), s mch nguyn l trnh by chi tit phn ph lc

Hnh 3.21. Mch khuych i lock in


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Kha Lun Tt Nghip

Tn hiu reference thu c sau khi s dng b chuyn i DA 4bit theo kiu mng R/2R c biu din cc hnh 3.22 v 3.23. Tn hiu reference khi cha qua b lc sallen-key

Hnh 3.22. Tn hiu reference khi cha qua b lc sallen-key Tn hiu reference khi qua b lc sallen-key

Hnh 3.23. Tn hiu reference khi qua b lc sallen-key Tn hiu refrence ny s cung cp cho cm bin cn kho st. Tn s ca tn hiu reference ny c th thay i c bng cch lp trnh cho vi iu khin.


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Kha Lun Tt Nghip

Tch ca tn hiu vo v tn hiu reference c trnh by trn cc hnh 3.24 v 3.25.

Hnh 3.24. Tch hai tn hiu cng pha v lch trung bnh DC ca tn hiu thu c khi qua b lc thng thp S m phng trn hnh 3.24(s dng phn mm Micro-Cap Evaluation) cho ta thy mt php nhn gia hai tn hiu cng pha (tn hiu vo v tn hiu tham chiu(reference)). Php nhn ny cho kt qa l mt tn hiu c tn s bng hai ln tn s reference v c mc trung bnh trn mc 0(dng). Khi tn hiu ny qua b lc thng thp chng ta s thu c 1 mc DC t l vi tn hiu vo.


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Hnh 3.25. Tch hai tn hiu lch pha 900 v lch trung bnh DC ca tn hiu thu c khi qua b lc thng thp Hnh 3.25. cho thy tch gia hai tn hiu (tn hiu vo v tn hiu tham chiu (reference)) khi chng khc pha nhau 900. Vi php nhn ta thu c mt tn hiu c tn s bng hai ln tn s reference nhng mc trung bnh l bng 0. Vy khi tn hiu ny qua b lc thng thp chng ta s thu c 1 mc DC bng 0.


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Hnh 3.26 ch ra kt qu php nhn ca tn hiu reference v tn hiu vo trong thc t khi tn hiu vo c pha tp n nhiu.

a)

b)

Hnh 3.26. a) Tn hiu u vo v tn hiu tham chiu b)Tch ca chng 3.3.2.Th nghim b khuych i lock-in vi cm bin p sut MPX2300D: nh gi v kh nng o c ca b khuych i lock-in xy dng em thc hin thit k mt h o cho sensor p sut MPX2300D. 3.3.2.1. Cm bin p sut MPX2300D: - Cm bin p sut MPX2300D l mt sn phm thng mi ca cng ty Motorola. - MPX2300D chu ng c p lc t 0mmHg n 300mmHg v vi mi p lc1mmHg MPX2300D cho ta mt in th ra 1uV (1uV/mmHg). - S chn cm bin MPX2300D (xem bng 3.1) cng vi hnh dng bn ngoi S chn ca cm bin MPX2300D 1 Vs 2 S+ 3 S4 GND


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Bng 3.1. S chn cm bin MPX2300D Hnh dng bn ngoi v bn trong cm bin c biu din trn hnh 3.27a v 3.27b

a) 3.3.2.2. Kt qu th nghim:

b)

Hnh 3.27. a)Hnh dng bn ngoi MPX2300D b)Hnh dng bn trong MPX2300D

S h o th nghim lock-in s s dng cm bin p sut c trnh by nh hnh 3.28.Sensor MPX2300D Reference signal B Khuych i Lock-In

Signal Input

Tc dng p sut

Kt qa (hin th trn LCD)

Hnh 3.28. S h o cm bin MPX2300 Hnh 3.29. ch ra cch mc cho h ou vo b khuych i lock-in


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H Cng Ngh - HQG H Ni Lock-in Amlifier

Kha Lun Tt Nghip

Hnh 3.29. Cch mc h o th nghim H o thc t c trnh by trn hnh 3.30

Hnh 3.30. H o thc t Kt qa o th ca b lock-in s dng cm bin p sut MPX2300D th nghim c trnh by trn bng 3.2

p sut vo 10mmHg 15mmHg 20mmHg 25mmHg 30mmHg

Kt qu 9,8uV 14,6uV 21,3uV 24,3uV 32,1uV


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40mmHg 50mmHg

40,3uV 53,8uV

Bng 3.2. Kt qu o

Kt qa o c biu din trn cc hnh 3.31 v 3.32 V(uV)

t(ms) Hnh 3.31. Mi quan h gia tn hiu ra theo thi gian


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Hnh 3.32. Mi quan h gia p sut a vo v tn hiu ra

Kt LunKt qu thu c sau khi kha lun c thc hin: Tm hiu v cu to v nguyn tc hot ng ca b khuych i lock-in Nm vng cu trc v lp trnh tt cho vi x l dsPic30F4011. Bit cch s dng Matlab thit k mt b lc. S dng thnh tho phn mm v mch in protel v orcad Hiu r v nhng phng php bin i ADC v DAC. Xy dng c cho bn thn cch lm vic khoa hc, cch t duy c h thng khi thc hin mt kha lun. Ch to mt b khuych i lock-in v th nghim vi mt sensor p sut.

nh gi kt qu thu c v hng pht trin ca kha lun:-

C th s dng b khuych i lock-in s ch to cho nhiu th nghim vi nhiu loi sensor khc nhau. B khuych i lock-in ang cn sai s v n nh vn cha cao.

-


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-

Mch vn cha c gn gng V thi gian thc hin ti l kh ngn nn h o cha c th nghim nhiu, do nh gi cha tht khch quan. Hng pht trin tip ca ti l rt gn mch in, tng chnh xc cho h o qua c th thng mi ha h o.(C th s dng h o c nhn l b khuych i lockin cho nhng cm bin y sinh hc Bio Sensor).

Ph LcM ngun chng trnh: //---Main--#include #include #include "common.h" #include "dsp.h" #include "lcd8bit.h" #include "delay.h" #include "string.h" _FOSC(CSW_FSCM_OFF & XT_PLL16); _FWDT(WDT_OFF); _FBORPOR(PBOR_OFF & MCLR_EN); _FGS(CODE_PROT_OFF); extern FIRStruct lowpassexample_psvFilter; /*Contains filter structures for FIR-LPF*/ extern FIRStruct fir_oneFilter; extern FIRStruct fir_baFilter; extern FIRStruct fir_cuoiFilter;


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fractional i_Ptr_sig[NUMSAMP]; fractional input_I_signal[NUMSAMP]; fractional input_Q_signal[NUMSAMP]; fractional output_I_signal[NUMSAMP]; fractional output_Q_signal[NUMSAMP]; fractional* i_Ptr; unsigned int ref_input_s90; unsigned int ref_input; unsigned int doFilterFlag; int main(void) { float nhan1,nhan2,kq1,kq2,adc; float fI,fQ; float mag,phi; char sBuff[40]; TRISE = 0xFFF0; FIRDelayInit(&lowpassexample_psvFilter); FIRDelayInit(&fir_oneFilter); FIRDelayInit(&fir_baFilter); // Uart_Init(); Init_Timers(); Init_ADC(); TMR1 = 0; TMR2 = 0; TMR3 = 0; T1CONbits.TON = 1; T2CONbits.TON = 1; T3CONbits.TON = 1; while(!doFilterFlag); while (1)


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{ if (doFilterFlag) { i_Ptr =& i_Ptr_sig[0]; adc = Fract2Float(i_Ptr_sig[0]); nhan1=Fract2Float(i_Ptr_sig[0])*ref_input; nhan2=Fract2Float(i_Ptr_sig[0])*ref_input_s90; input_I_signal[0] = Float2Fract(nhan1); input_Q_signal[0] = Float2Fract(nhan2); FIR(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&fir_oneFilter); FIRDecimate(NUMSAMP,&output_I_signal[10],&input_I_signal[10],&fir_oneFilter,10); FIR(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&fir_oneFilter); FIRDecimate(NUMSAMP,&output_Q_signal[10],&input_Q_signal[10],&fir_oneFilter,1 0); FIR(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&lowpassexample_psvFilter); FIRDecimate(NUMSAMP,&output_I_signal[8],&input_I_signal[8],&lowpassexample_p svFilter,8); FIR(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&lowpassexample_psvFilter ); FIRDecimate(NUMSAMP,&output_Q_signal[8],&input_Q_signal[8],&lowpassexample_ psvFilter,8); FIRDecimate(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&fir_baFilter,2); FIRDecimate(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&fir_baFilter,2); FIR(NUMSAMP,&output_I_signal[0],&input_I_signal[0],&fir_cuoiFilter); FIR(NUMSAMP,&output_Q_signal[0],&input_Q_signal[0],&fir_cuoiFilter); fI = Fract2Float(output_I_signal[0]); fQ = Fract2Float(output_Q_signal[0]); .................................... Init_LCD();


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// //

lcd_cmd(lcd_homeL1); print_lcd(0x80,"TIN HIEU DO DUOC"); sprintf(sBuff," PHI = %8.4f ",phi); puts_lcd(sBuff,strlen(sBuff)); lcd_cmd(lcd_homeL2); sprintf(sBuff," MAG = %8.5f ",mag); puts_lcd(sBuff,strlen(sBuff));

//

RS232XMT(sBuff); doFilterFlag = 0; } } return 0;

} //---Isr_Timers--#include #include "common.h" #include "dsp.h" volatile unsigned char _sinTableIndex; extern unsigned int ref_input_s90; extern unsigned int ref_input; static unsigned char sinTable[] = {5,6,7,8,9,9,10,10,10,10,10,9,9,8,7,6,5,4,3,2,1,1,0,0 ,0,0,0,1,1,2,3,4}; static unsigned char sinTable_s90[] = {10,10,10,9,9,8,7,6,5,4,3,2,1,1,0,0,0,0,0,1,1,2,3 ,4,5,6,7,8,9,9,10,10}; void __attribute__((__interrupt__,no_auto_psv)) _T2Interrupt( void ) { _sinTableIndex++; _sinTableIndex &= 0b00011111; LATE = (sinTable[_sinTableIndex]); ref_input = (sinTable[_sinTableIndex]);


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ref_input_s90 = (sinTable_s90[_sinTableIndex]); IFS0bits.T2IF = 0; // Xoa co ngat } //--lcd-#include "p30f4011.h" #include "delay.h" #include "lcd8bit.h" void print_LCD(char a,char *s); void Init_LCD( void ); void lcd_cmd( char cmd ); void lcd_data( char data ) ; void puts_lcd( unsigned char *data, unsigned char count ); // cai dat lcd void Init_LCD( void ) { TRISB &= 0xFF00; RW_TRIS = 0; RS_TRIS = 0; E_TRIS = 0; LATB &= 0xFF00; RW = 0; RS = 0; E = 0; lcd_cmd( lcd_8bit ); lcd_cmd( lcd_normal ); lcd_cmd( lcd_on_crsr ); Delay_ms(1); } //Chuong trinh con xuat lenh o che do 8 bit void lcd_cmd( char cmd ) // RW = low // RS = low // E = low // che do giao tiep 8 bit // che do nhap du lieu binh thuong // bat mam hinh va con tro // cai dat 8 bit (RB0...RB7) la out con lai la in // cai dat RW la out // cai dat RS la out // cai dat E la out


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{ DATA &= 0xFF00; DATA |= cmd; RW = 0; RS = 0; E = 1; Nop(); Nop(); Nop(); E = 0; RS = 0; Delay_ms(10); } //Chuong trinh con xuat du lieu o che do 8 bit void lcd_data( char data ) { RW = 0; RS = 1; DATA |= data; E = 1; Nop(); Nop(); Nop(); E = 0; RS = 0; } void print_lcd(char a,char *s) // ham in ky tu tren LCD, in ky tu truc tiep // // // // chuan bi RE0 - RE7 // gui du lieu toi lcd DATA &= 0xFF00; // // E = hight // chuan bi RB0 - RB7 // gui lenh toi lcd // RW = low

Delay_ms(10); // 200uS delay


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{ lcd_cmd(a); while(*s != 0) lcd_data(*s++); } void puts_lcd( unsigned char *data, unsigned char count ) { while ( count ) { lcd_data( *data++ ); count--; } }


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Mch Nguyn L


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Ti Liu Tham Kho[1] Chip pak high volume presure sensor for disposable, backside pressure applications MPX2300D http://www.datasheetcatalog.com [2] [3] [4] [5] [6] Bentham Lockin amplifers http://www.bentham.co.uk dsPIC Language Tool Libraries http://www.microchip.com dsPIC30F Family Reference Manual http://www.microchip.com dsPIC30Fs Programmer Reference Manual http://www.microchip.com dsPic30F4011/4012 http://alldatasheet.com

[7] FilterPro MFB and Sallen Key Low-Pass Filter Design Program John Bishop, Bruce Trump, R. Mark Stitt. http://www.focus.ti.com [8] Implementing Digital http://microchip.com [9] Lock-In Amplifiers Using the dsPIC DSC

Jerry Seams R/2R LADDER NETWORKS http://www.irctt.com

[10] Low Cost, Low Power Instrumentation Amplifier http://www.analog.com [11] Microchip Inc website http://www.microchip.com [12] Sallen-Key Low-Pass Filter http://www.ecircuitcenter.com [13] The Analog Lock-in Amplifier http://www.signalrecovery.com [14] The Digital Lock-in Amplifier http://www.signalrecovery.com [15] What is a Lock-in Amplifier? http://www.signalrecovery.com [16] Wide Bandwidth Dual JFET Input Operational Amplifier www.national.com [17] www.docu-track.com [18] Tutorial 04.01, Tutorial 05.01, Tutorial 06.01 http://www.picvietnam.com


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