vhdl lab manual.pdf

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VHDL Lab Manual Dated: 19/05/2011


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FPGA DESIGN FLOW

Programmable Logic Design Flow

Design Specifications

Design Entry

Functional Simulation (Zero Delay)

RTL Model

T E S T

B E

Gate level Model N C H

Libraries (Simprims

and Unisims)Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.)

[email protected]

Target Device

Gate level

Synthesis

Libraries (Vender Specific)

Simulation

Design Constraints Area / Speed

Target Device Libraries (Vender Specific)

Design Constraints Area / Speed Gate level description using target library cells

Timing

Mapping + Simulation

Translation (Gate +

Gate level model to Interconnect

device architecture Delays)

Place and Route Placing the design in device while optimizing it for speed and area

Programming file generation Bit Stream

Download onto FPGA/ CPLD


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FPGA Design Flow for Xilinx

The Design flow followed by Xilinx devices is as shown as under:


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Xilinx FPGAs are reprogrammable and when combined with an HDL design flow can

greatly reduce the design and verification cycle.

Prepared By: Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.)

[email protected]


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Broadly the stages can be categorized as:


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1. Design Entry may have two alternatives:

a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor). b) Using

Cores(Xilinx Core Generator). 2. Functional Simulation of synthesizable HDL code (MTI

ModelSim). 3. Design Synthesis ( Xilinx project navigator). 4. Design Implementation (Xilinx

Design Manager).The stages are linked as follows:

VERILOG HDL/Verilog Code Design Entry

Functional Simulation

Synthesis

Post Synthesis Simulation

Implementation

Timing Simulation

Program onto FPGA

Design Entry

The first stage of Xilinx design flow is a design entry process. A design must be specified

by using either a schematic editor or HDL text-based tool.

Functional Simulation

Upon the finish of the design entry stage, the functional simulation of the design is being

performed, which is used to verify functionality of the design assuming no delays, whatsoever.

This assumes no target technology selection at this stage and hence assumes zero delay in

simulation.


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Complex designs must be intensively simulated, at different simulation points, during

the design flow. Simulation verifies the operation of the design before it is actually implemented

as hardware. One of the most prevalent methods for simulation is testbenching. Testbenches

(VERILOG HDL) or text fixtures (Verilog) are used to specify circuit stimuli and responses.

Roughly, simulation can be divided as functional and timing simulation. Primarily, the functional

simulation verifies that the designs specifications are correctly understood and coded. Timing

information, produced during the device implementation stage, is not available during the

functional simulation. Functional simulation can be used after synthesis, too. Comparison

between the pre- and post-synthesis simulations results checks the results of the HDL

compilers work and the HDL codes correctness. Timing simulation operates with the real

delays (results of device implementation) and is used for verification of implemented design.

Timing data are given in an .sdf file (Standard Delay Format). Xilinx supports functional and

timing simulations at different points of the design flow:

Register Transfer Level (RTL) simulation.Post-synthesis functional simulation (Pre-

NGDBuild).Post-implementation back-annotated timing simulation.

Design Synthesis

After this process, the synthesis is performed. Here for the first time in the design flow

the target technology (choice of a particular FPGA device family) is being performed. This

target technology selection will remain the same, henceforth in the design flow, upto the final

implementation stage, where finally generated Bit stream file gets downloaded onto that FPGA.

The output of the synthesis process is creation of gate level netlist. This refers to the

EDIF implementation netlist of the FPGA design. Besides the EDIF implementation netlist, the

XNF (Xilinx netlist format) netlist can be used as well.

Although the XNF is now becoming rather obsolete. The EDIF netlist is used as an input

file to the Xilinx Implementation tool and specifies how the core will be implemented. The

Electronic Design Interchange Format (EDIF) is a format used to exchange design data between

different CAD systems. In the world of FPGA design, it is used for interchange of data between

different EDA (Electronic Design Automation) software tools. EDIF files are used for FPGA

implementation only. They are the result of design synthesis and can be generated from different

design entry EDA tools: schematic or HDL design tools. EDIF files are inputs to the Xilinx

implementation tools during the translation step (NGDBuild).

Design Implementation

Design Implementation includes the following steps:

i) Translate ii) Map iii) Place and Route


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In the Translate step, which is the first step in the implementation process, EDIF

netlist must be further converted into Native Generic Database file (NGD), by means of a

program called NGDBuild. The NGD file resulting from an NGDBuild run contains the logical

description of the design that can be mapped into a targeted Xilinx FPGA device family. It is

important to stress that NGDBuild merges all available EDIF netlists from the working directory.

This is actually the step where the black-box netlist becomes merged with the rest of FPGA

design.

In the next stage, the Map stage, the NGD file is an input into a MAP program that maps

logical design to a Xilinx FPGA. The output of the MAP program is an NCD (Native Circuit

Description) file. The NCD is a physical representation of the design mapped to the components

of internal FPGA architecture.

The mapped design is ready to be placed and routed. The PAR program does this job.

The input to PAR is a mapped (not routed) NCD file, while the output is a fully routed NCD file.

Review reports are generated by the Implement Design process, such as the Map Reportor Place & Route Report, and change any of the following to improve your design:

Process propertiesConstraintsSource files Synthesis and again implementation of the

design is being made until design requirements are met.

Timing verification of the design can be made at different points in the design flow as

follows:

i) Run static timing analysis at the following points in the design flow:

After Map.After Place and Route. ii) Running Timing Simulations at the following points

in the design flow:After Map (for a partial timing analysis of CLB and IOB delays).After Place and Route

(for full timing analysis of block and net

delays).

Program onto FPGA

Programming on the Xilinx device can be made as follows:

Creation of a programming file (BIT) to program FPGA. Generate a PROM, ACE, JTAG

file for debugging or to download to

the device.Use iMPACT to program the device through programming cable. Xilinx

FPGA, as an SRAM-based programmable PLD, must be configured with the configuration

bitstream. The configuration bitstream is generated from the fully routed NCD file, by means

of a BitGen program. The output of BitGen is a binary file with the .BIT extension that can be

formatted for different PROM devices.


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EXPERIEMENT NO. 1


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Simulation using all the modeling styles and Synthesis of all the logic gates

using VHDL

AIM: Perform Zero Delay Simulation of all the logic

gates written in behavioral, dataflow and structural modeling style in VHDL using a Test

bench. Then, Synthesize each one of them on two different EDA tools.

Electronics Design Automation Tools used: i) FPGA Advantage 3.1 (includes Model Sim

simulation tool and Leonardo

Spectrum Synthesis Tool) ii) Xilinx Project Navigator 8.1 (Includes all the steps in the design

flow from

Simulation to Implementation to download onto FPGA).

Block Diagram:

A

And, Nand, Or, Nor, Xor, Xnor B

Truth table:

And Gate: Or Gate:

A B Y 0 0 0 0 1 1 1 0 1 1 1 1

Nand Gate: Nor Gate:

A B Y 0 0 1 0 1 0 1 0 0


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C

A B Y 0 0 0 0 1 0 1 0 0 1 1 1

A B Y 0 0 1 0 1 1 1 0 1 1 1 0


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1 1 0


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Xor Gate: Xnor Gate: A B Y

A B Y 0 0 0

0 0 1 0 1 1

0 1 0 1 0 1

1 0 0 1 1 0

1 1 1

Boolean Equation:

And Gate: Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B) Nor Gate: Y = (A+B) Xor Gate: Y =

A.B + A.B Xnor Gate: Y = A.B + A.B

VHDL Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):

library ieee; use ieee.std_logic_1164.all;

entity andg is

port (a,b : in std_logic;

c : out std_logic ); end andg;

architecture andg_df of andg is -- simple dataflow modeling

begin

c


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c : out std_logic ); end org;


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architecture org_df of org is -- dataflow modeling using when .... else

begin

c


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architecture nandg_beh of nandg is -- behavioral modeling using case ... end case


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begin

process(a,b)

variable v : std_logic_vector(1 downto 0); begin

v := a & b; case v is

when "00" => c c c c c


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when others => c

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