verilog introduction by iit kharagpur profs- ppts

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Embedded Systems: HDL(Lect 9)Dr. RAJIB MALLProfessor Department Of Computer Science & Engineering IIT Kharagpur.03/08/10 1

Hardware Description Languages HDL can be used to describe any digital system: For example, a computer or a component.

A digital system can be described at several levels: Switch level: wires, resistors and transistors Gate level: logic gates and flip flops Register Transfer Level (RTL): registers and the transfers of information between registers.2

Application Areas of HDLSystem Specification

HW/SW PartitionHardware Spec ASIC FPGA Boards & Systems

Suitable for all levels Behavioral level Not suitable

Softwre Spec


PLDStd Parts


Basic Limitation of HDLDescription of digital systems only


Abstraction Levels in HDLsBehavioral

RTLGate Layout (VLSI)

Our focus


Main Language Concepts (i) Concurrency



Main Language Concepts (ii) Procedural Statements


When HDL was first developed: Netlist:

Why use HDL? 1

Most logic simulators operated on netlists

Not a very convenient way to express designs, simulate, debug

List of gates and how theyre connected A natural representation of a digital logic circuit8

Why use HDL? 2 Text-based Allows simulation before building circuit Can be compiled (synthesized) into logic circuit Much easier to write test benches9

Why use HDL? 3 More abstract models of circuitsEasier to write Simulates faster

More flexible Provides sequencing A major par of Verilogs success:It allowed both the model and the testbench to be described together10

Design written in HDL Simulated to death to check functionality Synthesized (netlist generated) Static timing analysis to check timing

How HDL Is Used?


VHDL Verilog HDL

Two Major HDLs

Virtually every chip (FPGA, ASIC, etc.):

Designed in part using one of these two languages

Combines structural and behavioral modeling styles.12

V is short for Very High Speed Integrated Circuits. Designed for and sponsored by US Department of Defense. Designed by a committee (1981-1985).


Syntax based on Ada programming language. Was made an IEEE Standard in 1987.13

Verilog HDL Introduced in 1985 by Gateway Design System Corporation: Now a part of Cadence Design Systems, Inc.

Became an IEEE Standard in 1995 Syntax based on C programming language.14

Verilog Compared to VHDL VHDL Provides some high-level constructs not available in Verilog: E.g. user defined types, configurations


Provides comprehensive support for low-level digital design. Not available in native VHDL E.g. Range of type definitions and supporting functions (called packages).15

Verilog Compared to VHDL Verilog and VHDL are comparable languages VHDL has a slightly wider scope System-level modeling Fewer sources of nondeterminism (e.g., no shared variables)

VHDL is harder to simulate quickly VHDL has fewer built-in facilities for hardware modelling VHDL is a much more verbose language Most examples dont fit on slides


Design Methodology


Two Main Components of Verilog BehaviorConcurrent, event-triggered processes

Structure:Wires, interconnection, etc.18

Structural vs. Behaviorial Verilog Structural verilog:

Behavioral verilog:

Module instances and their interconnections (by wires) only.

The use of regs, explicit time

delays, arithmetic expressions, procedural assignments, and other verilog control flow structures.

Concept of Verilog Module In Verilog, the basic unit of hardware is called a module. Modules cannot contain definitions of other modules. A module can, however, instantiate another module. Allows the creation of a hierarchy in a Verilog description.20

Basic Syntax of Module Definitionmodule module_name (list_of_ports); input/output declarations local net declarations Parallel statements endmodule


Example 1 :: Simple AND gatemodule simpleand (f, x, y); input x, y; output f; assign f = x & y; endmodule


Verilog Half Addermodule half_adder_v(x, y, s, c); input x, y; output s, c; assign s = x ^ y; assign c = x & y; endmodule23

Verilog Full Addermodule full_adder_v(x, y, z, s, c); input x, y, z; Mixing structural and output s, c; behaviorial code.half_adder_v HA1(x, y, hs, hc), HA2(hs, z, s, tc); assign c = tc | hc;


module adder_4_v(B, A, C0, S, C4); input[3:0] B, A; input C0; output[3:0] S; output C4; wire[3:1] C;

Four-Bit Adder

Look at connections between adders

full_adder_v Bit0(B[0], A[0], C0, S[0], C[1]), Bit1(B[1], A[1], C[1], S[1], C[2]), Bit2(B[2], A[2], C[2], S[2], C[3]), Bit3(B[3], A[3], C[3], S[3], C4); endmodule


Behavioral Verilog// 4-bit Adder: Behavioral Verilog module adder_4_b_v(A, B, C0, S, C4); input[3:0] A, B; Mixing structural and input C0; behaviorial code. output[3:0] S; output C4; Addition (unsigned) assign {C4, S} = A + B + C0; endmodule Concatenation operation

Verilog Program Structure Program composed of modules: Each module takes parameters and returns values Let us write a Verilog program for (A NAND B) NAND (C NAND D)27

Main module Other modules

First Verilog Program module mynand(out,in1,in2); input in1,in2; output out; assign out=~(in1 & in2);

p q

o o o

endmodule m module firstprog(o,p,q,m,n); input p,q,m,n; output o; wire w1,w2; mynand nand1(p,q,w1); mynand nand2(m,n,w2); mynand nand3(w1,w2,o);




Discrete-event Simulation Basic idea: only do work when something changes Centered around an event queue Contains events labeled with the simulated time at which they are to be executed

Basic simulation paradigm Execute every event for the current simulated time Doing this changes system state and may schedule events in the future When there are no events left at the current time instance, advance simulated time to the next event in the queue29

Taste of Verilog: Structuralmodule Add_half ( sum, c_out, a, b ); input a, b; Declaration of port output sum, c_out; modes wire c_out_bar; Declaration of internalsignal Module name Module ports

Verilog keywords

xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule

Instantiation of primitive gatesa b sum

c_out_barc_out 30

Taste of Verilog: Behaviorialmodule Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign {c_out, sum} = a + b; endmodulea b c_out_bar c_out31


Module Structure Verilog program built from modules with I/O interfaces A module may contain instances of other modules A module can contain local signals, etc. Module configurations are static and all run concurrently32

Nets represent connections between things

Two Main Data Types

Do not hold their value Take their value from a driver such as a gate Cannot be assigned in an initial or always block

Regs represent data storage

Behave exactly like memory in a computer Hold their value until explicitly assigned in an initial or always block Never connected to something Can be used to model latches, flip-flops, etc., but do not correspond exactly Shared variables with all their attendant problems 33

Variables are instances of two basic families of data types: Nets and Registers Net variables e.g. wire Variable used simply to connect components together Usually corresponds to a wire in the circuit. Register variables e.g. reg Variable used to store data as part of a behavioral description Just like variables in C language.34

Data Types: Variables

Nets Can be thought as hardware wires driven by logic Equals z when unconnected Various types of nets wire wand (wired-AND) wor (wired-OR) tri (tri-state)35

Net data type Different net types supported for synthesis: wire and tri are equivalent; wire, wor, wand, tri, supply0, supply1

wor / wand

when there are multiple drivers driving them, the outputs of the drivers are shorted together. inserts an OR / AND gate at the connection.36

supply0 / supply1 model power supply connections.

NetsA Y B

wire Y; // declaration assign Y = A & B; wand Y; // declaration assign Y = A; assign Y = B; wor Y; // declaration assign Y = A; assign Y = B;


dr A


tri Y; // declaration assign Y = (dr) ? A : z;37

Register data type Different register types supported: reg, integer

The reg declaration requires explicit specification of the size. reg x, y; // single-bit register variables reg [15:0] bus; // 16-bit bus, bus[15] MSB For integer, it takes the default size, usually 32-bits. Synthesizer tries to determine the size.38

Variables that store values Do not represent real hardware but .. Only one type: reg .. real hardware can be implemented with registers reg A, C; // declaration // assignments always done inside a procedure A = 1; C = A; // C gets the logical value 1 A = 0; // C is still 1 C = 0; // C is now 0 39


Nets and Registers Wires and registers can be bits or arrays wire a; tri [15:0] dbus; // Simple wire // 16-bit tristate bus

tri #(5,4,8) b;reg [-1:4] vec;

// Wire with delay// Six-bit register

trireg (small) q;

// Wire stores a small charge

integer imem[0:1023]; // Array of 1024 integers reg [31:0] dcache[0:63];// A 32-bit memory40

Vectors Represent buseswire [3:0] busA; re