verilog hdl (behavioral modeling)
DESCRIPTION
Verilog HDL (Behavioral Modeling). Bilal Saqib. Behavioral Modeling. Structured Procedures. A module may contain multiple always statements and multiple initial statements. Each statement starts a separate control flow and starts execution at time 0. In One Module. - PowerPoint PPT PresentationTRANSCRIPT
Verilog HDLVerilog HDL(Behavioral Modeling)(Behavioral Modeling)
Bilal Saqib
Behavioral ModelingBehavioral Modeling
Structured ProceduresStructured Procedures
In One ModuleIn One Module
A module may contain multiple always statements and multiple initial statements. Each statement starts a separate control flow and starts execution at time 0.
Initial statementInitial statement
An initial statement executes only once and begins its execution at start of simulation which is at time 0.
Syntax : initial[timing_control] procedural_statement
Always statementAlways statement
An always statement executes repeatedly and also begins its execution at start of simulation which is at time 0.
Syntax : always [timing_control]
procedural_statement
where a procedural_statement is one of :procedural_assignment ( blocking or
non_blocking)procedural_continuous _assignment conditional_statementcase_statementloop_statementwait_statementdisable_statementevent_triggersequential_blockparallel_blocktask_enable (user
Procedural BlocksProcedural Blocks
Procedural Blocks are constructed from the following components.◦Procedural Assignment Statements◦High-Level Constructs
Procedural AssignmentsProcedural Assignments
Procedural Execution ControlProcedural Execution Control
Execution of Procedural Blocks can be specified in different ways◦Simple Delays: #<delay>
Specify delay before and after execution for a number of time steps.
◦Edge-Sensitive Controls: always @ (<edge><signal>) Execution occurs only at a signal edge. Optional
keywords “posedge” or “negedge” can be used to specify signal edge for execution.
NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments
NonBlocking v Blocking NonBlocking v Blocking AssignmentsAssignments
Continuous assignment vs Continuous assignment vs Procedural assignmentProcedural assignment
Procedural assignment
◦ Occurs inside an always statement or an initial statement.
◦ Execution is with respect to other statements surrounding it.
◦ Drives registers.◦ Uses “ = “ or “ < = “
assignment symbol.◦ No assign keyword
Continuous assignment
◦ Occurs within a module.◦ Executes concurrently
with other statements ; executes whenever there is a exchange of value in an operand on its right-hand side.
◦ Drives nets.◦ Uses “ = “ assignment
symbol.◦ Uses assign keyword
Block statementsBlock statements
A block statement provides a mechanism to group two or more statements to act syntactically like a single statement. There are two kinds of blocks in Verilog HDL. These are :
◦ Sequential block ( begin…end ) : Statements are executed sequentially in the given order.
◦ Parallel block ( fork … join ) : Statements in this block execute concurrently.
Sequential blockSequential block
Statements in a sequential block execute in sequence.
Syntax : begin [ : block_id { declarations} ] procedural_statement (s)end
Parallel blockParallel block
Statements in a parallel block execute in concurrently.
Syntax : fork [ : block_id { declarations} ] procedural_statement (s)join
Conditional Statements: if elseConditional Statements: if else
Conditional Statements: caseConditional Statements: case
casex and casezcasex and casez
Looping Statements: repeat
Looping Statements: while
Looping Statements: forever
Looping Statements: for
ExampleExample
module FA_Seq (A , B , Cin , Sum, Cout) ; input A , B, Cin ; output Sum, Cout ; reg Sum, Cout ; reg T1, T2, T3 ; always
@ ( A or B or Cin ) begin
Sum = ( A ^ B ) ^ Cin ;T1 = A & Cin ;T2 = B & Cin ;T3 = A & B;Cout = ( T1 | T2 ) | T3 ;
endendmodule