verilog class
TRANSCRIPT
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VerilogBasic Concept
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verilog SM 2
Verilog Module In Verilog, the basic unit of hardware is called a
module.
Modules cannot contain definitions of other modules, i.e. it is illegal to nest module.
A module can, however, be instantiated withinanother module.
Allows the higher modules to use its f unctionalitythrough its ports.
So, anytime internal implementation can be changed, without affecting the top module.
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verilog SM 3
Syntax of Modulemodule module_ name (list _of_ ports);
input/output declarations;
local net/parameter declarations;
Instances of subblock ;
Behavioral statements;
Dataflow statements;
endmodule
Note: Other than module, module_ name andendmodule, all other components are optional
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verilog SM 4
module simpleand (f, x, y);
input x, y;
output f ;
assign f = x & y;
endmodule
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verilog SM 5
Comments
Single Line Comment:// - begins with a // andends with a newline.
Multiple Line Comment:/* <write comment here> */
Identifiers
Identifier s provide user-defined names for Verilog objects.
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verilog SM 6
An identifier is any sequence of letter s, digits, and theunder score (_) symbol except that:the fir st char acter must not be a digit, and the identifier must be 1024 char acter s or less.
Verilog is case sensitive.
Examples: bus8, Bus8, b$c01...
Illegal: 8 bus, out _ a% b...
Escaped identifiers allow for any printa ble ASCII char acter to be included in
the name.
Esca ped identifier s begin with white s pace.
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verilog SM 7
The back slash (³\´) char acter leads off theidentifier, which is then terminated with whites pace. The leading back slash char acter is not
considered par t of the identifier. Examples of esca ped identifier s include: \flip-
flop, \a+ b
Esca ped identifier s are used for tr anslator s
from other CAD systems. Esca ped identifier s should not be used under
normal circumstances.
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verilog SM 8
White Space
White s pace is defined as any of the followingchar acter s: blank s, ta bs, newlines, and formfeeds.
These are ignored except for when they are found in strings.
Number represtation
There are two ty pes of number s pecification in Verilog:
Sized and Unsized.
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verilog SM 9
Sized Number s:
Syntax: <bit _ size>¶<base><value>
Examples: 3¶b101, 32¶b1, 11¶d97, 16¶h1ff...
Unsized Number s:
Syntax:¶<base><value>
Examples: ¶b101, ¶d1 Note: Here the size is simulator and machine
s pecific(must be atleast 32)
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verilog SM 10
Logic System
Verilog Logic System
0 : zero, low, f alse, logic low, ground...
1 : one, high, true, logic high, power...
X : unk nown...
Z : high impedance, unconnected, tri-state...
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verilog SM 11
Net:
wire, wor, wand, tri, triand, tri0, tri1
etc.
Register:
reg, integer, time and real.
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verilog SM 12
Nets are physical connections between different devices.
Declaring a net
wire [<r ange>] <net _var> [<, net _var>*] Wire:
must be driven by something, and cannot store a value
without being driven.
cannot be used as the lef t-hand side of an = or <= sign in an always@ block.
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verilog SM 13
are the only legal ty pe on the lef t-hand
side of an assign statement.
can only be used to model combinationallogic.
are used to connect in put and out put por ts
of a module instantiation.
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verilog SM 14
R eg:
Contain implicit stor age - unless a varia ble of this
ty pe is ex plicitly assigned/modified, it holds its previously assigned value.
Def ault value of an un-initialized reg is 'x' or
undefined.
Declaring a register:
reg [<r ange>] <reg_var> [<, reg_var>*];
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verilog SM 15
can be connected to the in put por t of a module
instantiation.
can be used as out puts within an actual module
declar ation.
is the only legal ty pe on the LHS of an always@
block = or <= sign.
is the only legal ty pe on the LHS of an initial block
= sign (used in Test Benches).
cannot be used on the LHS of an assign statement.
Can be used to create both combinational and
sequential logic.
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verilog SM 16
Integer s
Gener al purpose register used for manipulating
quantities. The def ault width is host-machine word size but
is atleast 32 bits.
Integer s have the following representation:
Eg: integer counter;
initial
counter = -1;
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verilog SM 17
R eal
Real number constant and real register data ty pes are
declared as real.
They can be s pecified in decimal notation, i.e. 3.14 or
scientific notation, i.e. 3e6.
They cannot have r ange.
Their def ault value is 0.
Eg: real delta;
initial
delta = 4e10;
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verilog SM 18
Time:
The data ty pe time can hold a s pecial simulator valuecalled simulation time which is extr acted from thesystem function $time.
Time is unsigned integer, 64 bits.
The time information can be used to help you debugsimulations.
Eg: time simulationTime;
initial
begin
simulationTime = $time;
end
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verilog SM 19
Arr ays are used to hold sever al objects of the
same ty pe(reg, integer, time, real, realtime and
vector register data ty pes). Syntax:
<dataty pe> <arr ay _var><star t _ addr>:<end_ addr>];
Eg:
integer count[1:5]; // an arr ay of 5 integer s
reg [7:0] mem[0:8]; // Arr ay of 9 mem, each mem
is 8 bit wide
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verilog SM 20
Accessing arr ay elements:
Entire element: mem[6] = 8¶b 10101010;
Limitation: Cannot access arr ay subfield or entire
arr ay at once
mem = ???; //WRO NG!!
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verilog SM 21
Vector s are used to represent multi-bit busses
Syntax: <dataty pe> [<MSB>:<LSB>]<vector_var>;
Eg:reg [7:0] MultiBitWord1; // 8-bit reg vector with MSB=7
LSB=0
wire [0:7] MultiBitWord2; // 8-bit wire vector with
MSB=0 LSB=7reg [3:0] bitslice;
reg a; // single bit vector of ten referred to as
a scalar
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verilog SM 22
R eferencing vectors
a = MultiBitWord1[3]; //a pplies the 3rd bit of
MultiBitWord1 to a
bitslice = MultiBitWord1[3:0]; //a pplies the 3-0 bits of
MultiBitWord1 to bitslice
bitslice = MultiBitWord1[3+:2]; //Star ting bit= 3; width = 2;
bitslice =MultiBitWord1[5:3]
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verilog SM 23
Memories are arr ays of vector s which are
accessed similar to hardware memories.
Syntax:reg [<MSB>:<LSB>] <memor y _var>
[<star t _ addr>:<end_ addr>];
Memories are arr ays of vector reg. Eg:
reg [7:0] r am[0:4095]; // 4096 memor y cells that
are 8 bits wide
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verilog SM 24
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verilog SM 25
By Ordered List
Signals are Connected to the Corres ponding
Por ts in the Same Order of A ppear ance in Module por t list.
By Por t Name
Signals are Ex plicitly S pecified to which por t they are connected
Order is not impor tant
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verilog SM 26
module Mux4x1 (o, in p, ctrl);
out put o; in put [3:0] in p; in put [1:0] ctrl;
wire [1:0] mid;
Mux2x1 m0 (mid[0], in p[0], in p[1], ctrl[0]);
Mux2x1 m1 (mid[1], in p[2], in p[3], ctrl[0]);
Mux2x1 m2 (o, mid[0], mid[1], ctrl[1]);
endmodule
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verilog SM 27
module Mux4x1 (o, in p, ctrl);
out put o; in put [3:0] in p; in put [1:0] ctrl;
wire [1:0] mid;Mux2x1 (.o(mid[0]), .i1(in p[0]), .i2(in p[1]),
.ctrl(ctrl[0]));
Mux2x1 (.ctrl(ctrl[0]), .i1(in p[2]), .i2(in p[3]),.o(mid[1]));
Mux2x1 (o, mid[0], mid[1], ctrl[1]);
endmodule
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verilog SM 28
Primitive logic gates (instantiations):
` and G (out, in1, in2);
` nand G (out, in1, in2);
` or G (out, in1, in2);
` nor G (out, in1, in2);
` xor G (out, in1, in2);` xnor G (out, in1, in2);
` not G (out1, in);
` buf G (out1, in);
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verilog SM 29
bufif 1 G (out, in, ctrl);
bufif0 G (out, in, ctrl);
notif 1 G (out, in, ctrl);
notif0 G (out, in, ctrl);
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verilog SM 30
For all primitive gates:
The output port must be connected to a net
(a wire). The input ports may be connected to nets or
register type variables.
They can have a single output.
An optional delay may be specified.
Logic synthesis tools ignore time delays.
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verilog SM 31
Example: Gate Implementation`timescale 1 ns / 1ns //timescale t _ unit/t _ precision
module exclusive_or (f, a, b);
input a, b;
output f ;
wire t1, t2, t3;
nand #(5) m1 (t1, a, b);
and #(5) m2 (t2, a, t1);
and #(5) m3 (t3, t1, b);
or #(5) m4 (f, t2, t3);
endmodule
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verilog SM 32
Representation: $<identifier>.
$time - retur ns the current simulation time.
$dis play - used for formatted printing like
printf in C.
$stop - stops simulation(used for debugging).
$finish ± ends/terminates simulation.
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verilog SM 33
System Tasks
$display(³..́ , arg2, arg3, ..); p much like printf(), displays formattedstring in std output when encountered
$monitor(³..́ , arg2, arg3, ..);p like $display(), but .. displays string
each time any of arg2, arg3, .. Changes
$stop;p suspends sim when encountered
$finish;p finishes sim when encountered
$fopen(³filename´);p returns file descriptor (integer); then, you canuse $fdisplay(fd, ³..´, arg2, arg3, ..); or $fmonitor(fd, ³..´, arg2, arg3, ..);to write to file
<file_handle> = $fopen(³<name_of_file>´);
$fclose(fd);p closes file
$random(seed);p returns random 32-bit integer; give her an integer as a seed
Always written inside procedures
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verilog SM 34
$display & $monitor string format
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verilog SM 35
A compiler directive is immediately preceded by
a gr ave accent (µ). µdefine - defines a compile-time constant or macro.
Eg: µdefineWOR D 32
µifdef - µelse - µendif - provide suppor t for conditional
compilation.
Eg: µifdef WOR D
Word_cal( ) ;
µendif
µinclude - simple text inclusion(include entire content of a
verilog source during compilation).
Compiler Directives
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verilog SM 36
Arithmetic: + , - , * , / , % ,**
Binar y bit-wise: ~ , & , | , ^ , ~^
Unar y reduction: & , ~& , | , ~| , ^ , ~^
Logical: ! , && , ||
Equality: == , === , != , !==
Relational: < , < , >= , <=
Logical shif t: >> , << Conditional: cond_ex pr? true_ex pr : f alse_ex pr;
Concatenation: {}
Replication: {{}}
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verilog SM 37
Oper ator s in Verilog Arithmetic: + , - , * , / , % ,**
Note: ** - Ex ponential (ex: t**y is t to the power of y)
%- Modulus (Reminder from division of two
number s) Binar y bit-wise: ~ , & , | , ^ , ~^
ex: X = 4¶b1010, Y = 4¶b1101 and Z = 4¶b10x1
then:
~X = 4¶b0101
X & Y = 4¶b1000
X|Y = 4¶b1111
X&Z = 4¶b10x0
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verilog SM 38
Oper ator s in Verilog Unar y reduction: & , ~& , | , ~| , ^ , ~^
ex: X = 4¶b1010
then
&X = 1¶b0|X = 1¶b1
^X = 1¶b0
Logical: ! , && , ||Logical oper ator s always evaluate to one bit value: 0(f alse), 1(true) and x
(ambigous)ex:A = 3 and B =0,
A&&B// evaulates to 0
A||B = 1// evaulates to 1
(A==3) && (B == 0) //evaluates to 1
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verilog SM 39
Oper ator s in Verilog Equality: == , === , != , !==
A == B Possible value 0,1, x
A != B Possible value 0,1, x
A === B Possible value 0,1(includes x and z)
A !== B Possible value 0,1
Relational: < , > , >= , <=
Logical shif t: >> , <<>> : Right Shif t
<<: Lef t Shif t
ex: X = 4¶b1100, then X>> = 4¶b0110 and X<< = 4¶b1000
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verilog SM 40
Oper ator s in Verilog Conditional: cond_ex pr? true_ex pr : f alse_ex pr;
ex:
assign 0ut = ctrl?in1:in0;
Concatenation: {}A = 1¶b1, B = 2¶b00 and C = 2¶b10
then {A,B}= 3¶b100,
{C,B, 2¶b10}= 6¶b100010
{A, B[0], C[1]} = 3¶b101
Replication: {{}}{4{A}}= 4¶b1111
{3{A},2{B}}= 7¶b1110000
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verilog SM 41
Operator Precedence
Use parentheses to
enforce your priority
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verilog SM 42
Two different styles of description:
Data flow
Continuous assignment
Behavioral
Procedural assignment
Blocking
Non-blocking
Description Styles in Verilog
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verilog SM 43
Continuous Assignment
Identified by the keyword ³assign´.
assign a = b & c;
assign f[2] = c[0];
Forms a static binding between
The µnet¶ being assigned on the LHS,
The expression on the R HS.
The assignment is continuously active. Almost exclusively used to model combinational logic.
Data-flow Style
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verilog SM 44
A Verilog module can contain any number
of continuous assignment statements.
For an ³assign´ statement, The expression on R HS may contain both
³register´ or ³net´ type variables.
The LHS must be of ³net´ type, typically a³wire´.
Data-flow Style
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verilog SM 45
assign a = b >> 1;
assign a = b << 3;
assign f = {a, b};assign f = {a, 3¶b101, b};
assign f = {x[2], y[0], a};
assign f = { 4{a} }; // replicate four times
assign f = {2¶b10, 3{2¶b01}, x};
Some Valid Statements
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verilog SM 46
// An 8-bit adder description
module parallel_ adder (sum, cout, in1, in2, cin);
input [7:0] in1, in2;input cin;
output [7:0] sum;
output cout;assign #20 {cout, sum} = in1 + in2 + cin;
endmodule
Dataflow ModellingDataflow Modelling
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verilog SM 47
module generate_ mux (data, select, out);
input [0:7] data;
input [0:2] select;output out;
assign out = data [select];
endmodule
Note: Non-constant index in expression on R HS
generates a MUX
Dataflow ModellingDataflow Modelling
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verilog SM 48
module generate_ set _of_ MUX (a, b, f, sel);
input [0:3] a, b;
input sel;output [0:3] f ;
assign f = sel ? a : b;
Endmodule
Note: Conditional operator generates a MUX
Dataflow ModellingDataflow Modelling
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verilog SM 49
Procedural AssignmentThe procedural block defines
A region of code containing sequential statements.
The statements execute in the order they are written.
Two types of procedural block s in Verilog The ³always´ block: A continuous loop that never
terminates. The ³initial´ block: Executed once at the beginning of simulation (used in Test-benches).
Behavioral Style
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verilog SM 50
A module can contain any number of ³always´block s, all of which execute concurrently.
Basic syntax of ³always´ block:
always @ (event _expression)begin
statement;
statement;
end
The @(event _expression) is required for bothcombinational and sequential logic descriptions.
Only ³reg´ type variables can be assigned within an³always´ block.
Behavioral Style: Always Block
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verilog SM 51
Example:A
lways Block // A combinational logic example
module mux21 (in1, in0, s, f );
input in1, in0, s;
output f ;reg f ;
always @ (in1 or in0 or s)
if (s)
f = in1;
elsef = in0;
endmodule
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verilog SM 52
Example:A
lways Block module simple_counter (clk, rst, count);
input clk, rst;
output count;
reg [31:0] count;always @(posedge clk )
begin
if (rst)
count = 32¶b0;else
count = count + 1;
end
endmodule
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verilog SM 53
Initial block s execute only once, at the star t of
simulation.
Block s can be a single statement or a compound statement.
A compound statement is one or more single
statements enclosed within a begin...endconstruct.
Behavioral Style: Initial Block
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verilog SM 54
Example:Initial
module shif ter_ toplevel;
reg clk, clear, shif t;
wire [7:0] data;
//Instance of shif t _register
shif t _register S1 (clk, clear, shif t, data);
initial
begin
clk = 0; clear = 0; shif t = 0;
end
always
#10 clk = !clk ;
endmodule
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verilog SM 55
Used to delay the subsequent statement by a
s pecified amount of time.
Eg:#10 clk = 1;
#10 clk = 0;
Delays
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verilog SM 56
Triggering control: @ (trigger_event)
Delays execution until trigger_event changes or
tr ansitions. The trigger_event can be a signal/ex pression or
multiple ex pressions linked using the keyword or.
It is also possible to detect for par ticular tr ansitions
by using the keywords posedge or negedge. Eg:always @(posedge CLK) q = d;
always @(i0 or i1) o = i0 & i1;
Behavioral Style: Triggering Control
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verilog SM 57
Events
@always @(signal1 or signal2 or ..)
begin
..end
always @(posedge clk) begin
..end
always @(negedge clk) begin
..end
execution trigger s ever y time any signal changes
execution trigger s ever y
time clk changes
from 0 to 1
execution trigger s ever y time clk changes
from 1 to 0
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verilog SM 58
³Initial´ Blocks
Start execution at sim time zero and finishwhen their last statement executes m odule nothing;
initial
$display(³I¶ m first´);
initial begin
#50;$display(³Really?´);
end
end m odule
Will be dis playedat sim time 0
Will be dis played
at sim time 50
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verilog SM 59
Par ameter A parameter is a constant with a name.
No size is allowed to be specified for a parameter.
The size gets decided from the constant itself (32-bits if nothing is specified).
Examples:
parameter HI = 25, LO = 5;
parameter up = 2b¶00, down = 2b¶01, steady = 2b¶10;
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verilog SM 60
Example: Par ameter // Parameterized design:: an N-bit counter
module counter (clear, clock, count);
parameter N = 7;
input clear, clock ;output [0:N] count; reg [0:N] count;
always @ (negedge clock )
if (clear)
count <= 0;
elsecount <= count + 1;
endmodule
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verilog SM 61
Parameters
m odule dff(Q, D, clk); para m eter WIDTH = 4;output [WIDTH-1:0] Q;input [WIDTH-1:0] D;input clk;
reg [WIDTH-1:0] Q; wire [WIDTH-1:0] D; wire clk;
always @(posedge clk)Q = D;
end m odule
B. Implelementation
with par ameter s
m odule top(out, in, clk);output [1:0] out;
input [3:0] in;input clk;
wire [1:0] out; wire [3:0] in; wire clk;
wire [3:0] p_in;
wire wu, wd;
assign wu = p_in[3] & p_in[2];assign wd = p_in[1] & p_in[0];
dff instA(p_in, in, clk);// WIDTH = 4, fro m declaration
dff instB(out, {wu, wd}, clk);defpara m instB.WIDTH = 2;
// We changed WIDTH for instB only
end m odule
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verilog SM 62
Sequential statements within procedural
block s (³always´ and ³initial´) can use two types of assignments:
Blocking assignment
Uses the µ=¶ operator
Non-blocking assignment
Uses the µ<=¶ operator
Blocking & Non-blocking
Assignments
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verilog SM 63
If execution of other statements is blocked af ter evaluation of right hand side of a statementuntil assignment to lef t hand side is done, it is
called blocking statement. The target of assignment gets updated before
the next sequential statement in the procedural block is executed.
A statement using blocking assignment block sthe execution of the statements following it, until it gets completed.
R ecommended style for modeling combinational logic.
Blocking Assignment (using µ=¶)
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verilog SM 64
If we use a nonblocking statements in our code, right hand side of the statements to be executed without an timing delay in between will be
evaluated first, and assigned later. Only if timing delay exists between two
nonblocking assignments, assignment to LHS of one statements will be done before evaluationR HS of another statement. I
The assignment to the target gets scheduled for the end of the simulation cycle.
Non-Blocking Assignment (using µ<=¶)
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verilog SM 65
Non-Blocking Assignment (using µ<=¶) Normally occurs at the end of the sequential
block.
Statements subsequent to the instruction under
consideration are not blocked by the assignment.
R ecommended style for modeling sequential logic.
Can be used to assign several µreg¶ type variables synchronously, under the control of a
common clock.
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verilog SM 66
DifferenceDifference
// Section 1: Blocking
statements execute
sequentially
#5 a = b; // waits 5 timeunits, evaluates and
a pplies value to a
c = d; // evaluates and
a pplies value to c
Section 2: Non-Blocking
statements execute
concurrently
#5 a <= b; // waits 5 timeunits, evaluates,
schedules a pply for end
of current time
c <= d; // evaluate,schedules a pply for end
of current time
// At end of current
time both a and c
receive their values
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verilog SM 67
always@ (posedge clk)
begin
a = b;end
always@ (posedge clk)
Begin
b=a;end
//(1)both a and b becomes
1.
always@ (posedge clk)
begin
a <= b;
end
always@ (posedge clk)
begin
b <= a;end
//(2)a becomes 1 and b
becomes 0.
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verilog SM 68
Loops Verilog supports four types of loops:
± µwhile¶ loop
± µfor¶ loop ± µforever¶ loop
± µrepeat¶ loop
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verilog SM 69
Condotional StatementsVerilog supports following conditional
statements:
If-else Case
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verilog SM 70
Procedural Statements: if
if (ex pr1)
true_ stmt1;
else if (ex pr2)
true_ stmt2;
..
else
def_ stmt;
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);output out;
input [3:0] in;
input [1:0] sel;
reg out;
wire [3:0] in;
wire [1:0] sel;
always @(in or sel)
if (sel == 0)
out = in[0];
else if (sel == 1)
out = in[1];
else if (sel == 2)out = in[2];
else
out = in[3];
endmodule
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verilog SM 71
Procedural Statements: case
case (ex pr)
item_1, .., item_ n: stmt1;
item_ n+1, .., item_m: stmt2;..
def ault: def_ stmt;
endcase
E.g. 4-to-1 mux:module mux4_1(out, in, sel);
output out;
input [3:0] in;
input [1:0] sel;
reg out;
wire [3:0] in;wire [1:0] sel;
always @(in or sel)
case (sel)
0: out = in[0];
1: out = in[1];
2: out = in[2];3: out = in[3];
endcase
endmodule
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verilog SM 75
A variable cannot appear as the target of both a blocking and a nonblocking assignment.
Following is not permissible:
value = value + 1;
value <= init;
About ³Loop´ Statements Loop bound must evaluate to a constant.
Implemented by unrolling the µfor¶ loop, and replicating the statements.
Some R ules to be Followed
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verilog SM 76
Task and Function
A function shallexecute at zerosimulation time unit.
A function cannot contain time-controlling
statements. A function cannot
ena ble a task.
A task can beexecuted anytimeduring simulation.
A task can contain time-controlling,delay statements.
A task can ena bleother task s or functions.
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verilog SM 77
Task and Function
A function shall
have at least one
in put ty pe argument and shall not have
an out put or inout
ty pe argument.
A function shall
retur n a single
value.
A task can have
zero or more
arguments of any ty pe.
A task shall not
retur n a value.
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verilog SM 78
The definition of a task is the following:task <task name>; // Notice: no list inside ()s
<argument por ts>
<declar ations>
<statements>
endtask
An invocation of a task is of the followingform:
<name of task> (<por t list>);
Task Task
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verilog SM 79
Example:Task
task conver t;
in put [7:0] temp_in;
out put [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32)
end
endtask
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verilog SM 80
Example: Calling a Task module temp_cal (temp_ a, temp_b,temp_c, temp_d);
in put [7:0] temp_ a, temp_c;
out put [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v³
always @ (temp_ a)
conver t (temp_ a, temp_b);always @ (temp_c)
conver t (temp_c, temp_d);
endmodule
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verilog SM 81
The definition of a function is the following:function <r ange or ty pe> <function name>; // Notice: no
list inside ()s
<argument por ts>
<declar ations>
<statements>
endfunction
where <range or type> is the ty pe of the results
passed back to the ex pression where the
function was called
Function
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verilog SM 82
Example: Functionfunction myfunction;
in put a, b, c, d;
begin
myfunction = ((a+ b) + (c-d));
end
endfunction
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verilog SM 84
What is test bench?
A Verilog procedural block which executes
only once. Used for simulation.
Testbench generates clock, reset, and the
required test vectors.
Verilog Test Bench
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verilog SM 85
How to W
rite Testbench? Create a dummy template
Declare inputs to the module-under-test (MUT) as³reg´, and the outputs as ³wire´
Instantiate the MUT. Initialization
Assign some k nown values to the MUT inputs.
Clock generation logic
May include several simulator directives like $display, $monitor, $dumpfile, $dumpvars, $finish.
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verilog SM 87
Example:T
est bench(Contd«.)always
#10 clk = !clk ;
initial
begin
$display (³\ttime, \tclk, \tclr, \tsf t, \tdata);$monitor (³%d, %d, %d, %d, %d´, $time,clk, reset, clear,
shif t, data);
end
initial
#400 $finish;
*****REMAINING CODE HERE ******
endmodule
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Thank You