Verilog Introduction for System Verilog

This 1 day course provides an introduction to the Verilog syntax with emphasis on the constructs

required for creation of System Verilog testbenches.

Topics Covered

• Lexical conventions

• Allowed characters

• Escaped Identifiers

• String Literals

• System Functions and Macros

• Displaying text

• Monitoring signals

• Compile time directives

• Data types

• Net types

• Variable types

• Assignment

• Race conditions

• Modules

• Ports

• Instances

• Processes

• Scheduler

• Procedural assignments

• Connecting & driving ports

• Operators

• Programming statements

• if-else

• case

• Tasks and Functions

The course provides a background to the most commonly used Verilog constructs within a System

Verilog testbench.

The course is a consistent mix of lecture and lab-exercises. Targeted quizzes and labs are designed

to reinforce the course material.

Who Should Attend

Verification engineers who are familiar with VHDL but with limited or no knowledge of the Verilog

language.

Prerequisites

None, although some knowledge of a Hardware Description Language is useful.