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  • 8/18/2019 Verilog 101

    1/2

    Experiment 1

    Source Code:

    module Exp_1(input1, input2, output1, output2);

    input input1, input2;

    output output1, output2;

    assign output1=input1&input2;

    assign output2=input1|input2;

    endmodule

    RTL View:

    Technological View:

  • 8/18/2019 Verilog 101

    2/2

    Simulation:


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