vector potential equivalent circuit based on peec inversion hao yu and lei he electrical engineering...

Vector Potential Equivalent Circuit Based on PEEC Inversion

Vector Potential Equivalent Circuit Based on PEEC Inversion

Hao Yu and Lei HeHao Yu and Lei He

Electrical Engineering Department, UCLA

http://eda.ee.ucla.edu

Partially Sponsored by NSF Career Award (0093273) , and UC-Micro fund from Analog Devices, Intel and LSI Logic

OutlineOutline

Introduction

Vector Potential Equivalent Circuit Model

VPEC Property and Sparsification

Conclusions and Future Work

Interconnect ModelInterconnect ModelInterconnect ModelInterconnect Model de facto PEEC model is expensive

Total 3,278,080 elements for 128b bus with 20 segments per line 162M storage of SPICE netlist

small surface panelssmall surface panelswith constant chargewith constant charge

thin volume filamentsthin volume filamentswith constant currentwith constant current

Accurate model needs detailed discretization of conductors

Distributed RLC circuit has coupling inductance between any two segments

Challenge of Inductance SparisificationChallenge of Inductance SparisificationChallenge of Inductance SparisificationChallenge of Inductance Sparisification

Existing passivity-guaranteed sparsification methods lack accuracy or theoretical justification Returned-loop [Shepard:TCAD’00] Shift-truncation (shell) [Krauter:ICCAD’95] K-element [Devgan:ICCAD’00] Localized VPEC [Pacelli:ICCAD’02]

Partial inductance matrix L is not diagonal dominant

Direct truncation results loss of passivity

K-Element MethodK-Element Method

1 0, | |ij ii ijj

K L K K K

K-method Observe that the inversion of L is M-matrix [Devgan:ICCAD’00]

Need to extend SPICE to simulate K-element [Ji: DAC’01]

Windowing Extract the K-elements of sub-matrices to avoid full inversion [Beattie: DATE’01]

Wire-duplication Improve the accuracy of windowing method [Zhong: ICCAD’02, DAC’03]

Inductwise Heuristic bi-section the longest wire to guarantee K as M-matrix [Chen:ICCAD’02]

Contribution of Our Paper Contribution of Our Paper

Prove that circuit matrix in VPEC model is strictly diagonal dominant and hence passive Enable various passivity preserved sparsifications

Derive inversion based VPEC model from first principles Replace inductances with effective magnetic resistances

Develop closed-form formula for effective resistances

Enable direct and faster simulation in SPICE

OutlineOutline

Introduction




VPEC circuit model

Inversion based VPEC

Accuracy comparison

Vector Potential Equations for Inductive EffectVector Potential Equations for Inductive Effect

Vector potential for filament i

( ')'

4 | ' |

zz J rA dr

r r

1 z

i ii

A d A ith Filamentith Filament

Integral equation for inductive effect

Volume IntegrationVolume Integration2 z zA J

'

2L.H.S:

R.H.S:

i i

i

t

Gauss s law

ith filamen

z z

S

zi

d A dS A

d J lI

zzA

Et

Line IntegrationLine Integration

L.H.S:

R.H.S:

i

i

ith filament

inductive drop

zi

l

zi

l

A Adl l

t t

dl E V

i

i

zi

S

zi

dS A lI

A V

t l

^ ^,

0

i jii

j N j ii ij

i i

A AAI l

R R

A V

t l

i

i

zi

S

zi

dS A lI

A V

t l

0

^

jR

ijR^

0

^

iR

VPEC model for any two filaments

iR

jR

iCg

jCg

ijCx

1in

1jn

IN i

IN j

VPEC Circuit ModelVPEC Circuit Model

^

^

0

i

i

i jij z

S

ii z

S

A AR

dS A

AR

dS A

Effective Resistances

VPEC model for two filaments

iR

jR

iCg

jCg

ijCx

1in

1jn

IN i

IN j

0

^

jR

ijR^

0

^

iR

iI

2in

ii lII ^

jI

2jn

^

j jI lI

^

^ ^,

0

i jii

j N j ii ij

i i

A AAI

R R

A V

t l


^

ii lII

Vector Potential Current Source

^ ^,

0

i jii

j N j ii ij

i i

A AAI l

R R

A V

t l


VPEC model for two filaments

iR

jR

iCg

jCg

ijCx

1in

1jn

IN i

IN j

0

^

jR

ijR^

0

^

iR

iI

2in

ii lII ^

ii VlV^

OUT i

1iL

^ ^

iiV I

jI

2jn

^

j jI lI

OU T j

jj VlV^

1jL

^ ^

jjV I

^

^ ^,

0

^

i jii

j N j ii ij

ii

A AAI

R R

AV

t

^i

i

VV

l

Vector Potential Voltage Source^

^ ^,

0

i jii

j N j ii ij

i i

A AAI

R R

A V

t l

Recap of VPEC Circuit ModelRecap of VPEC Circuit Model

Inherit resistances and capacitances from PEEC

Inductances are modeled by: Effective resistances

Controlled current/voltage sources

Unit self-inductance

Much fewer reactive elements

leads to faster SPICE simulation

Comparison with Localized VPECComparison with Localized VPEC

Our solution

^

^ ^

0

( , )i jii

ji ij

A AAI j N j i

R R

(1) It is not accurate to consider only adjacent filaments

^

^ ^

0

( 1) i jii

ji ij

A AAI j i

R R

Solution in localized VPEC [Pacelli:ICCAD’02]

^

^

0

i

i

i jij z

S

ii z

S

A AR

dS A

AR

dS A

(2) There is no efficient and closed-form formula solution to calculate effective resistances

Introduction of G-Element Introduction of G-Element ^

^ ^

0

^

(1)

(2)

i jii

j ii ij

ii

A AAI

R R

AV

t

^^^ ^^

^ ^

^ ^ ^

0

1 1 1where ,

ii ij jii

j i

ij iij i

ij i ij

IGV VG

t

G GR R R

^

^ ^

0

^

/ ///

i jii

j ii ij

ii

A t A tA tI t

R R

AV

t

^ ^

^^2

Recall: and iii i

iiji jii

j i

VlII V

l

IGV V lG

t

Closed-form Formula for Effective Resistance Closed-form Formula for Effective Resistance

Major computing effort is inversion of inductance matrix LU/Cholesky factorization GMRES/GCR iteration (with volume decomposition)

^ 2 2 1l K l LG

System equation based on G-element^^

2 iiji jii

j i

IGV V lG

t

iii i ij j

j i

IK V K V

t

System equation based on K-element^

2 1

^

0 2 1 1

1

1

( )

ijij

iii ij

i j

Rl L

Rl L L

i.e.

Inversion Based VPECInversion Based VPEC

Interconnect Analysis Based on VPECInterconnect Analysis Based on VPEC

1. Calculate PEEC elements via either formula or FastHenry/FastCap

2. Invert L matrix

3. Generate full VPEC including effective resistances, current and voltage sources.

4. Sparsify full VPEC using numerical or geometrical truncations

5. Directly simulate in SPICE

PEEC (R,L,C)

L^(-1)

Full VPEC

Sparsified VPEC

SPICE Simulation

Spice Waveform Comparison Spice Waveform Comparison

Full PEEC vs. full VPEC vs. localized VPEC

Full VPEC is as accurate as Full PEEC Localized VPEC model is not accurate

(a ) 5 -b it b u s

(b ) lo ca liz ed V P E C m o d e l

(c ) fu ll V P E C m o d e l

1 2 3 4 5

^

10R

^

12R

^

20R

^

23R

^

30R

^

34R

^

45R

^

40R ^

50R

^

30R ^

40R

^

10R ^

20R ^

50R

^

12R ^

23R ^

34R

^

45R

^

13R ^

35R

^

24R

^

14R

^

25R

^

15R

Spiral InductorSpiral Inductor

Non-bus Structure: Three-turn single layer on-chip spiral inductor

Full VPEC model is accurate and can be applied for general layout

IN P U T O U T P U T

OutlineOutline

Introduction




Property of VPEC Circuit MatrixProperty of VPEC Circuit MatrixProperty of VPEC Circuit MatrixProperty of VPEC Circuit Matrix

Main Theorem

The circuit matrix is strictly diagonal-dominant and positive-definite

G^

Corollary

The VPEC model is still passive after truncation

^ ^

0

^ ^

^ ^ ^ ^ ^

0

, 0

1/ 0

1/ 1/ (1/ ) | |

i ij

ij ij

ii i ij ij iji j i j i j

R R

G R

G R R R G

Sketch proof:

Numerical SparsificationNumerical Sparsification

1.9696 1.2091 0.1904 0.0 0.0

1.2091 2.6964 1.1044 0.0 0.0

0.0 1.1044 2.7052 1.1044 0.0

0.0 0.0 1.1044 2.6964 1.2091

0.0 0.0 0.1904 1.2091 1.9696

Example: truncation of 5-bit bus with threshold 0.09

1.9696 1.2091 0.1904 0.1371 0.1749

1.2091 2.6964 1.1044 0.1231 0.1371

0.1904 1.1044 2.7052 1.1044 0.1904

0.1371 0.1231 1.1044 2.6964 1.2091

0.1749 0.1371 0.1904 1.2091 1.9696

Drop off-diagonal elements with ratio below the threshold Larger effective resistors are less sensitive to current change

Calculate the ratio between off-diagonal elements and the diagonal

element of every row

Given the full matrixG^

Truncation ThresholdTruncation Threshold

Supply voltage is 1V VPEC runtime includes the LU inversion Full VPEC model is as accurate as full PEEC model but yet faster Increased truncation ratio leads to reduced runtime and accuracy

Models and Settings(threshold)

No. of Elements

Run-time (s) Average Volt. Diff. (V)

Standard Dev. (V)

Full PEEC 8256 281.02 0V 0V

Full VPEC 8256 36.40 -1.64e-6V 3.41e-4V

Truncated VPEC (5e-5) 7482 30.89 4.64e-6V 4.97e-4V



128-bit bus with one segment per line

Waveforms ComparisonWaveforms Comparison

Full VPEC is as accurate as full PEEC Sparsified VPEC has high accuracy for up to 35.7% sparsification

Geometry Based Sparsification - Windowed Geometry Based Sparsification - Windowed Geometry Based Sparsification - Windowed Geometry Based Sparsification - Windowed

4 -b it lo ng b u s

Windowed VPEC neighbor-window (nix , niy ) for

aligned coupling and forwarded coupling

consider only forward coupling of same wire

n ix

W ind o w e d c o u p ling w ith s ize (3 , 3 ) fo r o ne high-lighte d s e gm e nt

n iy

F u ll C o u p ling o f o ne high-lighte d s e gm e nt in 4 -b it b u s w ith 4 -s e gm e nt p e r line

For the geometry of aligned bus line

Geometry Based Sparsification - Normalized Geometry Based Sparsification - Normalized Geometry Based Sparsification - Normalized Geometry Based Sparsification - Normalized

Normalized VPEC normalized aligned coupling

N o rm a lize d C o u p ling

^0ijR

^ ^0 2 ijij RR n

n: segments number

4 -b it lo ng b u s

^

ijR

F u ll C o u p ling o f o ne high-lighte d s e gm e nt in 4 -b it b u s w ith 4 -s e gm e nt p e r line

Geometrical Sparsification ResultsGeometrical Sparsification Results

32-bit bus with 8 segment per line

Decreased window size leads to reduced runtime and accuracy

Windowed VPEC has high accuracy for window size as small as (16,2)

Normalized model is still efficient with bounded error

Models and Settings

No. of Elements

Run Time (s) Avg. Volt. Diff. (V)

Standard Dev. (V)

Full PEEC 32896 2535.48 0 0

Full VPEC (32, 8)

32896 772.89 1.00e-5 6.26e-4

Windowed (32, 2)

11392 311.22 5.97e-5 1.84e-3

Windowed (16, 2)

3488 152.57 -1.23e-4 4.56e-3

Windowed (8, 2) 2240 85.14 -2.17e-4 8.91e-3

Normalized 4224 255.36 -6.05e-4 2.96e-3

Runtime ScalingRuntime Scaling

0 200 400 600 800 1000 1200

0

2000

4000

6000

8000

10000

Full PEEC Full VPEC Sparse VPEC via (8,1) window

Ru

nti

me (

s)

Bus Line Numbers

Circuit: one segment per line for buses

The runtime grows much faster for full PEEC than for full VPEC full PEEC is 47x faster for 256-bit bus due to reduced number of reactive

elements

Sparsified VPEC reduces runtime by 1000x with bounded error for large scale interconnects

Conclusions and Future WorkConclusions and Future Work

Derived inversion based VPEC from first principle

Shown that Full VPEC has the same accuracy as full PEEC but faster

Proved that VPEC model remains passive after truncation

To work on

Fast iteration algorithms for inversion of L

Model-order-reduction for VPEC (see ICCAD’2006)

vector potential equivalent circuit based on peec inversion hao yu and lei he electrical engineering...

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