Basic Encoding Method (BEM)

Multibit Recoding Booth . . , ,

, ,

, RB Y(n-bit) , ,

VADA Lab.

Basic Encoding Method (BEM) -

4-bit

0000

0001

0010

0011

0100

0101

0110

0111

VADA Lab.

Extended Encoding Method (EEM)

BEM digits({ , 0, 1 }) , . Extended Encoding Method(EEM) . EEM Virtual MSB( ) . ( )

,

( )

,

VADA Lab.

Extended Encoding Method (EEM) -

4-bit

0000

0001

0010

0011

0100

0101

0110

0111

1001

1010

1011

1100

1101

1110

1111

VADA Lab.

Conversion

2 EEM . ,

,

8 bits

VADA Lab.

Redundant Binary (RB) Booth

RB Booth .Recoded Digit ( )= Y2i-1 + Y2i -2Y2i+1 ( Y-1=0) Receded Digit ( )= - ( Y2i-1 + Y2i -2Y2i+1) ( Y-1=0)Recoded Digit

y2i-1

y2i

y2i+1

Recoded

Digit

Operation

on X

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

+1

+1

+2

-2

-1

-1

0

0X

+1X

+1X

+2X

-2X

-1X

-1X

0X

y2i-1

y2i

y2i+1

Recoded

Digit

Operation

on X

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

-1

-1

-2

+2

+1

+1

0

0X

-1X

-1X

-2X

+2X

+1X

+1X

0X

VADA Lab.

Redundant Binary (RB) Booth

Example

carry propagation .Sign extension .4:2 compressor . area, speed power .

VADA Lab.

Block Diagram

VADA Lab.

- Area

area

1092862633

509339552760

1076095816365

200971715111647

BW

PRB

DW02_mult

bits

area(gates)

Area

sheet4

1092862633

509339552760

1076095816365

200971715111647

BW

PRB

DW02_mult

bits

gates

AREA

Sheet1

BWPRBDW02_mult

81092862633

16509339552760

241076095816365

32200971715111647

Delay

44.5931.8456.2

93.8746.63114.92

121.46864.96164.5

195.63679.48283.03

BW

PRB

DW02_mult

bits

delay(ns)

D e l a y

Sheet2

BWPRBDW02_mult

844.5931.8456.2

1693.8746.63114.92

24121.46864.96164.5

32195.63679.48283.03

power

177.8834110.6359158.9884

684.4495527.84191284.2

1312.44841218.39444226.9

2278.59242149.97526028.4

BW

PRB

DW02_mult

Bits

Power(uW)

Dissipation Power

Sheet3

BWPRBDW02_mult

8177.8834110.6359158.9884

16684.4495527.84191284.2

241312.44841218.39444226.9

322278.59242149.97526028.4

Multiplier

Bits

DW02_mult

BW

PRB

8

633

1092

862

16

2760

5093

3955

24

6365

10760

9581

32

11647

20097

17151

VADA Lab.

- Delay

area

1092862633

509339552760

1076095816365

200971715111647

BW

PRB

DW02_mult

bits

area(gates)

Area

sheet4

1092862633

509339552760

1076095816365

200971715111647

BW

PRB

DW02_mult

bits

area(gates)

AREA

Sheet1

BWPRBDW02_mult

81092862633

16509339552760

241076095816365

32200971715111647

Delay

44.5931.8456.2

93.8746.63114.92

121.46864.96164.5

195.63679.48283.03

BW

PRB

DW02_mult

bits

delay(ns)

D e l a y

sheet5

44.5931.8456.2

93.8746.63114.92

121.46864.96164.5

195.63679.48283.03

BW

PRB

DW02_mult

bits

delay(ns)

DELAY

Sheet2

BWPRBDW02_mult

844.5931.8456.2

1693.8746.63114.92

24121.46864.96164.5

32195.63679.48283.03

power

177.8834110.6359158.9884

684.4495527.84191284.2

1312.44841218.39444226.9

2278.59242149.97526028.4

BW

PRB

DW02_mult

Bits

Power(uW)

Dissipation Power

sheet6

177.8834110.6359158.9884

684.4495527.84191284.2

1312.44841218.39444226.9

2278.59242149.97526028.4

BW

PRB

DW02_mult

bits

power dissipation(uw)

POWER DISSIPATION

Sheet3

BWPRBDW02_mult

8177.8834110.6359158.9884

16684.4495527.84191284.2

241312.44841218.39444226.9

322278.59242149.97526028.4

Multiplier

Bits

DW02_mult

BW

PRB

8

56.20

44.59

31.84

16

114.92

93.87

46.63

24

164.50

121.468

64.96

32

283.03

195.636

79.48

VADA Lab.

- Power Dissipation

area

1092862633

509339552760

1076095816365

200971715111647

BW

PRB

DW02_mult

bits

area(gates)

Area

sheet4

1092862633

509339552760

1076095816365

200971715111647

BW

PRB

DW02_mult

bits

area(gates)

AREA

Sheet1

BWPRBDW02_mult

81092862633

16509339552760

241076095816365

32200971715111647

Delay

44.5931.8456.2

93.8746.63114.92

121.46864.96164.5

195.63679.48283.03

BW

PRB

DW02_mult

bits

delay(ns)

D e l a y

sheet5

44.5931.8456.2

93.8746.63114.92

121.46864.96164.5

195.63679.48283.03

BW

PRB

DW02_mult

bits

delay(ns)

DELAY

Sheet2

BWPRBDW02_mult

844.5931.8456.2

1693.8746.63114.92

24121.46864.96164.5

32195.63679.48283.03

power

177.8834110.6359158.9884

684.4495527.84191284.2

1312.44841218.39444226.9

2278.59242149.97526028.4

BW

PRB

DW02_mult

Bits

Power(uW)

Dissipation Power

sheet6

177.8834110.6359158.9884

684.4495527.84191284.2

1312.44841218.39444226.9

2278.59242149.97526028.4

BW

PRB

DW02_mult

bits

power dissipation(uw)

POWER DISSIPATION

Sheet3

BWPRBDW02_mult

8177.8834110.6359158.9884

16684.4495527.84191284.2

241312.44841218.39444226.9

322278.59242149.97526028.4

Multiplier

Bits

DW02_mult

BW

PRB

8

158.9884

177.8834

110.6359

16

1284.2

684.4495

527.8419

24

4226.9

1312.4484

1218.3944

32

6028.4

2278.5924

2149.9752

VADA Lab.

Redundant Binary , Booth . .Booth n/2 .Redundant Binary carry-propagation-free adder , . encoding , .Redundant Binary array , Wallace tree Booth . Digital Signal Processing(DSP) .

VADA Lab.

References

A. Chandrakasan and R. Brodersen, Low Power CMOS Design Kluwer Academic Publishers, 1995.J. Rabaey and M. Pedram, Ed., ow Power Design Methodologies Kluwer Academic Publishers, 1995.Proceedings of the IEEE, Special Issue on Low Power, April 1995.

VADA Lab.

Booth Multiplier , ,

VADA Lab.

Instruction Level Power AnalysisEstimate power dissipation of instruction sequences and power dissipation of a programEb : base cost of individual instructions Es : circuit state change effects

EM : the overall energy cost of a program Bi : the base cost of type i instruction Ni : the number of type i instruction Oi,j : the cost occurred when a type i instruction is followed by a type j instruction Ni,j : the number of occurrences when a type i instruction is immediately followed by a type j instruction

VADA Lab.

Instruction orderingDevelop a technique of operand swappingRecoding weight : necessary operation cost of operands

Wtotal : total recoding weight of input operand Wi : weight of individual recoded digit i in Booth Multiplier Wb : base weight of an instruction Winter : inter-operation weight of instructionsTherefore, if an operand has lower Wtotal , put it in the second input(multiplier).

VADA Lab.

RESULT

VADA Lab.

References[1] Gary K. Yeap, "Practical Low Power Digital VLSI Design", Kluwer Academic Publishers.[2] Jan M. Rabaey, Massoud Pedram, "Low Power Design Methodologies", Kluwer Academic Publishers.[3] Abdellatif Bellaouar, Mohamed I. Elmasry, "Low-Power Digital VLSI Design Circuits And Systems", Kluwer Academic Publishers.[4] Anantha P. Chandrakasan, Robert W. Brodersen, "Low Power Digital CMOS Design", Kluwer Academic Publishers.[5] Dr. Ralph Cavin, Dr. Wentai Liu, "1996 Emerging Technologies : Designing Low Power Digital Systems"[6] Muhammad S. Elrabaa, Issam S. Abu-Khater, Mohamed I. Elmasry, "Advanced Low-Power Digital Circuit Techniques", Kluwer Academic Publishers.

VADA Lab.

References[BFKea94] R. Bechade, R. Flaker, B. Kaumann, and et. al. A 32b 66 mhz 1.8W Microprocessor". In IEEE Int. Solid-State Circuit Conference, pages 208-209, 1994.[BM95] Bohr and T. Mark. Interconnect Scaling - The real limiter to high performance ULSI". In proceedings of 1995 IEEE international electron devices meeting, pages 241-242, 1995.[BSM94] L. Benini, P. Siegel, and G. De Micheli. Saving Power by Synthesizing Gated Clocks for Sequential Circuits". IEEE Design and Test of Computers, 11(4):32-41, 1994.[GH95] S. Ganguly and S. Hojat. Clock Distribution Design and Verification for PowerPC Microprocessor". In International Conference on Computer-Aided Design, page Issues in Clock Designs, 1995.[MGR96] R. Mehra, L. M. Guerra, and J. Rabaey. Low Power Architecture Synthesis and the Impact of Exploiting Locality". In Journal of VLSI Signal Processing,, 1996.