unit v: specification using verilog hdl part -a (2 marks ... 5.pdf · ec2354 – vlsi design –...

EC2354 – VLSI DESIGN – III /VI SEM ECE –PREPARED BY L.M.I.LEO JOSEPH ASST.PROF./ECE

UNIT – V: SPECIFICATION USING VERILOG HDL

PART -A (2 Marks)

1. What are identifiers?

Identifiers are names of modules, variables and other objects that we can reference in

the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the

underscore character(_) and the dollar sign($). It must be a single group of characters.

Examples: A014, a ,b, in_o, s_out

2. What are the value sets in Verilog?

Verilog supports four levels for the values needed to describe hardware referred to as

value sets.

Value levels Condition in hardware circuits

0 Logic zero, false condition

1 Logic one, true condition

X Unknown logic value

Z High impedance, floating state

3. Give the different arithmetic operators?

Operator symbol Operation performed Number of operands

Multiply Two

/ Divide Two

+ Add Two

Subtract Two

% Modulus Two

** Power (exponent) Two

4. Give the different bitwise operators.

Operator symbol Operation performed Number of operands

~ Bitwise negation One

& Bitwise and Two

| Bitwise or Two

^ Bitwise xor Two

^~ or ~^ Bitwise xnor Two

~& Bitwise nand Two

~| Bitwise nor Two

5. What are gate primitives?[AUC JUNE 2013]

Verilog supports basic logic gates as predefined primitives. Primitive logic function

keyword provide the basics for structural modeling at gate level. These primitives are

instantiated like modules except that they are predefined in verilog and do not need a


module definition. The important operations are and, nand, or,xor, xnor, and buf(non-

inverting drive buffer).

6. Give the two blocks in behavioral modeling.

An initial block executes once in the simulation and is used to set up initial conditions

and step-by-step data flow An always block executes in a loop and repeats during the

simulation.

7. What are the types of conditional statements?

No else statement

a. Syntax : if ( [expression] ) true – statement;

One else statement

b. Syntax : if ( [expression] ) true – statement; else false-statement;

Nested if-else-if

c. Syntax : if ( [expression1] ) true statement 1;else if ( [expression2] ) true-

statement 2;

d. else if ( [expression3] ) true-statement 3;else default-statement;

The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is

e. executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

8. Name the types of ports in Verilog

Types of port Keyword

Input port Input

Output port Output

Bidirectional port inout

What are the types of procedural assignments?

Blocking assignment

Non-blocking assignment

9. Give the different bitwise operators

+ (addition) - (subtraction) * (multiplication) / (division) % (modulus)

10. What does synthesis mean ?

Synthesis is a step of mapping the RTL files to convert it to the technology specific files.

11. What is metastability and list the steps to prevent it ?

Metastability is an unknown state (neither zero or one).

Metastability happens for the design violating setup or hole time requirements.

Prevention steps

By using synchronizers.

Using faster flip-flops.


12. What are concatenation and replication operation in verilog and give example.[AUC

JUNE 2011]

The concatenation operator combines two or more operands to form a larger vector.

The replication operator makes multiple copies of an item.

Example

Replication

13. What is the difference between module and instance? [AUC May 2011]

Modules are building blocks of verilog designs.

Modules are instantiated inside other modules, and each instantiation creates a unique

object from the template.

14. Write the process involved in VLSI design flow.

Design specification

Behavioral description

RTL description

Functional verification and testing

Logic synthesis

Gate level netlist

Logical verification and testing

Floor planning and automatic place and route

Physical layout

15. What is verilog HDL ?

Verilog HDL is a hardware description language that can be used to model a digital

system at many levels of abstraction ranging from the algorithmic level to switch level.

16. What is gate level modeling ?[AUC JUNE 2013]

In verilog all basic gates are available as ready modules called primitives. Each primitive

defined in terms of its inputs and outputs are called gate level modeling.

17. What is data flow modelliing ?

Data flow modeling provides the means of describing combinational circuits by their

function rather by their gate structure.

18. What is behavioral modeling ? Behavioral modeling represents digital circuits at a functional and algorithmic level.

19. What id test bench ? Test bench is a virtual environment used to verify the correctness of a design or model.

20. What is gate delay ? The signal propagation delay from any gate input to the gate output is called the gate delay.


21. What are the three types of gate delays?[AUC NOV 2011]

Rise delay , Fall delay , Turn –off delay.

22. What is rise delay ? [AUC NOV 2011]

When the output gate terminal have the transition to a 1 from another value is called rise

delay.

23. What is fall delay ? [AUC NOV 2011]

When the output gate terminal have the transition to a 0 from another value is called Fall

delay.

24. What is turn –off delay? [AUC NOV 2011]

When the output gate terminal have the transition to the high impedance value from

another value is called turn -off delay.

25. What is switch level modeling ?[AUC JUNE 2013]

Designing module such as MOS transistor ,CMOS transistor is called switch level modeling.

26. Give some primitives of switch level modeling .

nmos , pmos, cmos, pullup, pulldown ,tran ,tranif

27. What is transport delay ?[AUC MAY 2011]

Transport delay is the delay caused by the wires connecting the gates.

28. What is subprogram overloading ? [AUC MAY 2011]

Sub program is a collective name for functions, procedures and operators.

29. Write the verilog module for a half adder.[AUC NOV 2011]

module ha (a,b,s,c);

input a,b;

output s,c;

xor (s,a,b);

and(c,a,b);

endmodule

PART –B (16 MARKS)

1. Write a verilog program for 3 to 8 decoder in gate level description .[AUC JUNE

2011]

module decoder(sel,out1);

input [2:0] sel;

output reg [7:0] out1; always @(sel,out1) case (sel) 3‟b000 : out1 = 8‟b00000001; 3‟b001 : out1 = 8‟b00000010; 3‟b010 : out1 = 8‟b00000100; 3‟b011 : out1 = 8‟b00001000; 3‟b100 : out1 = 8‟b00010000; 3‟b101 : out1 = 8‟b00100000; 3‟b110 : out1 = 8‟b01000000; default : out1 = 8‟b10000000; endcase endmodule


2. Explain various features of structural level modeling.

Structural level modeling: In gate level modeling or structural level modeling, the circuit is described in terms of logic gates. Example: and, or, nand, nor, etc... The logic gates have one scalar output and multiple scalar inputs. The first terminal in the list of gate terminals is an output and the other terminals are inputs. a. Gate Primitives Verilog defines some basic logic gates as part of the language. Gate primitives used in verilog codes are NOT, AND, OR, NAND, NOR, XOR, XNOR gate. Verilog includes predefined modules that implement basic logic gates. These gates allow a circuit‟s structure to be described using gate instantiation statements of the form:

Here gate_name specifies the gate type and instance_name is an identifier, also it is

optional. Each gate may have different number of ports, the output port listed first, followed by a variable number of input ports. Example: and


3. Explain briefly about various levels of design description .[AUC APR 2013]

CIRCUIT LEVEL

Circuit level modeling is the low level of abstraction.

Verilog has the basic switches built into its constructs which can be used to build basic circuits like inverters , logic gates ,static and dynamic memories.

Gate level modeling

All basic gates are available as ready modules called primitives.

Primitives are defined in terms of its inputs and outptuts


input a,b;

output s,c;

xor (s,a,b);

and(c,a,b);

endmodule

Data flow modelling

Dataflow is the next higher level of abstraction.

All possible operations on signals and variables are represented in terms of

assignments.


Behavioral level modeling

The behavior of a design is described using procedural constructs.

They are

Initial statement : This statement executes only once.

Always statement : This statement always executes in a loop.



input a,b;

output s,c;

always @ (a or b)

begin

sum = a^b;

carry = a&b;

end

endmodule

4. Write a brief note on test bench.

A test bench supplies the signals and dumps the outputs to simulate a Verilog design (module(s)). It invokes the design under test, generates the simulation input vectors, and implements the system tasks to view/format the results of the simulation. It is never synthesized so it can use all Verilog commands.

5. Explain briefly about gate level modeling.[AUC NOV 2011]


6. Explain in detail the VLSI design flow.(May 08/May 09)

Design Specification:

In this stage, functionality, interface and overall architecture of the digital circuit to be designed is described abstractly. Once the behavioral level design description is ready, it is tested extensively with the help of a simulation tool. Behavioral Description and RTL Description:

The design at this level has to be extended with the help of known functional blocks and it is the next level of detailed description. Once again the design is tested for its functionality.RTL description that is register transfer language explains the design in the form of data flow. Functional verification and Testing:

Design descriptions are tested for their functionality at every level - behavioral, data flow and gate. This is to check whether al l the functions are carried out as expected and to rectify them. This is carried out by the simulation tool.


Logic Synthesis: The corresponding hardware realization of the circuit is carried at this level. The circuits are realized through FPGA or ASIC. Logic synthesis converts the RTL description into gate level net list. Gate level net list: A gate level net list is a description of the circuit in terms of gates and connections between them. Logic synthesis tool ensures that the gate level net list meets timing, area and power specifications. PHYSICAL DESIGN: Floor Planning: In this step, the sizes of all the functional blocks are calculated and locations are assigned. The main objective of this step is to keep the highly connected blocks physically close to each other. Blocks with I/O pins are kept close to the periphery; those which interact frequently are kept close together. Placement:

The objectives of the placement step are: · Minimize the critical net delays · Make the chip as dense as possible · Minimize the power dissipation · Minimize the interconnect congestion · Minimize the timing requirement · Minimize cross talk · Minimize the interconnect length: Routing: Once the designer has floor planned a chip and the logic cells have been placed, it is time to make the interconnections by routing the chip. There are two types of routing : Global routing and Detailed routing The goal of the global router is to provide complete instructions to the detailed router on where to route .The main objective of this step is to reduce the interconnect length and area and to reduce the delays in the critical path. Implementation: Once the placement and routing are completed, the performance specifications are computed and verified. After verification, the design of the VLSI circuit is implemented in an IC.

7. Write a note on gate primitives in Verilog HDL.(8 Marks ) Verilog HDL has the capability of gate level modeling. The following are the built in primitive gates in VErilog HDL: (i) Multiple input gates: These gates have one or more than one input with one output. Eg: or,and,nand,nor,xor,xnor Syntax: multiple input gate type <instance name>(output A,input 1, input2…….,input n)

Eg: or or1(A,B,C,D,S1,); (ii) Multiple output gates; These gates have only one input with multiple outputs. These gates can be used in an application where the output of a gate has to drive more than one load. Eg: buf,not Syntax: multiple output gate type <instance name>(input A,output 1,output2…….,ouyput n) Eg: buf buf1(A,S1, S2,S3); (iii) Tristate gates; These gates have an additional control signal. The input is driven to the output only after the activation of the control signal. Eg: bufif0, bufif1, notif0, notif1 Syntax: Tristate gate type <instance name>(input A, output B, Control C ) Eg: bufif1 buffer(A,B,C); (iv) Pull gates: These gates have only one output with no inputs. A pullup gate places logic 1 on its output and a pulldown gate places a logic 0 on its output. Syntax : pullgate name <instance name>(output variable); Eg: pullup PUP(control); The output variable Control is assigned logic 1 always. (v) MOS switches: These gate models unidirectional switches,that is data flows from input to the output and the data flow can be turned off by appropriately setting the control input. These gates are used for switch level modeling in Verilog HDL.


Eg: nmos, cmos, pmos, rcmos, Syntax: gate type<instance name>(output A, input B, Control C); Eg: nmos MOS1(Source,Drain,Gate) (vi) Bidirectional Switches: These switches are bidirectional that is data flows from both ways and there is no delay when data propagates through the switches. Eg: tran, tranif0, tranif1 Syntax: gate type<instance name>(signal A, signal B, Control C); inside an always statement constitute an always block. An always block starts at time 0, executes the statements in the always block continuously in a looping fashion. This statement is used to model a block of activity that is repeated continuously in a digital circuit. Consider a program to generate a clock signal : Eg: module clockgen(clock); output reg clock; initial clock = 1‟b0; always #5 clock = ~clock; Endmodule 8. What are the procedural assignment statements?(OR) Differentiate Blocking and Non

blocking statements. (i) Blocking Assignments:

These statements are executed in the order they are specified in a sequential block.A blocking assignment will not block execution of statements that follow in a parallel block.

The “= “ operator is used to specify blocking assignments.

Read and write operations are performed simultaneously.

Eg: # 5 reg = 1‟b0; # 5 a = 2‟b01; “a” will assigned to value 01 only after 10 time units.

(ii) Non- Blocking Assignments:

These statements are executed and processed at the same simulation time.

The “<= “ operator is used to specify the Non-blocking assignments.

Separate read and write operations are performed. A read operation is performed on

each right hand side variables and then the write operations are executed according to

the scheduled time. Eg: : # 5 reg = 1‟b0; # 5 a = 2‟b01; “a” will assigned to value 01 after 05 time units.

Application of Non- Blocking Assignments:

This is used to model several concurrent data transfer that takes place after a common event.

Separate read and write operation.

These statements eliminate the race condition in digital circuits. Eg; Consider a program for swapping the values of two registers: Case (i): using Blocking Assignments: always @(posedge clock) a =b ; always @(posedge clock)

b =a; In the above program blocking assignment is used . After the execution of first statement „b‟

value is stored in ‟ a‟ and the original value of „a‟ is lost and hence when the second statement is executed some value will be stored in „b‟. Therefore swapping is not done in this case.


Case (i): using Non-Blocking Assignments: always @(posedge clock) a <=b ; always @(posedge clock) b <=a; In the above program Non blocking assignment is used . The values of „a‟ and „b‟ is first read and then assigned as per the instruction in the program. Therefore swapping is done in this case. 9. Explain the various timing control constructs available in Verilog HDL.(AUC Dec 07) Various timing controls are available in Verilog HDL. Timing controls provide a way to specify the simulation time at which procedural statements will execute. The symbol “# “ is used to specify the delay in a Verilog program. The various methods of timing control are : (i) Delay based timing control: This timing control specifies in an expression specifies the time duration between when the statement is encountered and when the statement is executed. There are three types:

Regular delay control : This is used when a non-zero delay is specified to the left

of a procedural assignment. Eg: # 10 y =1;

Intra assignment delay control: Instead of specifying delay control to the of the

assignment , it is possible to assign delay to the right of the assignment operator. Such delay specifications alters the flow of activity in a different manner. Eg: reg x,y,z; initial begin x =0; z=0; y = # 5 x+z ; // Takes the value of x and z and evaluate x+z at zero time but assigns to y only after 5 time units.

Zero delay control : This is a method to ensure that a statement is executed last after

all the statements in that simulation time are executed. Eg; reg x,y,z; initial begin x =0; z=0; end initial begin # 0 x =1; #0 z=1; end // The statements x = 1 and z =1 will be executed last as they have a delay time as #

0. (ii). Event based timing control : An event is the change in the value on a register or a net. Events can be used to trigger execution of a statement or a block of statements. There are four types of event based timing control : Regular event control, event OR control, named event control and level sensitive timing control.


Regular event control : The @ symbol is used to specify an event control.

Statements can be executed on changes in signal value or at a positive or negative transition of the signal value. The keywords posedge and negedge are used for positive transition and negative transition respectively. Eg: q = @(posedge clock ) d;

Event OR control : This refers to transition on any of the multiple signals or events can

trigger the execution of a statement or a block of statements. Eg: always @ (rest or clock or d) begin if (reset = = 0) q = 1’b0; else q = 1’b1; elseif end

Named event control: Verilog provides the capability to declare an event and then

trigger and recognize the occurrence of that event . The event does not hold any data. Declaration by the keyword event and triggering the event by the symbol

Eg: event store data // name of the event is store data always @ (posedge clock) begin if (data packet = = 4) -> store data // event store data is called again

Level sensitive Timing Control : Verilog HDL allows the ability to wait for a certain

condition to be true before a statement or a block of statement is executed. The keyword wait is used for level sensitive constructs. Eg: always wait ( count _enable) # 20 count = count +1 // the statement count +1 will be executed only when the signal count_enable is at logic 1.

10. Write a Verilog program to simulate a 4 bit ripple carry adder by instantiating four full adders. (AUC May 09/Dec 08/May 08//Dec 07, June 2011)


VERILOG


(b)Write a Verilog program to simulate a 2-bit magnitude comparator(AUC Dec

07,APR 2013)


11. Write a verilog program for 3:8 decoder.(AUC Dec 08 ,APR 2011 ,APR 2013)


12. Explain the syntax of conditional statements in Verilog HDL with examples.(May 08)


13. Write a note on switch level modeling.(May ’08)(8 Marks)

Switch level modeling forms the bsic level of modeling digital circuits. The MOS transistor is the basic element around which a VLSI circuit is built. The switches are available as primitive in Verilog. By successive instantiation of these switches ,logic gates can be realized.

Switch modeling elements: (i) MOS switch (ii) CMOS switch (iii) Bidirectional switches (iv) Power and Ground (v) Resistive switches (vi) Pull up and pull down (i) MOS switches: These gate models unidirectional switches,that is data flows from input to the output and the data flow can be turned off by appropriately setting the control input.These gates are used for switch level modeling in Verilog HDL. Eg: nmos, pmos, Syntax: gate type<instance name>(output A, input B, Control C); Eg: nmos MOS1(Source,Drain,Gate) (ii ) CMOS Switches: A CMOS switch is formed by connecting a PMOS and NMOS switch in parallel. The input pins are connected in one side and the output pins are connected in the other. P_control turns the PMOS ON when it is in the logic state 0. N_control turns the NMOS ON when it is in the logic state 1. Syntax: gate type<instance name>( out,in,P_control,N_control); Eg: cmos MOS1(out,in,P_control,N_control)


(iii)Bidirectional Switches: These switches are bidirectional that is data flows from both ways and there is no delay when data propagates through the switches. Eg: tran, tranif0, tranif1 Syntax: gate type<instance name>(signal A, signal B, Control C); (iv)Pull gates: These gates have only one output with no inputs. A pullup gate places logic 1on its output and a pulldown gate places a logic 0 on its output. Syntax : pullgate name <instance name>(output variable); Eg: pullup PUP(control);

The output variable Control is assigned logic 1 always (v) Power and Ground : Power and ground sources are specified by the keywords supply 1 and supply 0. (vi)Resistive Switches: These switches have higher source to drain impedance than regular

switches and reduce the strength of the signal passing through them. Eg: rnmos,rpmos

14. Write a Verilog code for a priority encoder.(8 marks)[AUC APR 2013]

15. Write a verilog HDL program for the 8*1 multiplexer circuit .[AUC APR 2013]

Module mux8(a,b,c,d,e,f,g,h,sel); Input a,b,c,d,e,f,g,h; Input [2:0] sel; Output reg y; Always @(sel) Begin If(sel == 3’b000) Y=a; Else if (sel == 3’b001) Y=b;


Else if (sel == 3’b010) Y=c; Else if (sel == 3’b011) Y=d; Else if (sel == 3’b100) Y=e; Else if (sel == 3’b101) Y=f; Else if (sel == 3’b110) Y=g; Else if (sel == 3’b111) Y=h; End endmodule

unit v: specification using verilog hdl part -a (2 marks ... 5.pdf · ec2354 – vlsi design –...

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