(ultra-) wide-bandgap materials and devices: reshaping the

The Bradley Department of Electrical and Computer Engineering

College of Engineering

Blacksburg, Virginia, USA

(Ultra-) Wide-Bandgap Materials and Devices: Reshaping the Power Electronics Landscape

Dr. Yuhao Zhang

Assistant Professor

Center for Power Electronics Systems, Virginia Tech

Email: [email protected]

IEEE-EDS Santa Clara

Valley/San Francisco

Chapter June Seminar

June 16, 2019, online

• Power electronics: conversion of electric energy with solid-state electronics

Power Electronics

Center for Power Electronics Systems 1

Basic Idea of Power Electronics: Non-linear Switches


• Non-linear switch: no I and V simultaneously (no loss)

• Energy storage/filtering: add lossless element

$25 billion/year market

Power Devices are Ubiquitous in Electric Vehicles


Proceedings of the IEEE, vol. 95, no. 4, April 2007

Market Projection (US $Bn)

100

200

2011 20192015

Year

Efficient Data Center Enabled by Power Device Innovations


Market Projection (US $Bn)

100

200

2012 20222017Year

• Data center will reach 10% of the total electrical power consumption in 2020

• Power device innovation allows for the architecture innovation

• 1% efficiency improvement: 160 TWH ≈ 5 nuclear power plant

WBG Semiconductor: Superior Power Semiconductor Over Si


MV/cm4

2

2

2

43.0

1.5

1000

0

0

0 Si

SiC

GaN

eV

W/cm·K107 cm/s

0

4

High Voltage

High TemperatureHigh Voltage

High Current

High Frequency

Heat Dissipation

Source: Proceedings of the IEEE, vol. 105, no. 11, Nov. 2017 .

cm2/Vs

WBG: Lower Power Loss, Higher Efficiency, Higher Frequency


n/p type 𝑅on,𝑠𝑝 =4𝐵𝑉2

𝜀𝜇𝐸𝐵3

𝑅on,𝑠𝑝 = 𝑅on ∙ 𝐴

WBG Benefits: System Simplification & Miniaturization


Source: Cambridge Electronics Inc.

Source: Rohm

Frequency scaling-up allows

for significant reduction in

system size and weight

Source: Anker

Revolutionize the Power Electronics Manufacturing Paradigm


LTCC integrated

inductor structures Integrated PoL Converter

F. C. Lee, Q. Li, T-PE, 28 (9), 2013

WBG Devices Reduce System-level Cost


• System-level cost reduction due to reduced size, weight of magnetics and reduced system cooling;

• Reduced system loses provide savings throughout life of the system

Courtesy: Dr. V. Veliadis, PowerAmerica

Dr. Levett, Infineon

SiC

WBG Power Semiconductor Wafer Diameter & Cost


Source: Proceedings of the IEEE, vol. 105, no. 11, Nov. 2017 . Source: Journal of Physics D: Applied Physics, 51 (2018) 273001

6 inch == 150 mm 8 inch == 200mm

WBG Power Devices: GaN HEMTs and SiC MOSFETs

15 V 650 V 1200 V 1700 V 10000 V

× large chip size (cost) for high-voltage devices

√ 2DEG channel: high mobility (>1500 cm2/Vs)

√ easy for integration with driver/control IC× MOS channel: low mobility (~100 cm2/Vs)

× Difficult for integration

× Substrate resistance

√ high current capability

√ small chip size for high-voltage devices

3300 V

GaN SiC

√ high-speed switching

× more challenging thermal and E-field

management√ easier thermal management

Adoption of WBG Power Devices at a Unprecedented Speed


Significant loss reduction

Less Conversion stages

• Google’s New 48V Architecture

Tesla Model 3 Inverter with SiC Modules

(Source: Tesla & STMicroelectronics)

WBG/UWBG Power Device Research in My Group

June 12, 2020 Center for Power Electronics Systems 13

Physics

& Material

Proof-of-

concept

Device Demo

Large-area

Device &

Packaging

Robustness

& ReliabilityConverter

ApplicationDevice

Design

Processing

Technologies

Medium-voltage Vertical

GaN Devices

Ultra-wide Bandgap

Materials & DevicesApplication-oriented Device

Robustness & Prognosis

WBG/UWBG Power Device Research in My Group


Physics

& Material

Proof-of-

concept

Device Demo

Large-area

Device &

Packaging

Robustness

& ReliabilityConverter

ApplicationDevice

Design

Processing

Technologies

Medium-voltage Vertical

GaN Devices

Ultra-wide Bandgap

Materials & DevicesApplication-oriented Device

Robustness & Prognosis

Reliability & Robustness Test Conditions


Time ~

Reliability

Stress ~

Robustness

Specified

lifetime (e.g., 15 years)

Operation Conditions (e.g., f, V, I)

Acceptable

Test Time(e.g., 1000

hours)

Single Event

Field Test

(by device

users)

Qualification

(by device

manufactures)

< Device

RatingWorst Case Destruction

Limit

Thermal

Aging

Thermal

Cycling

Power

Cycling

Short

Circuit Avalanche

High Temp

Reverse Bias

High Temp

Gate BiasPackage

Failure

Device

Failure

Stress Events

Dynamic Ron

robustness

A New Switching-based Robustness Test Methodology


V & I overstress

Switching Cycling = Overstressed Stimuli + Hard Switching

• Robustness: withstand capability of out-of-SOA event

• Surge V & I in any switching due to di/dt, dv/dt, parasitics

“Switching Cycling” test on 1.2 kV SiC Power MOSFETs


Test Circuit and Hotplate

Auxiliary Equipment

• V overshoot of 1500 V, 94% of

avalanche breakdown voltage

• I overshoot of 23 A

• 250 μs period, 150 ns on time

• Characterization after every 6

hours (86.4 million cycles)

𝑬𝒙𝒑𝒆𝒓𝒊𝒎𝒆𝒏𝒕𝒂𝒍𝑻𝒆𝒔𝒕𝒃𝒆𝒅

𝑬𝒙𝒑𝒆𝒓𝒊𝒎𝒆𝒏𝒕𝒂𝒍𝑾𝒂𝒗𝒆𝒇𝒐𝒓𝒎𝒔

J. Kozak…..Y. Zhang, Applied Power Electronics Conference (APEC 2020)

Cree C2M0280120D

TO-247, 1200 V, 10 A

SiC MOSFET Degradation Mechanism #1 – Gate Oxide


Minimal change in Ron

Gate Leakage Current @ 25 oC

(Degradation and induce device failure)


Accelerated gate degradation @ 100 oC

• A new degradation mechanism independent of gate bias

• Drain leakage increase by 100-fold, avalanche BV unchanged

• Non-reversible, no further change with increased switching cycles

• For the first time reported, not report in HTRB tests

Degradation Mechanism #2 – Semiconductor Degradation



SiC MOSFET Degradation Mechanisms


- Increased leakage at higher temperature (1,000-fold higher leakage at 100 oC)

- I-V-T relations: electron hopping through defect states

Degraded Device

Good Device

J. Kozak…..Y. Zhang, International Reliability Physics Symposium (IRPS 2020)

SiC MOSFET Degradation Mechanisms (cont.)


- No degradation in body diode forward conduction -> degradation in edge termination

- Relate to the turn-off process: capacitive current discharges the depletion region in the edge

termination + overvoltage during turn-off -> higher E-field at the edge termination

- New switching-based stress profile generates new degradation in devices

J. Kozak…..Y. Zhang, under review, IEEE Trans. Power Electron.

GaN HEMTs: still open questions in conventional robustness


- Power device surge energy robustness is essential in many applications (EVs, power grids, etc.)

- Usually characterized by unclamped inductive switching (UIS) test

- Often referred to as “avalanche robustness”

DUT

V & I overstress

How do GaN HEMTs withstand surge energy (w/o avalanche)?


• No or minimal avalanche capability

Open questions

• How to withstand/dissipate surge energy?

• What determines the withstand capability?

• What is the failure/degradation mechanism

under surge energy condition?

• Surge energy is dissipated by avalanching

in device.

• Impact ionization process to accommodate

high current at breakdown voltage

• Avalanche energy (thermal-limited) is an

important JEDEC metric for power devices.

Si / SiC power MOSFETs GaN HEMTs

• Tested 4 mainstream 600/650 V E-mode GaN HEMTs (in collaboration with companies)

• A unified mother board and three daughter boards

UIS Test of GaN HEMTs – Withstand Process


R. Zhang…..Y. Zhang, International Reliability Physics Symposium (IRPS 2020)

• I: DUT on, inductor charging.

• II: DUT turn-off.

• III: Resonance between

inductor & device Coss, little

resistive energy dissipation.

• IV: Device 3rd-quad

conduction, resistive energy

dissipation via device,

inductor is dis-charged by

the power supply.

UIS Test of GaN HEMTs – Failure Waveform and Boundaries


Linear relationship between IL and

peak transient VDS (Vm):

• Drain-to-source leakage

• Gate is still functional

Company A

Device failure solely determined by

the transient peak voltage, not

surge energy, surge time, etc.

R. Zhang…..Y. Zhang, International Reliability Physics Symposium (IRPS 2020)

𝑽𝒎 = 𝑳𝑰𝑳𝟐/𝑪𝑶𝑺𝑺

UIS Test of GaN HEMTs – Failure Analysis


Company A Company B

• Emission microscopy +

cross-sectional SEM +

mix-mode TCAD

simulation

• Failure locations

consistent with peak E-

field locations

• Confirms the failure is

E-field inducted rather

than thermal limited

R. Zhang…..Y. Zhang, IEEE Trans.

Power Electron., early access, May. 2020

Surge-energy Robustness: Si/SiC MOSFETs v.s. GaN HEMTs


Si & SiC MOSFET: GaN HEMT:

Withstand process avalanching LC resonance & reverse conduction

Energy pathdissipation in device in

avalanching

little/no dissipation in withstand;

dissipation in reverse conduction

Limiting factor avalanche energy overvoltage capability

Failure mechanism thermal run-away E-field induced breakdown

R. Zhang…..Y. Zhang, IEEE Trans. Power Electron., early access, May. 2020

Is EAVA still the

best meaningful

metric for the

surge-energy

robustness of

GaN HEMTs?

What is the implementation for converter-like switching?


• In converters, the device typically undergoes

a clamped inductive switching, and the surge

energy is produced by circuit parasitics

• Designed a clamped inductive switching test

with controllable parasitic inductance

R. Zhang…..Y. Zhang, IEEE Trans. Power Electron.,

early access, May. 2020

Company A

Surge-energy failure under clamped inductive switching


• Test the device to failure

under different turn-off

current and parasitic

inductance

• Consistent failure

boundary with UIS (peak

transient voltage)

• The gate is still

functional, oscillation

continues, but due to

large drain-to-source

leakage under high

voltage, the device

ultimately fails thermally

R. Zhang…..Y. Zhang, IEEE Trans. Power Electron.,

early access, May. 2020

Summary


Physics

& Material

Proof-of-

concept Device

Demo

Large-area

Device

Manufacturing

Robustness &

ReliabilityConverter

ApplicationDevice

Design

Processing

Technologies

SiC (650-1700 V) & Lateral GaN (15-650 V)

(application at an unprecedented speed)Application-oriented

Reliability/Robustness

Vertical GaN:

New medium-voltage device beyond SiC

limit & new device designs and physics

(e.g. power FinFETs)

• Device manufacturing

• Reliability & robustness

• Fundamental material issues

• Converter applications

UWBG: fast progress, still not

competitive with SiC/GaN, far

from theoretical limit

• Distinct capabilities for PE applications?

• New processing and device technologies

• material-device-packaging co-optimization

Center for Power Electronics Systems (CPES)

• 10 Tenure-track Faculty

- Founder (Director Emeritus): Fred C. Lee

- Director: Dushan Boroyevich

- 2 NAE members, 4 IEEE fellows

• 40 Ph. D. students & 20 master students

• 15 visiting scholars (academia & industry)

• 2 campus (Blacksburg & Arlington)

• New to devices and semiconductors

31

Statistics (1978-2017)

• 26 Startup companies founded by CPES alumni

• 19 CPES alumni in academia

• $158M Research expenditures

• 185 Masters degrees awarded

• 175 Ph. D. degrees awarded

• 298 Invention disclosure & 126 patents awarded

• 275 Visiting professors and industry members

CPES Research Today

Technology Areas

Application Areas

Sustainable & Distributed

Electronic Energy

Systems

Vehicular

Power Converter

Systems

Point-of-Load

Conversion

Power Management

for Computers &

Telecommunications

watts to megawatts

Point of Load ConvertersTraction Converters Medium Voltage Converters

High Density

Integration

Modeling and

Control

EMI and

Power Quality

Power Devices &

Semiconductors

Power Conversion

Topologies and

Architectures

High-Power

High-Voltage

Converters

32

CPES Industry Consortium and Funding Growth


(ultra-) wide-bandgap materials and devices: reshaping the

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