Unit 3 – Page 1

UNIT 3: Transistor sizing in CMOS Aims and Objectives To learn how variation in the physical parameters of MOSFETs will affect circuit performance. To study the design methodology of T-sizing and its use in optimising standard cell design and the drive strength gates.

1 Introduction In Unit 2 we looked at a range of circuits, but we assigned no particular properties to each of the transistors. However, in Unit 1 we saw that even for a simple CMOS inverter, both the static and dynamic characteristics of the circuit were dependent on the transistor properties β and Vt. It is therefore clear that designers must take care to control these parameters to ensure that circuits work well. In practice, there is only a limited amount of control available to the designer. The threshold voltage cannot (or should not) be modified at will by the designer. Vt is strongly dependent on the doping of the substrate material, the thickness of the gate oxide and the potential in the substrate. The doping in the substrate and the oxide thickness are physical parameters that are determined by the process designers, hence the circuit designer is unable to modify them. The substrate potential can be varied at will by the designer, and this will influence Vt via a mechanism known as the body effect. It is unwise to tamper with the substrate potential, and for digital design the bulk connection is always shorted to VSS for NMOS and VDD for PMOS.

Recall that !"

#$%

&µ'=(

L

W

tox

ox . From this, we see that the VLSI designer has no control over the

prefactor !!"

#$$%

&µ'

ox

ox

t since the carrier mobility (µn or µp) is a fixed property of the

semiconductor (affected by process), εox is a fixed physical parameter and tox is set by process. The designer is therefore left with the two dimensional parameters, W and L. In principle both W and L can be varied at will by the chip designer, provided they stay within the design rules for the minimum size of any feature. However, the smaller L, the larger β and smaller the gate capacitance, hence the quicker the circuit, so with few exceptions designers always use the smallest possible L available in a process. For example, in a 0.1 µm process the gate length will be 0.1 µm for virtually every single transistor on the chip. To conclude, the only parameter that the circuit designer can manipulate at will is the transistor gate width, W, and much of the following discussion will deal with the effect of modifying W and making the best selection. 2 Logic threshold – static behaviour

2.1 Labelling convention Figure 1a shows the circuit for a CMOS inverter. The figures beside each transistor (10/0.5 for PMOS and 5/0.5 for NMOS) are the physical dimensions of the transistor gates in the format W/L. Sometimes you will see these parameters beside a gate symbol (Fig 1b) and often you will find that the dimension for L is omitted (Fig 1c) since it will be set to the minimum dimension of the process.

Unit 3 – Page 2

10/0.5

5/0.5

10

5

10/0.5

5/0.5

(a) (b) (c)

Figure 1. (a) an inverter with Wn = 5 µm, Wp = 10 µm and Ln = Lp = 0.5 µm, (b) the equivalent labelling for the inverter symbol and (c) the conventional shorthand.

2.2 Controlling threshold in an inverter

Recall from Unit 1 that

p

n

p

ntntpDD

th

VVV

V

!

!+

!

!++

=

1

for a CMOS inverter.

First, note that the threshold voltage is very sensitive to VDD. For this reason, considerable effort is expended in large designs in making sure VDD is the same across the whole chip. This is not as simple as you might think, but in this discussion we will assume VDD is well controlled. We will also ignore the effect of variation in Vtn or Vtp. In practice these values will vary between every transistor on a chip, but it is the job of the process manager to keep the spread in values to within acceptable tolerance. A designer should use the expected tolerance band to simulate best and worst case scenarios for a design, but we will assume Vtn or Vtp are fixed. We next consider the ratio βn/βp.

Since !!"

#$$%

&'µ=(

n

n

ox

oxn

n

L

W

t and

!!

"

#

$$

%

&'µ=(

p

p

ox

oxp

pL

W

t and Ln = Lp, we have

p

n

p

n

p

n

W

W

µ

µ=

!

!.

Typically µn = 1200 cm2/Vs and µp = 450 cm2/Vs for silicon so µn/µp ≈ 2.7. Example A circuit is designed to run from a 5 V supply. For the process concerned, Vtn = -Vtp = 0.8 V. The formula for the threshold voltage will therefore be

p

n

p

n

th

W

W

W

W

V

7.21

7.28.02.4

+

+

= .

Figure 2. shows how the threshold voltage changes with the ratio Wp/Wn. When Wp = Wn the threshold voltage is approximately 2 V. This is somewhat less than the ideal threshold voltage of VDD/2 = 2.5 V. The reason for this is that the more mobile electrons in the NMOSFET enable the NMOSFET to operate at a lower VDS than the PMOSFET for the same IDS, hence pulling VOUT (= VIN at threshold) low. The threshold voltage can be increased by increasing the width of the PMOSFET (hence Wp/Wn) so that the VDS of the PMOSFET falls. In fact, if the ratio Wp/Wn = µn/µp = 2.7, then a threshold voltage of VDD/2 is achieved.

Unit 3 – Page 3

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5 3

Wp/Wn

Vth

(V

)

Figure 2. The threshold voltage of a CMOS inverter as a function of Wp/Wn.

This trick of making the PMOSFET larger to compensate for the lower hole mobility is universally used in silicon design. However, making the PMOSFETs 2.7 times larger than the NMOSFETs leads to large circuits that occupy large areas of silicon for little extra benefit. If we examine Fig. 2 we see that the rate of change of Vth with respect to Wp/Wn is large for Wp/Wn < 1, but is smaller for Wp/Wn > 1. Because of the diminishing improvement in Vth for increasing Wp/Wn there is little reward for making Wp/Wn large. In practice, real designs use a compromise value for Wp/Wn – typically in the range 1.5 to 2.0. The adroit selection of transistor dimensions is known as T-sizing.

2.2.1 Threshold and transfer characteristics Figure 3 shows the transfer characteristics for three different values for βn/βp. As βn/βp is reduced the threshold voltage creeps up in value so that a larger input voltage is required to make the output fall.

Vin

VDD

VDD

Vout

!n/!p = 1

!n/!p > 1

!n/!p < 1

Vin

Vout

!n/!p = 1

Vth!n/!p < 1

!n/!p > 1

t1

t2

t3t

V

Figure 3. The transfer characteristic changes dramatically with βn/βp.

Figure 4. Variations in Vth change the timing characteristics of cascaded circuits.

Unit 3 – Page 4

2.2.2 Threshold and timing characteristics Figure 4 shows the effect of increasing threshold voltage on timing. The figure depicts the output transition as a function of time for three differently T-sized inverters. The timing measurements are all made at the intercept of the output traces with the optimum gate threshold voltage for a design library in which βn/βp = 1, therefore the only correct measurement of propagation (tpdud) delay is t2. If βn/βp is reduced, then the measured tpdud = t3 – e.g. tpdud increases to t3 > t2. This is because a gate with βn/βp < 1 will have a higher threshold voltage than the value that is assumed when making the measurement, so that the gate switches later than you expect. If βn/βp is increased, then the measured tpdud = t1 – e.g. tpdud decreases to t1 < t2. This is because a gate with βn/βp > 1 will have a lower threshold voltage than the value that is assumed when making the measurement, so that the gate switches earlier than you expect. In the example, the effect is so large as to give the appearance of a negative delay (but remember that all logic systems are causal or event driven, so this is an unwanted measurement anomaly). From this analysis we conclude that variation in transistor size not only affects the performance of single gates, but that it also affects the relationship between gates. The picture only becomes more complicated when we consider gates that have more transistors than an inverter and some care is taken in T-sizing all gates to ensure that they have the same switching characteristics. If this is not done, timing prediction becomes impossible hence synthesis and digital design automation is not feasible.

2.3 T-sizing compound gates

2.3.1 Introduction The T-sizing problem described in Section 2.2 is straightforward for an inverter, but becomes slightly more complex for compound gates. If we look at a NAND2 gate (Fig. 5) we see that there are two parallel PMOSFETs between VDD and Z. If one PMOSFET is OFF and the other is ON, then the pull-up strength of the gate will be the same as that of an inverter with a similarly sized PMOSFET. However, if we look at the NMOSFETS, we see that both must be on at once to pull down Z. There will be two NMOSFETs, hence two ON resistances added in series between VSS and Z. For this reason the pull-down strength of a NAND2 gate will be less than that of an inverter with a similarly sized NMOSFET. This problem is solved by T-sizing.

A

A

B

B

Z

A

A

B

B

Z

Figure 5. A NAND2 gate. Figure 6. A NOR2 gate.

Unit 3 – Page 5

2.3.2 Stacks The N-block and P-blocks of CMOS gates are often referred to as stacks. Each gate can have one or more circuit paths connecting the output to one or other of the supply rails, and the number of transistors that appears in any path is referred to as the stack depth. Examples The NAND2 gate (Fig. 5) has an N-stack depth of 2 and a P-stack depth of 1. The NOR2 gate (Fig. 6) has an N-stack depth of 1 and a P-stack depth of 2. In order to counteract the effect of deep stacks on gate transfer characteristics, it is normal to increase the size of the stacked FETs. Figure 7 shows a simplified cross section of two NMOSFETs laid out in series. Both transistors are of length L. We can easily imagine how the two transistors can be moved closer to one another so that the two gates butt up to one another to make one transistor with a length 2L.

n

p

n

poly

n

poly

n

p

poly

n

poly

L L

2L

Figure 7. Connecting two FETs in series is electrically equivalent to one FET with twice the gate length.

Since !"

#$%

&µ'=(

L

W

tox

ox , we can see that by effectively doubling L we will half β. The halving

of β is simply compensated for by doubling the width, W. Example If we want to make a NAND2 gate have the same transfer characteristic as an inverter with Wpi = 10 µm and Wni = 5 µm, then the FETs in the NAND2 gate will have Wpn = 10 µm and Wnn = 10 µm. That is to say: Wpn = SpWni and Wnn = SnWni, where Sp is the P-stack depth and Sn is the N-stack depth. This method of T-sizing is reliable and easy to use for simple, single logic function, gates, but is less straightforward to apply to compound gates. Example Figure 8 shows compound gate.

Unit 3 – Page 6

A B

C

A

C

B

D

D

Z

Figure 8. A CMOS compound gate with the function DCBAZ )..( += .

There are several paths from Z to either of the supplies. Listing the paths for P- and NMOS by referring to the input label to each FET we derive Table I. Table I. The possible paths in the circuit of Fig. 8 and their associated stack depths. The new Ws are calculated for each transistor in a path with respect to an equivalent inverter with widths Win and Wip.

PMOS paths NMOS paths Stack depth (S) New Wp New Wn A-C B-C D

B-A-D C-D

2 2 1 3 2

2Wip

2Wip Wip

3Win 2Win

Using the stack depths in Table I, it is straightforward to calculate the required transistor widths to give each path the appropriate pull-down or pull-up strength. However, this procedure generates an anomaly – NMOSFET D is required to have two different sizes. This is clearly impossible to achieve! A variety of solutions to the problem have been proposed, but the problem is not strictly tractable. Here are a few: • T-size the deepest stack first. • T-size the least deep stack first • Use sub-linear scaling – e.g. multiply by S instead of S. For the above example, these three methods would deliver the solutions in Table II. Table II. The new T- sizes for circuit in Fig. 8 using linear and sub-linear ( S ) scaling.

Method 1 Linear – deepest

stack first

Method 2 Linear – least deep

stack first

Method 3 Sub-linear (√) –

deepest stack first

N- or PMOSFET (by input label)

New Wp New Wn New Wp New Wn New Wp New Wn A B C D

2Wip

2Wip

2Wip Wip

3Win 3Win

1.5Win

3Win

2Wip

2Wip

2Wip

Wip

4Win 4Win

2Win

2Win

1.4Wip

1.4Wip

1.4Wip

Wip

1.7Win 1.7Win

1.22Win

1.7Win

Unit 3 – Page 7

Table II notes: Both the linear methods have the width of the C-input PMOSFET selected to be half the width of the A and B PMOSFETs – i.e., the T-sizing method is applied within each sub-block of the whole P-block so that each sub-block is correctly matched. However the method still produces anomalies with different paths having different pull-down or pull-up strengths. The T-sizing within sub-blocks idea is used with the sub-linear method too – e.g. for the NMOSFET of input C we have √3/√2 = 1.24. Sub-linear T-sizing can be performed using the least deep stack first method. The advantage of the sub-linear scaling method is that it reduces the spread sizes, hence characteristics between the paths. Exercise 1 Design gates with the following logic functions and T-size them to produce a table like Table II.

EDCBAZ )...( +=

DCBAZ ++= ).(

3 Fan-out and Fan-in Fan-out (FO) and Fan-in (FI) are well-established concepts that are used to determine the loading on any given node of a logic circuit. For a chip-based logic family, such as one of the 74HCMOS families, the input capacitance to the input of any gate is very similar, so FO and FI are calculated by adding up the number of inputs connected on any given circuit node. The definitions are therefore: • FO – for a gate output Z, FO is the number of gate inputs connected to Z. • FI – for a gate input A, FI is the number of gate inputs, including A, that are connected to

A. Using these definitions we can see that for any given node FI = FO – the distinction is then merely one of perspective. e.g. are we analysing how fast a gate’s output is changing in response to loading (FO), or how fast any given input is changing in response to the available share of the drive current (FI). The system is numerically simple and leads to quick estimations of timing. Because VLSI CMOS libraries can contain logic gates with different input capacitance and drive strengths the definition of FO and FI needs to be broadened to account for the different physical properties of gates. In this scheme we define relative fan-in (RFI) as measure of the capacitance on a node and relative fan-out (RFO) as a measure of the available drive strength on a node.

3.1 Drive strength If we look again at the T-sizing that we did in Section 2.3, the idea was to match the transfer characteristics of a compound gate with those of an inverter. A coincidental effect is that we also match the drive strength of the compound gate with that of the inverter. That is to say, the gate output is capable of pushing the same amount of current, determined by the IDS of the transistors, into the external load capacitance. (Note: the sub-linear T-sized device does not achieve quite the same drive strength, but this can be compensated for.)

Recall that for an output that is pulling down DDn

Ln

pdudV

Ckt

!"2

and !!"

#$$%

&'µ=(

n

n

ox

oxn

n

L

W

t

Unit 3 – Page 8

thus noxn

nox

DD

Ln

pdudW

Lt

V

Ckt

!µ"2

So, for a fixed load (CL), a gate can be made to go more quickly by increasing Wn, since all the other parameters are fixed. A similar calculation can be performed for tpddu. In conclusion, to double the drive strength, hence halve the propagation delay of a gate, all that one need do is double all the transistor widths.

3.2 Loading In CMOS the load capacitance at the output of a gate is made up from the gate capacitance of any inputs connected to the node plus any capacitance due to the interconnect between components. In practice, it is easier to separate the delay due to the intrinsic properties of gates from that due to interconnect. We will return to interconnect delay in Unit 6, but for now we will consider the properties of gates without the parasitic effect of interconnect. The input capacitance is due to the gate electrode capacitance of the NMOS and PMOSFETs into which the signal is driven. The input capacitance is estimated by treating the gate electrode as a parallel plate capacitor, thus:

ox

pnox

ox

ppox

ox

nnox

int

LWW

t

LW

t

LWC

)( +!=

!+

!= since Ln = Lp = L.

Note that as a gate has its drive strength increased by increasing Wn and Wp, then its input capacitance increases by the same ratio.

3.3 Using drive and load to calculate RFO, RFI and propagation delay It is often easier in engineering problems to perform calculations on a per unit basis. We will do this by referring our designs to the T-sizes selected for a unit inverter with: • Wn = Wni • Wp = Wpi = RiWni • Ri is the ratio Wpi/Wni = Wp/Wn

3.3.1 Scaling of input capacitance

The input capacitance of a unit inverter is therefore ox

iniox

ox

piniox

init

LRW

t

LWWC

)1()( +!=

+!= .

This value is a constant that can be used in subsequent per unit calculations for capacitance. In this per-unit scheme, all transistor sizes are specified by a scale factor F, such that: • Fn = Wn/Wni • Fp = Wp/Wpi Since Wp = RiWn, for an inverter we also have the simplification • Fp = RiWn/RiWni = Fn = F Using our new definitions for size we can calculate that for any inverter.

ini

ox

iniox

ox

pipninox

ox

pnox

in FCt

LRFW

t

LWFWF

t

LWWC =

+!=

+!=

+!=

)1()()(

For any other gate Fn ≠ Fp, but we will neglect this complication for the sake of clarity.

Unit 3 – Page 9

3.3.2 Scaling of drive strength A similar calculation can be performed for the drive strength of an inverter.

nioxn

nox

DD

Ln

pdudFW

Lt

V

Ckt

!µ"2

Since all parameters except CL and F are constants, we can write F

MCt Lpdud = , where M is a

constant with units of resistance. M is effectively a measure of the output resistance of the gate, and the MC time constant determines the gate delay. For compound gates the drive strength will depend on the stack depths and the T-sizing that has been performed to match the compound gate to the unit inverter.

3.3.3 Using the scale factor F for a multi-gate circuit Figure 9 shows three examples of inverter circuits fanning-out. For each circuit the scale factor for the driver inverter is F = Fd, and the scale factor for each load inverter is F = Fj such that the total load is

!=j

jl FF

Examples In Fig. 9a there are two identical inverters with the same scale factor Fd = Fl = 1. Assuming tpddu = tpdud, the propagation delay at the node connecting the two will be:

ini

d

Ll

pd MCF

CMFt ==

If the product MCini is known, then all other times can be calculated straightforwardly. MCini has units of seconds. For Fig 9b we have

ini

ini

d

Ll

pd MCCM

F

CMFt 4

1

4===

i.e. the propagation delay will be four times longer than for the circuit of Fig. 9a. For Fig 9c we have

ini

ini

d

Ll

pd MCCM

F

CMFt 3

2

)321(=

++==

3.3.4 Scale factor and RFO/RFI We can calculate RFO = RFI on any node directly from Fd and Fl:

• d

l

F

FRFIRFO ==

• RFOMCt inipd *=

The terms Fl and Fd can vary from gate to gate in a standard cell library, hence relative means of determining FO and FI are a requirement.

Unit 3 – Page 10

1 1 1 4 2

1

2

3

(a) (b) (c)

Figure 9. Three examples of fan-out.

3.3.5 Compound gates The picture is a little more complex for compound gates, and the stack depth of the driver gates must be taken into account. Example

12

12

12

4

4

4 4 4

8

2

2

3

2

1

4

2

6

1

2

3

2

1

4

2

A

B

C

D

Z

Figure 10. A compound gate with four inputs driven by four different gates. Similar types of gate have one of their inputs connected to the output. The gate superscript numbers are the PMOSFET sizes, and the subscript numbers are the NMOSFET sizes. The nodes are labelled A, B, C, D and Z. If we look at the circuit in Fig 10, we see that the smallest inverter has Wp = 2 and Wn = 1. We will take this to be our unit inverter. Note that Ri = 2/1 = 2. We will assign a unit propagation delay of MCini = 50 ps. To calculate Fl for the compound gate in the centre of Fig. 10 we need to consider the Wn and Wp separately: • For node A: Fl = (12+4)/(2+1) = 16/3 • For node B: Fl = (12+4)/(2+1) = 16/3 • For node C: Fl = (12+4)/(2+1) = 16/3 • For node D: Fl = (4+4)/(2+1) = 8/3 • For node Z: Fl = (2+1+2+3+6+1+4+2)/(2+1) = 21/3 = 7 We need to calculate the Fd based on our knowledge of the transistor stacks in the driving gates: • For node A: Fd = 1, since it is the unit inverter

Unit 3 – Page 11

• For node B: NAND3 is T-sized to have same drive as unit inverter (same PMOS sizes and N-stack depth = 3), so Fd = 1

• For node C: NOR2 is T-sized to have double drive strength of unit inverter (NMOS is double size and PMOS is quadrupled), so Fd = 2

• For node D: INV has twice drive strength of unit inverter, so Fd = 2 • For node Z: Fd = 2 (this can be seen by looking at the PMOSFET on the D-input that is

twice the size of the PMOSFET in the selected unit inverter (as an exercise you can compare the other inputs).

The propagation delay can then be calculated, as shown in Table III. Table III. Calculation of propagation delay.

Node Fl Fd RFO = RFI = Fl/Fd tpd (ps) A 16/3 1 16/3 266 B 16/3 1 16/2 266 C 16/3 2 8/3 133 D 8/3 2 4/3 66 Z 7 2 7/2 175

In practice the process is automated by assigning each gate a Fl for every input and a Fd so that RFO/RFI can be quickly evaluated on every node of a circuit. This leads to very rapid delay estimators implemented within design tools. Exercise 2

A B

CZ

D

A C

B D4

4

4

4

8

8

8

8

12

3

4

6

2

1

4

2

6

2

2

3

4

2

A

B

C

D

Figure 11. Circuit for Exercise 2. The connections A-A, B-B, C-C and D-D are not drawn explicitly as wires, but points with the same label should be treated as though they are connected together. Perform the calculations that were carried out for the circuit in the above example for the circuit in Fig. 11.

3.4 AND, OR, INVERT (AOI) A standard cell library format that is widely used is that of the AOI. Any CMOS function can be expressed in the form functional form

Z = F1F2…FnIij…k(input1, input2,…inputN)

Unit 3 – Page 12

where F1F2…Fn is a string of sub-functions (As = AND or Os = OR), the I implies an INVERT at the output, the ij…k is a string of numbers that specifies the number of inputs to a sub-function block and the last section in brackets is a list of the inputs. The ij…k values add up to the total number of inputs for the gate. The circuit Fig. 12a is a 6-input AOI. It has two AND sub-functions and an OR sub-function. The output of the AND functions goes into an OR function with two more gate inputs. The function is FEDCBAZ +++= .. and is equivalent to Z = AOI222(A, B, C, D, E, F).

Another example is EDCBAZ ).).(( ++= = OAI221(A, B, C, D, E). The logic symbol for this gate is shown in Fig. 12b.

A

B

C

D

Z

E

F

AND OR INVERT

AOI222

{

{{

A

BC

D

Z

E

OAI221

{{

(a) (b) Figure 12. Two examples of the AOI logic family that can be used to build a standard cell library. The advantage of the AOI gate-naming scheme is that it is textual and can therefore be parsed by automatic cell design tools.

4 Summary In this Unit we have studied the creation of standard cell libraries. We have analysed the effect of changing transistor size on the static and dynamic performance of CMOS gates. It is essential to optimise transistor size in a gate to give all gates in a library the same threshold characteristics. If this is done, then timing prediction becomes impossible. We have developed a “per-unit” method for analysing the fan-in and fan-out of logic circuit nodes. This method leads to a simple technique for estimating the propagation delay in the circuit.

5 Problems The following problems, selected from the recommended course texts, can be used as study aids. From Smith:

Chapter 2, Exercises 25, 35 From Rabaey:

Chapter 3, Exercises 13, 14 Chapter 4, Exercises 1, 2, 3, 4, 13