iccad 2017 tutorial standard cell design and optimization ... · standard cell library design and...

©2017ArmLimited

StandardCellDesignandOptimizationMethodology

forASAP7PDKXiaoqingXu,NishiShah,AndrewEvans,

SaurabhSinha,BrianClineandGregYericArmInc

[email protected]/15/2017

ICCAD2017Tutorial

©2017ArmLimited2

Outline

ASAP7PDK

StandardCellLibraryDesignandOptimization

DesignSynthesisandExploration

HowtoDownloadandUse

Summary

©2017ArmLimited3

ASAP7PDK

Predictive7nmProcessDesignKit– ArmandASU:http://asap.asu.edu/asap/

• FinFET withdiscretetransistorsizing

Transistorgeometries

• 20/54nmgatelength/pitch,27nmfinpitch.

Keydesignrules

• 18/36nmmetal-1width/pitch(two-dimensionallayoutwithEUV)

• Metalminimumtip-to-tip31nm,metalminimumtip-to-side:25nm

• Minimumhorizontaldistancebetweendiff-netactiveareas:92nm

©2017ArmLimited4

KeyImplicationsonLayoutDesign

Keydesign-ruleconstraints:• Diffusionbreak• Horizontalmetalrouting• Verticalmetalrouting• Gatecontact• Gatecutusage

©2017ArmLimited

StandardCellLibraryDesignandOptimization

©2017ArmLimited9

StandardCellArchitecture

9-Trackand7.5-Track

SCarchitecture 9-track 7.5-trackTotal#offins 12 10

#offinspertransistor 4 3

# ofmetal-1tracksforsignalrouting

8 5.5

#ofmetal-2trackforsignal routing

8 6

metal-2 andmetal-1trackoffset(nm)

0 9

©2017ArmLimited10

ExhaustiveTransistorSizing

NAND2_X1Nunder7.5-trackarchitecture

• Exhaustivetimingsimulationstochoosethebalancedrisingandfallingslew/delay

• NAND2_X1RandNAND2_X1F,rising/fallingdominatedcells

(2p,2n) (2p,3n) (3p,2n) (3p,3n)

©2017ArmLimited11

TransistorPlacement

AOI31_X2N:consistentEulerpathforpull-upandpull-downlogic

A0

A0

A1 A2

A1

A2

B0

B0

A0 A0 A1 A1 A2 A2

B0 B0

B0 B0

A0 A0

A1 A1

A2 A2

pull-up logic

pull-down logic

(A0,B0,B0,A0,A1,A2,A2,A1)

[Uehara+,DAC’1979][Maziasz+,DAC’1987]

©2017ArmLimited12

GeneralizedEulerPath

MXT2_X1N:pass-gate-basedmultiplexer

• MultigraphsforPMOS/NMOSarenolongerdual

ny

ns0

BAS0

ny

PMOS

NMOS

S0 AS0 ns0

B

S0

(S0,A,S0,ns0,B,ny)

(S0,A,ns0,S0,B,ny)

S0

A

B

ns0ns0

S0

S0

ns0

Yny

©2017ArmLimited13



• Area-compactplacementleadstoroutability issues:pinAisblocked

S0

A

B

ns0ns0

S0

S0

ns0

Yny

(S0,A,0,S0,ns0,B,0,0,ny)

(S0,A,ns0,S0,0,B,0,0,ny)PinA

©2017ArmLimited14



• Area-compactplacementleadstoroutability issues:pinAisblocked

S0

A

B

ns0ns0

S0

S0

ns0

Yny

(S0,A,0,S0,ns0,B,0,0,ny)

(S0,A,ns0,S0,0,B,0,0,ny)PinA

©2017ArmLimited15



• Adifferentarea-compactplacementsolution:pinAisaccessible

S0

A

B

ns0ns0

S0

S0

ns0

Yny

(S0,ny,0,0,S0,ns0,0,B,A)

(S0,ny,0,0,0,ns0,S0,B,A)Adifferentpath

©2017ArmLimited16



• Adifferentarea-compactplacementsolution:pinAisaccessible

S0

A

B

ns0ns0

S0

S0

ns0

Yny

(S0,ny,0,0,S0,ns0,0,B,A)

(S0,ny,0,0,0,ns0,S0,B,A)Adifferentpath

©2017ArmLimited17

CellLayoutComparisons

LATNQ_X1N

7.5-track:13poly-pitchwideNormalizedarea:97.5Singlegatediffusion

9-track:11poly-pitchwideNormalizedarea:99

Gatecutusage

©2017ArmLimited18

FO4Comparisons

Fan-out-4(FO4)forbasiclogiccells

• 9-trackcellsprovidesmallerdelaybyconsuminghigherpower/area

©2017ArmLimited20

DesignSynthesisFlow

Arm®Cortex®- M0processorfromArmDesignStartTM portal

7.5-track/9-trackminimum/alphaSClibrary

Cadence®GenusTM SynthesisSolution,v15.12&InnovusTM ImplementationSystem,v15.10

SC Library Design RTL

Logic Synthesis

Partitioning & Floorplanning

Placement & Routing

Design Closure

CadenceReferenceFlow:up-topostrouting stageEvaluationmetrics:• Frequency,Power,Leakage,WNS• TNS,Utilization,gatecountandarea

©2017ArmLimited21

ExploreStandardCellArchitecture

Totalnegativeslack(TNS)andworstnegativeslack(WNS):9-tracklibpushesthefrequency

©2017ArmLimited22

ExploreLibraryRichness- 9-tracklibraries

Totalnegativeslack(TNS)andworstnegativeslack(WNS):alphalibpushesthefrequency

©2017ArmLimited

HowtoDownload

©2017ArmLimited24

ArmDesignStart Portal

ArmDesignStart – UniversityProgram

https://developer.arm.com/products/designstart/university-program

Comingsoon!!!

©2017ArmLimited26

SizingwithOne-FinTransistor

Currentlibrariesaredesignedwithminimum2finspertransistor

• One-fintransistorhasvariationconcernsbutbenefitscelltiming/power

ResizetheSDFFQ_X1Nwithone-fintransistor

• Setuptime:11.8psà 9.6ps(18.6%),Clock-to-Qdelay:42.1psà 40.0ps(5%)

• Energydelayproduct(EDP):8.15à 7.13(10-17 J*s) (12.5%)

©2017ArmLimited27

ResearchTopicsforStandardCellDesignMethodology

Transistorsizing

• Howtoavoidbrute-forceeffortsfortransistorsizing?

• Whatisthelibrary-leveladvantageofenablingone-fintransistor?

Squeezethetrackheight

• Howfarcanyoureducethetrackheight?

• 5-trackcells– IMECatIEDM2016

Multi-rowheightcells– designanddesignautomation

• Howtoplaceandroutetransistorsacrossmultiplerows?

• Whatsetofcells(notjustflops)shouldbedesignedacrossmultiplerows?

©2017ArmLimited28

BroaderResearchTopics

AutomaticCellSynthesis

• themultigraphisnotalwaysEulerian

• the“best”transistorplacementisnotalwaysroutable

• the“best”solutioncouldbetechnology/architecture-dependent

• Automaticcellsynthesistobeatour“alpha”qualityintermsofPPA?

Technology-independentstickdiagramgeneration

• placementandroutingareco-optimizedunderlexicalcostformulation

• generatemore-than-onesolutiontobreaktechnology/architecturedependence

Design-technologyco-optimization,reliability,hardwaresecurityandacceleratordesigns

©2017ArmLimited29

ASuccessfulandPublishedExampleforAgingResearch

Layout-dependentagingbehaviors

Agingmitigationforcritical-pathtiming

• Agingmodelsw/ASAP7PDK- PekingUniversity

• Agingoptimizationwithdetailedplacement- UTDA

• Che-Lun Hsuet.al,“Layout-DependentAgingMitigationforCritical-PathTiming”atASP-DAC2018

SA↓ NBTI, HCI&PBTI↑ODS↓ NBTI, HCI&PBTI↑SPM↓ NBTI ↓

SA– LengthbetweengateandedgeofdiffusionODS– ActivetoactivespacingSPM– Polyextensionfromactive

[Ren+,IEDM’2015]

©2017ArmLimited30

Summary

Standardcelllibrarydesignandoptimizationmethodology

• Transistorsizing,placementandrouting

• Front-endandback-endviewsbuilt,testedandfreelyavailableforacademicusages

Vt options Trackheights PVT corners Cellviews

RVTLVTSLVT

7.5-track9-track

ff_typical_max_0p77v_25cff_typical_max_0p77v_m40css_typical_max_0p63v_125css_typical_max_0p63v_25ctt_typical_max_0p70v_25c

cdl,db,db-ccs-tngds2,gds2-ascii,LEF,lib,lib-ccs-tn,spice,

verilog

©2017ArmLimited31

Summary

Standardcelllibrarydesignandoptimizationmethodology

• Transistorsizing,placementandrouting

• Front-endandback-endviewsbuilt,testedandfreelyavailableforacademicusages


• Libraryarchitectureandrichnessexplorations

HowtoDownloadandUse

• ArmDesignStart portal– universityprogram

• Multipleresearchtopicsofinterestandasuccessful/publishedresearchstudyJ

Freq.(GHz)

SCarch. TNS(ps)

Power(mW)

Gatearea(um2)

1.0 7.5.track -893 2.26 1537.99-track 0 2.21 1646.9

0.7 7.5-track 0 1.29 1306.99-track 0 1.41 1463.5

iccad 2017 tutorial standard cell design and optimization ... · standard cell library design and...

Documents