Computer Science & Engineering DepartmentUniversity of California, San Diego

Transient Analysis of Power System

Chung-Kuan Cheng

January 27, 2006

Outline

Statement of the Problem Status of Simulators Solver Engine: Multigrid Review Integration Method Frequency Domain Analysis Experimental Results Conclusion

Statement of Problem

Huge RLC linear system with multiple sources

Wide spread of natural frequencies (KHz-GHz)

Many corners and many modes of operations Packaging and transmission lines Nonlinear devices

Status of the Simulator

Matrix Solvers: Multigrid, Multigraph Integration Method: Operator Splitting Frequency Domain Analysis

Matrix Solvers

Direct MethodDirect Method

LU, KLU

Basic Iterative Basic Iterative

MethodMethod Slow Convergence

Conjugate GradientConjugate Gradient Multigrid MethodMultigrid Method

MultiGrid, MultiGraphMultiGrid, MultiGraph

High

Complexity

Multigrid Review Error Components

High frequency error (More oscillatory between

neighboring nodes)

Low frequency error (Smooth between neighboring

nodes)

Basic iterative methods only efficiently reduce high

frequency error

Basic Idea of Multigrid Convert hard-to-damp low frequency error to easy-to-

damp high frequency error

Multigrid : A Hierarchy of Problems

1 3 52 4 6

A0 • X0=b0

21

43A1 • X1=b1

21A2• X2=b2

Smoothing Smoothing

Smoothing Smoothing

Gauss Elimination

Restriction

RestrictionInterpolation

Interpolation

Hierarchically, all error components smoothed efficientlyHierarchically, all error components smoothed efficiently

Geometric vs Algebraic Geometric multigrid method

Require Regular Grid Structure

Algebraic Multigrid Coarsening Relied on Matrix,

No requirement of regular grid structure Coloring scheme

Error Smoothing Operator: Gauss-Seidel Interpolation

Small residue but the error decreases very slowly. In practice, we use only coarse node at the RHS of above

formula to approximate error correction of fine node.

jij

ijiii eaea

0Ae

Convergence of Multigrid Method

RLKC network

)]()([12

)()(

)(2)]()([)()12

2

)()12

2

tVhtVlAL

htIhtI

TITlAhtUtUtV

lALT

lA

hG

h

C

htVlALT

lA

hG

h

C

00

0

0

U

I

VA

A

G

I

V

L

C Tl

lSystem Equation:

0

)()(

)(

)2

2

)(

)(2

2 tUhtU

tI

Vt

h

LA

A

Gh

C

htI

htV

h

LA

A

Gh

C Tl

l

Tl

l

Apply Trapezoidal Rule:

The LHS matrix is not S.P.D, but can be converted to S.P.D matrix

The LHS matrix of first equation is now S.P.D. Similar for B.E and F.E

L-1 is called K / Susceptance / Reluctance Matrix

Experimental Results (1)

chip

board

Power Supply

IBM Test Case Board / Packaging / Chip Power Network Fully coupled packaging inductance 60k elements, 5000 nodes. Spice failed

Our tool Less than 10 minutes

Experimental Results (2) Power/Clock network case from OEA Tech.

30k nodes, 1000 transistor devices HSPICE/Spice run more than 2 days on our 400M Solaris

machine (Sun Blade 100) Our Run time: 1.5 hour

Integration Method:Operator Splitting

ADI: Two way partitions. Working on time steps.

Operator Splitting: Multiway Partitioning. Research + Development.

Operator Splitting- A Simple Example

uLu

t

where L is a linear/nonlinear operator and can be written as a linear sum of m subfunctions of u

Initial value problem (IVP) of ordinary differential equation (ODE)

1 2 mLu L u L u L u Suppose are updating operators on u from time step n to n+1 for each of the subfunctions, the operator splitting method has the form of:

(1/ )1

(2 / ) (1/ )2

1 ( 1) /

( , / )

( , / )

( , / )

n m n

n m n m

n n m mm

u U u h m

u U u h m

u U u h m

1 2, , , mU U U

1 ( , )n nu U u h

General Operator Splitting on Circuit Simulation

We generalize the operator splitting to graph based modeling

No geometry or locality constrains Convergence

A-stable: independent of time step size Consistence : local truncation error

Spice Formulation - Forward Euler

)()(

)(

)(

)(

0

0tU

tI

tV

Rh

LA

AGh

C

htI

htV

h

Lh

C T

Forward Euler Formulation

where : capactiance matrix : inductance matrix

: resistance matrix : conductance matrix

: incidence matrix : time step

C L

R G

A h

Circuit Equation for RLC circuits:

htItIhtIhtVtVhtV )()()(,)()()(..

Spice Formulation – Backward Euler

)()(

)(

0

0

)(

)(htU

tI

tV

h

Lh

C

htI

htV

Rh

LA

AGh

C T

Backward Euler Formulation

where : capactiance matrix : inductance matrix

: resistance matrix : conductance matrix

: incidence matrix : time step

C L

R G

A h

Circuit Equation for RLC circuits:

hhtItIhtIhhtVtVhtV )()()(,)()()(..

Splitting FormulationSplit the circuit resistor branches into two partitions, we have

1 2

1 2

1 2

A A A

G G G

R R R

Each partition has a full-version of capacitors and inductors.

Splitting Formulation

1 221 2

221 2

1 2

2 122 1

22 12 1

2 2( ) ( )

( )2 2( ) ( )

2 2( )( )

(2 2 ( )( )

T Th

hh

T Th

h

C CA AV t V tG GU th hL LI t I tR RA Ah h

C CA A V tV t hG GU t hh hL L I tI t hR RA Ah h

)

General Operator Splitting Iteration:

Alternate Backward and forward integration on partitions

Circuit Splitting: Splitting Algorithm Objective

Minimize the overall nonzero fill-ins Guarantee DC path for every nodes Hint:

Tree structure generate no nonzero fill-ins in LU factorization. High Degree nodes generates more nonzero fill-ins during LU

factorization

Linear Circuits (talk about circuits with transistors later) Bipartition of neighbors for each node Basic idea

In the LU decomposition process, non-zero fill-in will be introduced among neighbors of the pivot. Reduce the number of neighbors for all nodes will be beneficial to decrease the number of non-zero fill-ins.

Avoid loop, make tree structure as much as possible

Check DC path, reassign partition if necessary

Experimental Results-1 Power Network & Gate Sinks

Examples Circuit1 Circuit2 Circuit3 Circuit4

# Nodes 11,203 41,321 92,360 160,657

# Transistors 74 513 1,108 2,130

Simulation Period

10ns 10ns 10ns 10ns

SPICE3(sec) 602.44 8268.92 39612.32 N/A

Operator Splitting

74.64 305.38 681.18 1356.21

Speedup 8.1x 27.1x 58.2x N/A

Voltage Drop of Circuit3

Experimental Results-2 RLC Power/Clock network case.

29110 nodes, 720 transistor devices Spice3 Runtime: 12015 sec. Our Run time: 649.5 sec. 18.5x

Experimental Result-3

Two 1K and 10K cell designs

# of Nodes # of transistor Spice3 runtime(s)

Our runtime (s)

Speedup

1k Cell 10,200 6,500 2121 415.9(s) 5.1x

10k Cell 123,600 69,000 44293 3954.7(s) 11.2x

Bottle neck:Nonzero fill-insDevice Evaluation Time

Large Power Ground Network

600,000 nodes Irregular RC network 10ns Transient Simulation: 4083sec

Frequency Domain Analysis

Natural Frequency Extraction Complex Matrix Solver

Fast Fourier Transformation

ConclusionTransient of Power Analysis: Post Doc.

(Sep 05-Feb 06)Nonlinear Network: Fastrack ReleaseOperator Splitting: Rui ShiPackaging: Vincent PengFrequency Domain Analysis: R. Wang

References Efficient Transistor Level Simulation Using Two-Stage Newton-

Raphson and Multigrid Method,CK Cheng and Zhengyong Zhu, filed by UCSD, SD2005-013.

Circuit Splitting in Analysis of Circuits at Transistor Level, C.K. Cheng, R. Shi, and Z. Zhu, filed by UCSD, SD2005-129-PCT, June 7, 2005.

Z. Zhu, B. Yao, and C.K. Cheng, "Power Network Analysis Using an Adaptive Algebraic Multigrid Approach, ACM/IEEE Design Automation Conference, pp. 105-108, June 2003.

Z. Zhu, K. Rouz, M. Borah, C.K. Cheng, and E.S. Kuh, "Efficient Transient Simulation for Transistor-Level Analysis,“ Asia and South Pacific Design Automation Conf., 240-243, 2005.