tps56637 4.5-v to 28-v input, 6-a synchronous buck converter … · 2020. 12. 14. · tps56637...

Output Current (A)

Effic

iency (

%)

0.01 0.1 1 1080

82

84

86

88

90

92

94

96

98

100

FAD2

VIN=8VVIN=12VVIN=19VVIN=24V

EN VOUT

FBMODE

PG

VIN BOOT

SW

VIN

LCBST

COUT

RFBT

RFBB

CIN

TPS56637RPA

NC

PGNDAGND

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS56637SLVSEG1A –JULY 2018–REVISED SEPTEMBER 2019

TPS56637 4.5-V to 28-V Input, 6-A Synchronous Buck Converter

1

1 Features1• 4.5-V to 28-V input voltage range• 0.6-V to 13-V output voltage range• 6-A maximum continuous output current• Integrated 26-mΩ and 12-mΩ MOSFETs• 0.6-V ±1% Reference Voltage• D-CAP3™ control mode for fast transient

response• Eco-mode™ and FCCM (forced continuous

conduction mode) selectable for light-loadoperation through MODE pin

• Internal 2-ms soft start• Built-in output discharge function• 500-kHz switching frequency• Power good indicator to monitor output voltage• Cycle by cycle over current limit• Non-latched protections for UV, OV, OT and

UVLO• –40°C to +150°C operating junction temperature• Small 10-Pin 3.0-mm × 3.0-mm HotRod™ QFN

Package• Available in WEBENCH® Power Designer to

create custom designs

2 Applications• Enterprise systems: multifunction printers, storage• Personal electronics: TVs, speakers, set-top box,

portable electronics• Industrial applications: electronic point of sale,

factory automation and control, motor drives• General purposes for 12-V,19-V, 24-V power-bus

supply

3 DescriptionThe TPS56637 is a high efficiency, high-voltageinput, easy-to-use synchronous buck converter withintegrated MOSFETs.

With the wide operating input voltage range of 4.5 Vto 28 V, the TPS56637 is ideally suited for systemspowered from 12-V, 19-V, 24-V power-bus rails. Itsupports up to 6-A continuous output current atoutput voltages between 0.6 V and 13 V.

The TPS56637 uses DCAP3™ control mode toprovide fast transient response, good line and loadregulation, no requirement for external compensation,and supports low equivalent series resistance (ESR)output capacitors such as POSCAP and MLCC.

The TPS56637 has both FCCM and Eco-mode™operation modes for selection at light-load conditionthrough configuration of MODE pin. To attain highefficiency at light load, Eco-mode™ could beselected. To support tight output voltage ripplerequirement, FCCM could be selected.

The TPS56637 provides complete non-latched OV(Over-voltage), UV (Under-voltage), OC (Over-current), OT (Over-temperature) and UVLO (Under-voltage lock-out) protections combined with powergood indicator and output discharge function features.

The TPS56637 is available in a 10-pin 3.0-mm x 3.0-mm HotRod™ QFN package and the junctiontemperature is specified from –40°C to 150°C.

Device Information(1)PART NUMBER PACKAGE BODY SIZE (NOM)

TPS56637 VQFN-HR (10) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Schematic Efficiency vs Output CurrentVOUT = 5 V

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2

TPS56637SLVSEG1A –JULY 2018–REVISED SEPTEMBER 2019 www.ti.com

Product Folder Links: TPS56637

Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 Handling Ratings....................................................... 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information .................................................. 46.5 Electrical Characteristics........................................... 56.6 Timing Requirements ................................................ 66.7 Typical Characteristics .............................................. 7

7 Detailed Description ............................................ 107.1 Overview ................................................................. 107.2 Functional Block Diagram ....................................... 117.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 178 Application and Implementation ........................ 18

8.1 Application Information............................................ 188.2 Typical Application ................................................. 18

9 Power Supply Recommendations ...................... 2410 Layout................................................................... 24

10.1 Layout Guidelines ................................................. 2410.2 Layout Example .................................................... 25

11 Device and Documentation Support ................. 2611.1 Documentation Support ....................................... 2611.2 Receiving Notification of Documentation Updates 2611.3 Community Resources.......................................... 2611.4 Trademarks ........................................................... 2611.5 Electrostatic Discharge Caution............................ 2611.6 Glossary ................................................................ 26

12 Mechanical, Packaging, and OrderableInformation ........................................................... 26

4 Revision History

Changes from Original (July 2018) to Revision A Page

• Changed marketing status from Advance Information to production data. ............................................................................ 1

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FB

EN

AG

ND

PG

BOOT

NC

SW

8

9

7

6

10 5

1 2 3 4

VIN

PGND

MODE

VINVINVIN

3

TPS56637www.ti.com SLVSEG1A –JULY 2018–REVISED SEPTEMBER 2019


Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

RPA Package10-Pin VQFN-HR

Top View

Pin FunctionsPIN

TYPE DESCRIPTIONNAME NO.AGND 3 G Ground of internal analog circuitry. Connect AGND to PGND plane at a single point.

BOOT 7 I Supply input for the gate drive voltage of the high-side MOSFET. Connect a 0.1-µF bootstrap capacitorbetween BOOT and SW.

EN 1 I Enable input control. Driving EN high or leaving this pin floating enables the converter. A resistordivider can be used to imply an UVLO function.

FB 2 I Output feedback. Connect FB to the tap of an external resistor divider from the output to GND to setthe output voltage.

MODE 10 I Operation mode selection pin. Leaving this pin floating(≥500 kΩ) forces the TPS56637 into FCCM.Connecting this pin to GND(≤10 kΩ) forces the TPS56637 into Eco-mode™ under light load.NC 5 N Not Connected, keep this pin floating.

PG 4 O Open Drain Power Good Indicator, it is asserted low if output voltage is out of PG threshold due toover-voltage, under-voltage, thermal shutdown, EN shutdown or during soft-start.PGND 9 G Power GND terminal. Source terminal of low side MOSFET.

SW 6 O Switching node terminal. Connect the output inductor to this pin with wide and short tracks

VIN 8 P Input voltage supply pin. Drain terminal of high-side MOSFET. Connect the input decoupling capacitorsbetween VIN and GND.


4




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum RatingsOver the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted) (1)

MIN MAX UNIT

Input voltage

VIN –0.3 32 VBOOT –0.3 SW+6 VBOOT-SW –0.3 6.0 VEN, FB, MODE –0.3 6.0 VPGND, AGND –0.3 0.3 V

Output voltageSW –0.3 32 VSW (

5




(1) Not representative of the total input current of the system when in regulation. Ensured by design and characterization test.(2) Not production tested. Ensured by design and engineering sample correlation.

6.5 Electrical CharacteristicsThe electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. Thesespecifications are interpreted as conditions that will not degrade the parametric or functional specifications of the device forthe life of the product containing it. Typical values correspond to TJ = 25°C, VIN = 12 V. Minimum and maximum limits arebased on TJ = –40°C to +150°C, VIN = 4.5 V to 28 V(unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSUPPLY CURRENT

IQQuiescent current, Operating at ULQmode (1) 140 µA

ISD Shutdown supply current TJ=25°C, VEN=0 V 2 µAUVLO

UVLO VIN Under-Voltage LockoutWake up VIN voltage 4.0 4.2 4.4 VShut down VIN voltage 3.6 3.7 3.8 VHysteresis VIN voltage 500 mV

ENABLE(EN PIN)IEN_INPUT Input current VEN = 1.1V 1 µAIEN_HYS Hysteresis current VEN = 1.3V 4 µAVEN(ON) Enable threshold

EN rising 1.18 1.26 VVEN(OFF) EN failling 1.04 1.12 VFEEDBACK VOLTAGE

VFB Feedback voltage

VOUT = 5V, continuous modeoperation, TJ=25°C

0.594 0.6 0.606 V

VOUT = 5V, continuous modeoperation, TJ=-40°C to 150°C

0.591 0.6 0.609 V

MOSFETRDS(on)h High side switch resistance TJ = 25°C, VBST - VSW = 5 V 26 mΩRDS(on)l Low side switch resistance TJ = 25°C 12 mΩCURRENT LIMITIOCL Valley current limit 6.3 7.5 8.6 AIOC_REV Reverse current limit for FCCM Mode 2.3 3 3.7 APOWER GOOD

VPGTH

PG lower threshold - falling % of VFB 85%PG lower threshold - rising % of VFB 90%PG upper threshold - falling % of VFB 110%PG upper threshold - rising % of VFB 115%

IPGSINK PG sink current VFB = 0.5V, VPG = 0.5V 1.5 mAIPGLK PG leakage current VPG = 5.5V -1 1 µAFREQUENCYFSW Switching frequency VOUT =5V, continuous mode operation 500 kHzOUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

VOVP Output OVP thresholdOVP detect(L>H) 125%Hysteresis 5%

VUVP Output UVP thresholdHiccup detect(H>L) 65%Hysteresis 5%

THERMAL SHUTDOWN

TSDN Thermal shutdown threshold (2)Temperature Rising 165 °CHysteresis 30 °C

SW DISCHARGE RESISTANCERDISCHG VOUT discharge resistance VEN=0, VSW=0.5V, TJ=25°C 200 Ω


6




(1) Not production tested. Ensured by design and engineering sample correlation.

6.6 Timing RequirementsThe electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. Thesespecifications are interpreted as conditions that will not degrade the parametric or functional specifications of the device forthe life of the product containing it. Typical values correspond to TJ = 25°C, VIN = 12 V. Minimum and maximum limits arebased on TJ = –40°C to +150°C, VIN = 4.5 V to 28 V(unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNITON-TIME TIMER CONTROLtON(MIN) Minimum on time (1) 50 ns

tOFF(MIN) Minimum off timeVFB = 0.5 V, measure SW at 50% VIN,Eco-mode 200 300 ns

SOFT STARTTSS Soft start time Internal soft-start time 2 msOUTPUT UNDERVOLTAGE PROTECTION

TUVP_WAIT UV protection hiccup wait timeUV triggered (VFB lower than 65%VFB_nom)

0.25 ms

TUVP_HICCUPUV protection hiccup time beforerecovery 25 ms


TJ - Junction Temperature (qC)

Feedback V

olta

ge (

V)

-40 -20 0 20 40 60 80 100 120 140 1600.594

0.596

0.598

0.6

0.602

0.604

0.606

Vfb2TJ - Junction Temperature (qC)

VIN

UV

LO

Th

resh

old

(V

)

-40 -20 0 20 40 60 80 100 120 140 1603.4

3.6

3.8

4

4.2

4.4

4.6

UVLO

VINUVLO_RISEVINUVLO_FALL


Hig

h-s

ide R

ds_

on (

m:

)

-40 -20 0 20 40 60 80 100 120 140 16020

22

24

26

28

30

32

34

36

38

40

RdsHTJ - Junction Temperature (qC)

Lo

w-s

ide

Rds_

on (

m:

)

-40 -20 0 20 40 60 80 100 120 140 1608

10

12

14

16

18

RdsL


Quie

scent C

urr

ent (P

A)

-40 -20 0 20 40 60 80 100 120 140 160138

138.5

139

139.5

140

140.5

141

141.5

142

142.5

143

IqTe TJ - Junction Temperature (qC)

Sh

utd

ow

n C

urr

en

t (P

A)

-40 -20 0 20 40 60 80 100 120 140 1601

1.5

2

2.5

3

3.5

4

IsdT

7




6.7 Typical CharacteristicsVIN = 12 V (unless otherwise noted)

Figure 1. Quiescent Current vs Temperature Figure 2. Shutdown Current vs Temperature

Figure 3. High-Side RDS(on) vs Temperature Figure 4. Low-side RDS(on) vs Temperature

Figure 5. Feedback Voltage vs Temperature Figure 6. VIN UVLO Threshold vs Temperature


IOUT - Load Current (A)

Effic

ien

cy

0.001 0.01 0.1 1 100

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1.05

VIN=6V, ECOVIN=6V, FCCMVIN=12V, ECOVIN=12V, FCCMVIN=19V, ECOVIN=19V, FCCMVIN=24V, ECOVIN=24V, FCCM


Effic

iency

0.001 0.01 0.1 1 100

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

3.3V


VIN - Input Voltage (V)

FS

W -

Sw

itchin

g F

requency (

kH

z)

6 8 10 12 14 16 18 20 22 24 26 28 30450

475

500

525

550

575

600

625

FswV

ECOFCCM

IOUT - Output Current (A)

FS

W -

Sw

itchin

g F

requency (

kH

z)

0.001 0.01 0.1 1 100

50

100

150

200

250

300

350

400

450

500

550

600

FswL



EN

Th

resh

old

(V

)

-40 -20 0 20 40 60 80 100 120 140 1601.06

1.08

1.1

1.12

1.14

1.16

1.18

1.2

1.22

1.24

1.26

EN2p

VEN_RISINGVEN_FALLING


I OC

L -

Va

lley C

urr

en

t Lim

it (

A)

-40 -20 0 20 40 60 80 100 120 140 1607.3

7.35

7.4

7.45

7.5

7.55

7.6

7.65

7.7

7.75

LOC2

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Typical Characteristics (continued)VIN = 12 V (unless otherwise noted)

Figure 7. EN Threshold vs Temperature Figure 8. Valley Current Limit vs Temperature

VOUT=5 V IOUT = 6 A

Figure 9. Switching Frequency vs Input voltage

VOUT = 5 V L = 3.3 µH Eco-mode™

Figure 10. Switching Frequency vs Output Current

Figure 11. VOUT = 1.05 V Efficiency, L = 1 µH Figure 12. VOUT = 3.3 V Efficiency, L = 2.2 µH



Effic

ien

cy

0.001 0.01 0.1 1 100

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

5Vou



Effic

ien

cy

0.001 0.01 0.1 1 100

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

12Vo

VIN=19V, ECOVIN=19V, FCCMVIN=24V, ECOVIN=24V, FCCM

9




Typical Characteristics (continued)VIN = 12 V (unless otherwise noted)

Figure 13. VOUT = 5 V Efficiency, L = 3.3 µH Figure 14. VOUT = 12 V Efficiency, L = 5.6 µH


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7 Detailed Description

7.1 OverviewThe TPS56637 is a 6-A synchronous buck converter operating from 4.5V to 28V input voltage (VIN), and itsoutput voltage ranges from 0.6V to 13V. The proprietary D-CAP3™ mode enables low external componentcount, ease of design, optimization of the power design for power, size and efficiency. The device employs D-CAP3™ mode control that provides fast transient response with no external compensation components and anaccurate feedback voltage. The control topology provides seamless transition between CCM operating mode athigher load condition and DCM operation at lighter load condition. Eco-mode™ allows the TPS56637 to maintainhigh efficiency at light load. FCCM mode has the quasi-fixed switching frequency at both light and heavy load.The TPS56637 is able to adapt both low equivalent series resistance (ESR) output capacitors such as POSCAPor SP-CAP, and ultra-low ESR ceramic capacitors.


SWXCON+ TSD165°C /

30°C

VIN

BOOT

PGND

UV+

SS

0.6V

FB

Control Logic +

+ OV

+

4.2V/3.7V

UVLO

UV threshold

OV threshold

Soft Start

+

+

OCL

ZC

+

One Shot

Reference

Regulator

VREG5

VREG5

+NOCL

PG Logic

PG rising threshold

+

+

PG falling threshold

PG

x� On/Off time

x� Min On/Off time

x� FCCM/Eco-mode

x� Soft-start

x� Power Good

x� OCL

x� UVP/OVP/TSD

EN

Enable Threshold

+

Ip

Ih

Light Load Operation

MODE

NCAGND

Discharge Control


11




7.2 Functional Block Diagram


PGOOD

EN

Internal

VCC

MODE

VOUT

EN Threshold

1.18V

VCC UVLO

4.2V

64µs

1ms

MODE

Detection

Tss= 2ms 90%

VOUT

100µs 650µs

12




7.3 Feature Description

7.3.1 The Adaptive On-Time Control and PWM OperationThe main control loop of the TPS56637 is adaptive on-time pulse width modulation (PWM) controller thatsupports a proprietary DCAP3™ mode control. The DCAP3™ mode control combines adaptive on-time controlwith an internal compensation circuit for quasi-fixed frequency and low external component count configurationwith both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. TheTPS56637 also includes an error amplifier that makes the output voltage very accurate. No external currentsense network or loop compensation is required for DCAP3™ control topology.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internalone-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inverselyproportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltagerange, hence it is called adaptive on-time control. When the feedback voltage falls below the reference voltage,the one-shot timer is reset and the high-side MOSFET is turned on again . An internal ripple generation circuit isadded to reference voltage for emulating the output ripple, and this enables the use of very low-ESR outputcapacitors such as multi-layered ceramic caps (MLCC).

7.3.2 Mode SelectionTPS56637 has a MODE pin that can offer 2 different states of operations under light load condition. If MODE pinis short to GND(≤10kΩ), TPS56637 works under Eco-mode™ control scheme. If MODE pin is floating(≥500kΩ),TPS56637 works under FCCM mode.

Figure 15 below shows the typical start-up sequence of the device once the enable signal triggers the EN turn-onthreshold. After the voltage of internal VCC crosses the UVLO rising threshold, it takes about 64µs to finish thereading and setting of MODE. After this process, the MODE is latched and will not change until VIN or EN togglesto restart-up this device. Then after a delay of around 650µs the internal soft-start function begins to ramp up thereference voltage to the PWM comparator.

Table 1. MODE Pin SettingsMODE Pin Light Load Operation Mode

Short to GND (≤10kΩ) Eco-mode™Floating (≥500kΩ) FCCM

Figure 15. Power-Up Sequence


IN

OUTOUTIN

SW

OUT(LL)V

V)V(V

fL2

1I

�

13




7.3.2.1 Eco-mode™ Control SchemeWhen MODE pin is short to GND(≤10kΩ), the TPS56637 is set to Eco-mode™ control scheme to maintain highlight load efficiency. As the output current decreases from heavy load condition, the inductor current is alsoreduced and eventually comes to a point that its rippled valley touches zero level, which is the boundary betweencontinuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zeroinductor current is detected. As the load current further decreases the converter runs into discontinuousconduction mode. The on-time is kept almost the same as it was in the continuous conduction mode so thatlonger time is needed to discharge the output capacitor with smaller load current to the level of the referencevoltage. This process makes the switching frequency lower, proportional to the load current, and keeps the lightload efficiency high. The transition point to the light load operation IOUT(LL) current can be calculated byEquation 1.

(1)

7.3.2.2 FCCM ControlWhen MODE pin is floating(≥500kΩ), the TPS56637 is set to operate in forced continuous conduction mode(FCCM) in light load conditions and allows the inductor current to become negative. In FCCM, the switchingfrequency is maintained at a quasi-fixed level over the entire load range which is suitable for applicationsrequiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency underlight load compared with which under Eco-mode™. This mode also can help to avoid switching frequencydropping into audible range that may introduces some audible "noise".

7.3.3 Soft Start and Pre-Biased Soft StartThe TPS56637 features an internal 2-ms soft-start function. The internal soft start circuitry controls the outputvoltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage risetime. It also prevents unwanted voltage drops from high impedance power sources or batteries. When EN pin isset to start device operation, the internal soft-start circuitry will begin ramping up the reference voltage to thePWM comparator with a controlled slope. If the output capacitor is pre-biased at startup, the device initiatesswitching and start ramping up only after the internal reference voltage becomes greater than the feedbackvoltage VFB. This scheme ensures that the converters ramp up smoothly into regulation point.


� �2 IN 1 2 p hEN

1 2

R V R R I IV

R R

u � �

�

� �hp1ENfallingSTOP

ENfalling1

2IIRVV

VRR

��

u

h

ENrising

ENfalling

p

STOP

ENrisig

ENfalling

START

1

IV

V1I

VV

VV

R

�¸¸

¹

·

¨¨

©

§�

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EN

Ip IhR1

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14




7.3.4 Enable and Adjusting Undervoltage LockoutThe EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the thresholdvoltage, the device begins operating. If the EN pin voltage is pulled below the threshold voltage, the regulatorstops switching and enters the standby operation.

The EN pin has an internal pull-up current source which allows the user to float the EN pin to enable the device.If an application requires control of the EN pin, open-drain or open-collector output logic can be used to interfacewith the pin.

The TPS56637 implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabledwhen the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has ahysteresis of 500 mV.

If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shownin Figure 16. When using the external UVLO function, setting the hysteresis at a value greater than 500 mV isrecommended.

The EN pin has a small pull-up current, Ip, which sets the default state of the pin to enable when no externalcomponents are connected. The pull-up current is also used to control the voltage hysteresis for the UVLOfunction because it increases by Ih when the EN pin crosses the enable threshold. Use Equation 2 , andEquation 3 to calculate the values of R1 and R2 for a specified UVLO threshold. Once R1, R2 were settleddown, the VEN voltage can be calculated by Equation 4, which should be lower than 5.5V with max VIN.

Figure 16. Adjustable VIN Undervoltage Lockout

(2)

(3)

(4)

Where• Ip = 1 µA• Ih = 4 µA• VENfalling = 1.12 V• VENrising = 1.18 V


15




7.3.5 Output Overcurrent Limit and Undervoltage ProtectionThe output overcurrent limit (OCL) is implemented using a cycle by cycle valley detect control circuit. Theswitching current is monitored during off state by measuring the low-side FET drain to source voltage. Thisvoltage is proportional to the switching current. To improve accuracy, the voltage sensing is temperaturecompensated.

During the on-time of the high-side FET switch, the switching current increases at a linear rate determined byVIN, VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this currentdecreases linearly. The average value of the switch current is the load current IOUT. If the monitored current isabove the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, eventhe voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequentswitching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of over current limit. When the load current is higher thanthe over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and thecurrent is being limited, output voltage tends to drop because the load demand is higher than what the convertercan support. When the output voltage falls below 65% of the target voltage, the UVP comparator detects it andshuts down the device after a deglitch wait time of 0.25ms and then re-start after the hiccup time of 25ms. Whenthe over current condition is removed, the output will be recovered.

7.3.6 Overvoltage ProtectionWhen the output voltage becomes higher than 125% of the target voltage, the OVP comparator output goes highafter a deglitch time of 256µs and then the output will be discharged. When the over voltage condition isremoved, the discharge path will still be on for a hiccup time of 25ms before a re-soft-start process to recover theoutput voltage.


16




7.3.7 UVLO ProtectionUndervoltage Lockout protection(UVLO) monitors the internal regulator voltage. When the voltage is lower thanUVLO threshold voltage, the device is shut down. This protection is non-latched.

7.3.8 Thermal ShutdownThe junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 165°C(typical), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off andthe discharge path is turned on. When Tj decreases below the hysteresis amount, the converter resumes normaloperation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 30°C is implementedon the thermal shut down temperature.

7.3.9 Output Voltage DischargeThe TPS56637 has a built in discharge function by using an integrated MOSFET with 200-Ω RDS(on), which isconnected to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.The discharge path will be turned on when the device is turned off due to UV, OV, OT and EN shut downconditions.

7.3.10 Power GoodThe TPS56637 has a built in power good (PG) function to indicate whether the output voltage has reached itsappropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is anopen-drain output that requires a pull-up resistor (to any voltage below 5.5 V). A pull-up resistor of 100kΩ isrecommended to pull it up to 5V voltage. It can sink 1.5mA of current and maintain its specified logic low level.Once the FB pin voltage is between 90% and 110% of the internal reference voltage (VREF) and after a deglitchtime of 64µs, the PG turns to high impedance status. The PG pin is pulled low after a deglitch time of 32µs whenFB pin voltage is lower than 85% of the internal reference voltage or greater than 115% of the internal referencevoltage, or in events of thermal shutdown, EN shutdown, UVLO conditions. VIN must remain present for the PGpin to stay Low.

Table 2. Power Good Pin Logic Table (TPS56637)

Device StatePG Logic Status

High Impedance Low

Enable (EN=High)VFB doesn't trigger VPGTH √

VFB triggers VPGTH √Shutdown (EN=Low) √UVLO 2 V < VIN < VUVLO √Thermal Shutdown TJ > TSD √Power Supply Removal VIN < 2 V √


17




7.4 Device Functional Modes

7.4.1 Standby OperationThe TPS56637 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdowncurrent of 2µA(typical) when in standby condition.

7.4.2 Normal OperationWhen the input voltage is above the UVLO threshold voltage and EN pin is high, TPS56637 can operate in itsnormal switching modes. Normal continuous conduction mode (CCM) occurs when the minimum switch current isabove 0 A. In CCM, the TPS56637 operates at a quasi-fixed frequency of 500kHz (typical).

7.4.3 Light Load OperationWhen the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conductionmode (FCCM) during light-load conditions. During FCCM, the switching frequency is maintained at an almostconstant level over the entire load range which is suitable for applications requiring tight control of the switchingfrequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is selected tooperate in Eco-mode™ control scheme, the device enters pulse skip mode after the valley of the inductor ripplecurrent crosses zero. The Eco-mode™ control scheme maintains higher efficiency at light load with a lowerswitching frequency. If the TPS56637 works at Eco-mode™ and the load current is light enough to a specificvalue, the TPS56637 will enter ULQ mode that the TPS56637 will disable some internal circuits to furtherincrease the light load efficiency.


1

2

J1

1

2

J2

10uF

C1

10uF

C2

0.1uF

C3

AGND

PGND

PGND

0

R4

0.1uF

C4

3.3uH

L1

22uF

C5

22uF

C6

22uF

C7

22uF

C8

49.9

R5

73.2k

R6

10.0k

R7

20.0k

R8

100pF

C9

PGND

FB

AGNDPGNDAGND

VOUTVIN SW

100k

R9

EN1

FB2

AGND3

PG4

NC5

SW6

BOOT7

VIN8

PGND9

MODE10

TPS56637

U1

AGND

VCC

169k

R1

36.1k

R2

DNP DNP


18




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe schematic of Figure 17 shows a typical application for TPS56637. This design converts an input voltagerange of 8V to 28V down to 5V with a maximum output current of 6 A.

8.2 Typical ApplicationThe application schematic in Figure 17 shows the TPS56637 8-V to 28-V Input, 5-V output converter designmeeting the requirements for 6-A output. This circuit is available as the evaluation module (EVM). The sectionsprovide the design procedure.

Figure 17. TPS56637 5-V, 6-A Reference Design

8.2.1 Design RequirementsTable 3 shows the design parameters for this application.

Table 3. Design ParametersPARAMETER EXAMPLE VALUE

Input voltage range 24V nominal, 8V to 28VOutput voltage 5VTransient response, 6-A load step ΔVOUT = ±5%Output ripple voltage

OUTOUT

P

CL2

1f

u

¸¹

·¨©

§�u

R7

R610.6V

OUT

19




8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors SelectionThe output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%tolerance or better divider resistors. Start by using Equation 5 to calculate VOUT. R5 is optional and can be usedto measure the control loop's frequency response.

To improve efficiency at very light loads consider using larger value resistors. If the resistance is too high thedevice will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable.Please note that dynamically adjusting output voltage is not recommended.

(5)

8.2.2.2 Output Filter SelectionThe LC filter used as the output filter has double pole at:

(6)

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internalgain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls offat a –40 dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reducesthe gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zerofrequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 6is located below the high frequency zero but close enough that the phase boost provided be the high frequencyzero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommendedin Table 4.

(1) Please use the recommended L1 and COUT combination of the higher and closest output rail forunlisted output rails.

(2) R6=0Ω for VOUT=0.6V(3) COUT is the sum of effective output capacitance. In this datasheet the effective capacitance is defined

as the actual capacitance under DC bias and temperature, not the rated or nameplate values. All highvalue ceramic capacitors have a large voltage coefficient in addition to normal tolerances andtemperature effects. A careful study of bias and temperature variation of any capacitor bank should bemade in order to ensure that the minimum value of effective capacitance is provided. Refer to theinformation of DC bias and temperature characteristics from manufacturers of ceramic capacitors.

(4) R8 and C9 can be used to improve the load transient response or improve the loop-phase margin. Theapplication report Optimizing Transient Response of Internally Compensated DCDC Converters withFeed-forward Capacitor is helpful when experimenting with a feed-forward capacitor.

Table 4. Recommended Component Values

OUTPUTVOLTAGE (1)

(V)R6 (2)(kΩ)

R7(kΩ)

L1(µH)

COUT(3)(µF) C9 (pF)

(4) R8 (kΩ) (4)

MIN TYP MAX1.05 7.5 10.0 1 30 35 1001.2 10 10.0 1 30 35 1001.8 20 10.0 1.2 30 35 1003.3 45.3 10.0 2.2 20 35 100 100 to 220 205 73.2 10.0 3.3 20 30 100 100 to 220 2012 191 10.0 5.6 25 30 100 100 to 220 20

http://www.ti.com/product/tps56637?qgpn=tps56637http://www.ti.comhttp://www.ti.com/product/tps56637?qgpn=tps56637http://www.ti.com/feedbackform/techdocfeedback?litnum=SLVSEG1A&partnum=TPS56637http://www.ti.com/lit/an/slva289b/slva289b.pdfhttp://www.ti.com/lit/an/slva289b/slva289b.pdf

( )CIN(rms)

IN(min) OUTOUTOUT

IN(min) IN(min)

V -VVI = I × ×

V V

SWin

outmax

in

fC

0.25Iû9

� �

SWOIN

OUTINOUT

CO(RMS)fLV12

VVVI

�

2

PP

2

OLO(RMS) Il12

1II

��

2

IlIIl

PP

OPEAK

��

SWO

OUTIN(MAX)

IN(MAX)

OUT

PPfL

VV

V

VIl

�

�

20




The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 7,Equation 8, and Equation 9. The inductor saturation current rating must be greater than the calculated peakcurrent and the RMS or heating current rating must be greater than the calculated RMS current.

Use 500 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 8 and the RMScurrent of Equation 9.

(7)

(8)

(9)

For this design example, the calculated peak current is 7.28A and the calculated RMS current is 6.05 A. Theinductor used is IHLP3232DZER3R3M11 with a peak current rating of 10.5A and an RMS current rating of 9.7A.

The capacitor value and ESR determines the amount of output voltage ripple. TheTPS56637 is intended for usewith ceramic or other low ESR capacitors. Recommended values range from 20 µF to 100 µF. Use Equation 10to determine the required RMS current rating for the output capacitor.

(10)

For this design two MuRata GRM32ER71E226KE15L 22-µF output capacitors are used so that the effectivecapacitance is 31.08 µF at DC biased voltage of 5V. The calculated RMS current is 0.738A and each outputcapacitor is rated for 4 A.

8.2.2.3 Input Capacitor SelectionThe TPS56637 requires an input decoupling capacitor and a bulk capacitor is needed depending on theapplication. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µFcapacitor (C3) from VIN to PGND pin is recommended to provide additional high frequency filtering. Thecapacitor voltage rating needs to be greater than the maximum input voltage. The input voltage ripple can becalculated using Equation 11.

(11)

The capacitor must also have a ripple current rating greater than the maximum input current ripple of theapplication. The input ripple current is calculated by Equation 12:

(12)

8.2.2.4 Bootstrap Capacitor SelectionA 0.1-µF ceramic capacitor(C4) must be connected between the BOOT to SW pin for proper operation. TIrecommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V orhigher voltage rating.


Vin = 200 mV/div

100 µs/div

Vout = 50 mV/div

SW = 7 V/div

IL = 3 A/div

VIN = 300 mV/div

VOUT = 40 mV/div

SW = 8 V/div

IL = 3 A/div

5 µs/div

VIN (V)

VO

UT(V

)

8 10 12 14 16 18 20 22 24 26 284.976

4.984

4.992

5

5.008

5.016

5.024

5.032

5.04

5.048

5.056

Line

IOUT = 0.01AIOUT = 0.6AIOUT = 3AIOUT = 6A

Frequency (Hz)

Mag (

dB

)

Phase (d

eg)

1x103 1x104 1x105 1x106 3x106-60 -240

-50 -200

-40 -160

-30 -120

-20 -80

-10 -40

0 0

10 40

20 80

30 120

40 160

50 200

60 240

Bode

MagnitudePhase


Effic

ien

cy

0.001 0.01 0.1 1 1050%

55%

60%

65%

70%

75%

80%

85%

90%

95%

100%

5Vou

VIN=8V, VOUT=5VVIN=12V, VOUT=5VVIN=19V, VOUT=5VVIN=24V, VOUT=5V

IOUT (A)

VO

UT (

V)

0.001 0.01 0.1 1 104.992

4.996

5

5.004

5.008

5.012

5.016

5.02

5.024

5.028

5.032

Load


21




8.2.3 Application Curves

Figure 18. Efficiency Figure 19. Load Regulation

Figure 20. Line Regulation

VIN = 24V VOUT = 5V IOUT = 6A

Figure 21. Bode Plot

Figure 22. Steady State Waveforms, IOUT = 0.01 A Figure 23. Steady State Waveforms, IOUT= 0.6 A


VOUT = 200 mV/div

ILOAD = 3 A/div

500 µs/div

VOUT = 200 mV/div

ILOAD = 3 A/div

500 µs/div

VOUT = 200 mV/div

ILOAD = 3 A/div

500 µs/div

VOUT = 200 mV/div

ILOAD = 3 A/div

500 µs/div

VIN = 300 mV/div

VOUT = 40 mV/div

SW = 8 V/div

IL = 3 A/div

2 µs/div

VIN = 300 mV/div

VOUT = 40 mV/div

SW = 8 V/div

IL = 3 A/div

2 µs/div

22




Figure 24. Steady State Waveforms, IOUT= 3 A Figure 25. Steady State Waveforms, IOUT= 6 A

Figure 26. Transient Response 0 to 3 A Figure 27. Transient Response 0 to 6 A

Figure 28. Transient Response 0.6 to 5.4 A Figure 29. Transient Response 3 to 6 A


EN = 5 V/div

Vout = 5 V/div

PG = 5 V/div

5 ms/div

SW = 20 V/div

EN = 5 V/div

Vout = 5 V/div

PG = 5 V/div

200 µs/div

SW = 20 V/div

Vin = 20 V/div

Vout = 5 V/div

PG = 5 V/div

10 ms/div

SW = 20 V/div

Vin = 20 V/div

Vout = 5 V/div

PG = 5 V/div

10 ms/div

SW = 20 V/div

23




Figure 30. Startup Relative to VIN Figure 31. Shutdown Relative to VIN

Figure 32. Enable Relative to EN Figure 33. Disable Relative to EN


24




9 Power Supply RecommendationsThe TPS56637 is designed to operate from input supply voltage in the range of 4.5 V to 28 V. Buck convertersrequire the input voltage to be higher than the output voltage for proper operation. Input supply current must beappropriate for the desired output current. If the input voltage supply is located far from the TPS56637 circuit,some additional input bulk capacitance is recommended.

10 Layout

10.1 Layout Guidelines1. Recommend a four-layer PCB for good thermal performance and with maximum ground plane.2. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of

advantage from the view point of heat dissipation.3. Putting at least two vias for VIN and GND traces, and as close as possible to the pins.4. The input capacitor and output capacitor should be placed as close to the device as possible to minimize

trace impedance.5. Provide sufficient vias for the input capacitor and output capacitor.6. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.7. Do not allow switching current to flow under the device.8. A separate VOUT path should be connected to the upper feedback resistor.9. Make a Kelvin connection to the GND pin for the feedback path.10. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has

ground shield.11. The trace of the VFB node should be as small as possible to avoid noise coupling.12. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize

its trace impedance.


VOUT

Top

Inner PGND and AGND Plane

Signal traces and PGND and AGND Plane

CIN

9

1 2 3 4

5

6

78

10

INDUCTOR

Inner PGND and AGND Plane

VCC

VIN

AGND

PGND PGND

Top Trace/Plane

AGND Plane

PGND Plane

VIA to Signal Plane

VIA to PGND Planes

VIA to AGND Planes

Trace on Signal Layer

CHF

COUT COUT

CBST

CFF

RFFRFBT

RFBB

RPG

RM

OD

E

RENT

RENB

25




10.2 Layout Example

Figure 34. TPS56637 Layout


26




11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related DocumentationFor related documentation see the following: Texas Instruments, TPS56637EVM-029 6-A, Regulator EvaluationModule user's guide• Texas Instruments, TPS56637EVM-029 6-A, Regulator Evaluation Module user's guide•11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

11.3 Community ResourcesTI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and donot necessarily reflect TI's views; see TI's Terms of Use.

11.4 TrademarksD-CAP3, Eco-mode, HotRod, DCAP3, E2E are trademarks of Texas Instruments.WEBENCH is a registered trademark of Texas Instruments.

11.5 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

http://www.ti.com/product/tps56637?qgpn=tps56637http://www.ti.comhttp://www.ti.com/product/tps56637?qgpn=tps56637http://www.ti.com/feedbackform/techdocfeedback?litnum=SLVSEG1A&partnum=TPS56637http://www.ti.com/lit/pdf/SLVUBE3http://www.ti.com/lit/pdf/SLVUBE3http://www.ti.com/lit/pdf/SLVUBE3http://e2e.ti.comhttp://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://www.ti.com/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS56637RPAR ACTIVE VQFN-HR RPA 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 T56637

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS56637RPAR VQFN-HR

RPA 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Oct-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS56637RPAR VQFN-HR RPA 10 3000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Oct-2019

Pack Materials-Page 2

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

PACKAGE OUTLINE

4224047/A 01/2018

www.ti.com

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT-NO LEAD

RPA0010A

A

0.08 C

B

PKG

PKG

3.1

2.9

3.1

2.9

PIN 1 INDEX AREA

1.00

0.80

0.05

0.00

SEATING PLANE

C

3X

0.3

0.2

2X

0.45

0.35

2X

2

1.8

1.6

1.4

0.1 C A B

0.05 C

0.1 C A B

0.05 C

7X

0.5

0.3

8X

0.3

0.2

0.1 C A B

0.05 C

REF (0.36)

(0.1) TYP

5X 0.5

2X 0.93

0.37

0.205

0.945

0.87

1

4

5 7

810

AutoCAD SHX Text

AutoCAD SHX Text

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

EXAMPLE BOARD LAYOUT

4224047/A 01/2018

www.ti.com


RPA0010A


PKG

PKG

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

NON SOLDER MASK

DEFINED

EXPOSED METAL

2X (0.4)

8X (0.25)

7X

(0.6)

(1.7)

2X

(2.1)

3X (0.25)

2X (0.93)

(0.37)

(0.95)

5X (0.5)

(2.8)

(0.21)

(0.87)

1

4

5 7

810

(R0.05) TYP

2X

(0.65)

(0.85)

(1.4)

(1.42)

(0.56)

www.ti.com/lit/slua271AutoCAD SHX Text

AutoCAD SHX Text

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

EXAMPLE STENCIL DESIGN

4224047/A 01/2018

www.ti.com


RPA0010A


SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD

PADS 6 and 9: 89% PRINTED COVERAGE BY

AREA

SCALE: 20X

PKG

PKG

2X (0.4)

8X (0.25)

7X

(0.6)

2X (0.75)

2X

(0.95)

3X (0.25)

2X (0.93)

(0.37)

(0.95)

5X (0.5)

(2.8)

(0.21)

(0.87)

(0.08)

(1.15)

(0.95)

(0.38)

1

4

5 7

810

METAL

TYP

(R0.05) TYP

(1.4)

(1.42)

(0.56)

AutoCAD SHX Text

AutoCAD SHX Text

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

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1 Features2 Applications3 DescriptionTable of Contents4 Revision History5 Pin Configuration and Functions6 Specifications6.1 Absolute Maximum Ratings6.2 Handling Ratings6.3 Recommended Operating Conditions6.4 Thermal Information6.5 Electrical Characteristics6.6 Timing Requirements6.7 Typical Characteristics

7 Detailed Description7.1 Overview7.2 Functional Block Diagram7.3 Feature Description7.3.1 The Adaptive On-Time Control and PWM Operation7.3.2 Mode Selection7.3.2.1 Eco-mode™ Control Scheme7.3.2.2 FCCM Control

7.3.3 Soft Start and Pre-Biased Soft Start7.3.4 Enable and Adjusting Undervoltage Lockout7.3.5 Output Overcurrent Limit and Undervoltage Protection7.3.6 Overvoltage Protection7.3.7 UVLO Protection7.3.8 Thermal Shutdown7.3.9 Output Voltage Discharge7.3.10 Power Good

7.4 Device Functional Modes7.4.1 Standby Operation7.4.2 Normal Operation7.4.3 Light Load Operation

8 Application and Implementation8.1 Application Information8.2 Typical Application8.2.1 Design Requirements8.2.2 Detailed Design Procedure8.2.2.1 Output Voltage Resistors Selection8.2.2.2 Output Filter Selection8.2.2.3 Input Capacitor Selection8.2.2.4 Bootstrap Capacitor Selection

8.2.3 Application Curves

9 Power Supply Recommendations10 Layout10.1 Layout Guidelines10.2 Layout Example

11 Device and Documentation Support11.1 Documentation Support11.1.1 Related Documentation

11.2 Receiving Notification of Documentation Updates11.3 Community Resources11.4 Trademarks11.5 Electrostatic Discharge Caution11.6 Glossary

12 Mechanical, Packaging, and Orderable InformationSheets and Views4224047-02_PKG_OULINE4224047-03_BOARD_LAYOUT4224047-04_STENCIL