11

TSMC Property

Towards High-Volume Manufacturingof Logic Devices

Using EUV Lithography

Anthony Yen, T.C. Wu, Shinn-Sheng Yu

Taiwan Semiconductor Manufacturing Company

22

TSMC Property

TSMC Fabs Around the World

6“ Fab in Taiwan 8“ Fabs in Taiwan 8“ Fabs Overseas

* JV with NXP

12“ Fabs in Taiwan

Fab 2 Fab 3

Fab 5

Fab 6

Fab 8

Fab11 (USA)

Fab10 (China)

SSMC (Singapore)*

Fab12

Fab14

33

TSMC PropertyTSMC Sales Growth

12,000

10,000

8,000

US$

M

6,000

4,000

2,000

0'98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09

Q1 Q2 Q3 Q4

44

TSMC Property

TSMC Technology RoadmapEnabled by Advances in Optical Lithography

Min

imum

Hal

f Pitc

h

Single-ExposureOptical Imaging Limit

TechnologyNode

65 nm(2006)

40 nm(2008)

28 nm(2010)

22 nm

55

TSMC PropertyEUVL Will Have a Cost Advantage

if suppliers execute to their throughput roadmaps

2.5R

elat

ive

Lith

o C

ost p

er W

afer EUV

2.0DP

SP

DDL 1.5

1.0

0.52009 2010 2011 2012 2013

66

TSMC Property

Processing Steps for 22-nm Patterning Alternatives

MetrologyStrip/clean

BARC/ACL/SiON etchMetrology

KrF DevelopExpose

KrF ResistKrF BARCMetrology MetrologyStrip/clean Strip/clean Metrology

BARC/ACL/SiON etch BARC/ACL/SiON etch Strip/cleanMetrology Metrology BARC/ACL/SiON etch

ArF Develop ArF Develop MetrologyExpose Expose ArF Develop

Metrology ArF Resist ArF Resist ExposeStrip/clean ArF BARC ArF BARC ArF Resist

BARC/ACL/SiON etch Metrology Metrology ArF BARCDefect Strip/clean Strip/clean Metrology

Metrology ACL/SiON etch Metrology ACL/SiON etch Strip/cleanArFi Develop Metrology Strip/clean Metrology Spacer etch

Expose Metrology Strip/clean BARC/ACL/SiON etch Strip/clean CMP OxArFi Top Coat Strip/clean Oxide Etch Back Spacer etch Oxide Etch Back CVD Oxide fill

ArFi Resist BARC/ACL/SiON etch Spacer Oxide CMP Ox Spacer Oxide Nitride SpacerArFi BARC Defect Metrology CVD Oxide fill Metrology Metrology

Metrology Metrology Metrology Strip/clean Nitride Spacer Strip/clean Strip/cleanStrip/clean Strip/clean ArFi Develop BARC/ACL/SiON etch Metrology BARC/ACL/SiON etch BARC/ACL/SiON etch

BARC/ACL/SiON etch BARC/ACL/SiON etch Expose Defect Strip/clean Defect DefectDefect Defect ArFi Top Coat Metrology BARC/ACL/SiON etch Metrology Metrology

Metrology Metrology ArFi Resist ArFi Develop Defect ArFi Develop ArFi DevelopArFi Develop ArFi Develop Freeze Expose Metrology Expose Expose Metrology

Expose Expose ArFi Develop ArFi Top Coat ArFi Develop ArFi Top Coat ArFi Top Coat Strip/cleanExpose ArFi Top Coat Expose ArFi Resist Expose ArFi Resist ArFi Resist ACL Etch

ArFi Top Coat ArFi Resist ArFi Top Coat ArFi BARC ArFi Top Coat ArFi BARC ArFi BARC MetrologyArFi Resist ArFi BARC ArFi Resist SiON/SiC ArFi Resist SiON/SiC SiON/SiC EUV DevelopArFi BARC SiON/SiC ArFi BARC ACL ArFi BARC ACL ACL ExposeSiON/SiC ACL SiON/SiC SiON/SiC SiON/SiC SiON/SiC SiON/SiC EUV Resist

ACL SiON/SiC ACL ACL ACL ACL ACL ACLDevice Film Device Film Device Film Device Film Device Film Device Film Device Film Device Film

Si Si Si Si Si Si Si Si

Double Exposure (DDL)

Litho-EtchLitho-Etch

Litho-Freeze Litho-Etch

Spacer positive 3x Litho

Spacer negative 1x Litho

Spacer positive 2x Litho

Spacer negative 2x Litho

Single Expose 0.32 NA EUV

Incr

easi

ng C

ost &

Cyc

le T

ime

Logic DRAM NAND All

EUV Single

Expose

DoubleExpose(DDL)

Spacer Double Patterning Litho Double Patterning

Source: ASML

77

TSMC Property

22-nm Node Critical Layer Patterning Cost

NAND DRAM Logic

Lith

o C

ritic

al L

ayer

Cos

t / W

afer

[$]

Spacer DPTLitho DPTEUV

~40%

~45%~30%

4 Layers 8 Layers 12 Layers

~50%

Source: ASML

88

TSMC Property

0 50 100 150 200 250 300 350 4000

10

20

30

40

50

60

70

80

90

100

Open Loop EUV Power in 10ms Window

In-b

and

EU

V P

ower

at I

.F. (

W)

Time (ms)

Closed Loop Dose Stability of <±0.35% meets Device Production Requirements

Open loop dose performance is <+/-11% (10ms window)

Closed loop dose performance is <+/-0.35%

EUV power level set point for closed loop control was 50W

0 50 100 150 200 250 300 350 4000

10

20

30

40

50

60

70

80

90

100

In-B

and

EU

V P

ower

at I

.F (W

)Time (ms)

Closed Loop EUV Power in 10ms Window

Source: Cymer

99

TSMC Property

In-House Fabrication of EUV Masks

Contact Holes

Metal-1

1010

TSMC Property

Absorber Defect Inspection Using 193-nm Tool

KT610 can execute inspection on the 22-nm Hole layer

1111

TSMC PropertyLTEM-ML Blank Defect Trend

Source: AGC

Goal: 0.01/cm2 @ 18 nm

1212

TSMC PropertyChallenges in EUV Mask Repair - Deposition

Need accurate 3-D profile control of deposited area

Need image verification by actinic AIMS tool

LTEM

LTEM

E-beam deposition

LTEM

AFM trim scrape

60 incident angle

1313

TSMC PropertyActinic Mask Metrology Tools Required for HVM

User funding of NRE is necessary

Actinic BI, AIMS, and PMI tools are required for HVM of EUV masksConsensus by SEMATECH EUV Mask TWG

User funding of NRE is required in order to build these tools in timeConsensus by SEMATECH EUV Mask BWG

ToolTotal NRE

Year 2010 2011 2012 2010 2011 2012 2011 2012 2013

User funding 10% 20% 20% 10% 30% 30% 10% 20% 20%

User funding in $ $4M $8M $8M $7M $21M $21M $20M $40M $40M

Patterned Inspection Tool$150 - $250M, average $200M

Blank Inspection Tool$40M

EUV AIMS Tool$70M

A scenario

Year 2010 2011 2012 2013 TotalCash Out $2M $8M $12M $7M $29M

Each user’s share, assuming six contributing parties

NRE funding recouped through future tool sales

1414

TSMC Property

Contact Layer of 32-nm LogicAlpha Demo Tool (ADT) at

IMEC

Metal-1 Layer of 20-nm Logic

EUV Lithography Processing Development

1515

TSMC Property

EUV Processing Window for 28-nm Logic

Focus (µm)

DOF: > 0.3 µm

1616

TSMC Property

EUV Processing Window for 22-nm Logic

Focus (µm)

Common DOF: > 150 nm

Common EL: ~10%

1717

TSMC Property

EUV OPC Run Time Test ResultsVendor A EUV Run time Analysis

hierman(1.3%) caculate density (4.04%)

generate flare (1.37%) dp correction (93.29%)

Vendor B EUV Run Time Analysis database preparation (0.66%)

flare map (0.92%)

flare retargeting (18.75%)

model base OPC (60.28%)

shadowing compensation

(19.38%)

Run time Run time in sec (120cpus) Run time in hrs (120cpus)Vendor A 154169(40cpus) 51389 14.27

Vendor B 208319 (28cpus) 48607 13.50

1818

TSMC PropertyEUV Resist-Related JDPs Planned

Hsinchu Science Park

NSRRC

TSMC

TLS

TPS

NSRRC: National Synchrotron Radiation Research CenterTLS: Taiwan Light Source (open to users in 1993)TPS: Taiwan Photon Source (will be open to users in 2013)

1919

TSMC Property

QuadrupoleMass Spectrometer

EUV Reflectometer

Taiwan Light Source

EUV Research Activities in Taiwan

2020

TSMC PropertyAcknowledgement

TSMC Nano Patterning Technology DivisionBurn Lin, Y.C. Ku, T.S. Gau, R.G. Liu, Angus Chin, Vincent Lee, Alex Chen, Luke Hsu, James Chu, T.C. Lien, Y.T. Tsai, Boren Lo, C.H. Chang, Jimmy Hu

TSMC Manufacturing Technology CenterJohn Lin, H.J. Lee, R.C. Peng, Tony Wu

IMEC/ASMLKurt Ronse, Hans Meiling, Jan Hermans, Andre van Dijk

2121

TSMC Property

“Once more unto the breach, dear friends, once more.”

– Wm. Shakespeare, in Henry V, quoted by Dr. Morris Chang

in TSMC Q2 2009 Analyst Meeting