topic10 introduction to the analog to digital subsystem on the freescale mc9s12x

7/29/2019 Topic10 Introduction to the Analog to Digital Subsystem on the Freescale MC9S12X.

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Analog: Its not all digital thesedays... 10

1Monday, 2 November 2009


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Analog to Digital Conversion

The analog subsystem is crucial in any embeddedapplication.

The real world is analog, not digital. Soconverting the real world into a form theprocessor can understand is very important.

The analog to digital subsystem is responsible forconverting an analog signal into a digitalrepresentation.



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An Analog to Digital converter can transform analog signals into a digitalword that the processor can understand.

This digital word can vary in size depending on the particular A/D

subsystem. Word sizes supported by A/D subsystems

8 bit

10 bit

12 bit

16 bit

24 bit

32 bit



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The A/D subsystem allows the possible range of input analog voltages to be

limited using two reference voltages: VRH (Highest possible input voltage)

Any input voltage higher than this value will result in the highestpossible digital word value.

VRL (Lowest possible input voltage)

Any input voltage lower than this value will result in the lowestpossible digital word value (zero).



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Analogue to Digital Conversion

So if the lowest digitaltoken (zero)represents VRL, and

the highest digitaltoken represents VRH.

Then any voltagewithin this rangewould follow a linearrelationship.

Relationship digital token and input analog voltage if VRH=5V,

VRL=0V, and AD word size is 8 bits.



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What is the relationship?

If we have a fixed word size and a know voltagerange we can work it out.

If we have a word size of 8 bits then we canrepresent 256 different numbers (256 differentvoltages between VRL and VRH).

The voltage difference between each digitalnumber is=(VRH - VRL) / (2word_size-1)



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If we had an 8 bit A/D, where VRL = 0 V andVRH = 5V, then

=(5-0)/(28-1)

=5/255

=0.01960 Volts

=19.6mV



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The relationship between analog input

voltage (Vi) and the resulting digital token(Dt) is

0 ,Vi < VRL

Dt = (Vi-VRL)/ ,VRLViVRHMax ,Vi > VRH{



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What is the relationship?Exercise (Answers)

=(VRH-VRL)/2word_size - 1

=(3-1)/(2

12

-1)=2/4095

=0.000488 Volts

=488Volts



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0 ,Vi < VRLDt = (Vi-VRL)/ ,VRLViVRH

Max ,Vi > VRH

1.89V since it is greater than VRL and less than VRHwould be

Dt = (Vi-VRL)/

= (1.89-1)/0.000488

= 1823

{



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Max ,Vi > VRH

2.4V since it is greater than VRL and less than VRHwould be

Dt = (Vi-VRL)/

= (2.4-1)/0.000488

= 2868

{



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Max ,Vi > VRH

4.5V since it is greater than VRH would beDt = 212-1

= 4095

{



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Aside: Digital 2 Analog



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How is it done?

There are many ways of converting analog signals into digital tokens.

The most common method used in micro-controllers is the successive

approximation approach.

S/H

Comparator

D/A

Weights Array

Control Logic

Shift Register

Vi

Dt

Clock

Reset

Init



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How is it done?

S/H

Comparator

D/A

Control Logic

100

Vi

Dt

Clock

Reset

Init

3 bit example assuming VRH = 5V and VRL = 0V

100

Weights Array

Shift Register



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How is it done?

S/H

Comparator

D/A

Control Logic

100

Vi

Dt

Clock

Reset

Init


100

Weights Array

Shift Register

3.8V



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How is it done?

S/H

Comparator

D/A

Control Logic

100

Vi

Dt

Clock

Reset

Init


100 Weights Array

Shift Register

3.8V



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How is it done?

S/H

Comparator

D/A

Control Logic

100

Vi

Dt

Clock

Reset

Init


100 Weights Array

Shift Register

2.5V3.8V



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How is it done?

S/H

Comparator

D/A

Control Logic

100

Vi

Dt

Clock

Reset

Init


100 Weights Array

Shift Register

2.5V3.8V

1



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How is it done?

S/H

Comparator

D/A

Control Logic

010

Vi

Dt

Clock

Reset

Init


010

Weights Array

Shift Register

3.8V

100



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How is it done?

S/H

Comparator

D/A

Control Logic

010

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

3.8V

110



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How is it done?

S/H

Comparator

D/A

Control Logic

010

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

3.75V3.8V

110



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How is it done?

S/H

Comparator

D/A

Control Logic

010

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

3.75V3.8V

1

110



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How is it done?

S/H

Comparator

D/A

Control Logic

001

Vi

Dt

Clock

Reset

Init


001

Weights Array

Shift Register

3.8V

110



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How is it done?

S/H

Comparator

D/A

Control Logic

001

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

3.8V

111



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How is it done?

S/H

Comparator

D/A

Control Logic

001

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

4.375V3.8V

111



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How is it done?

S/H

Comparator

D/A

Control Logic

001

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

4.375V3.8V

0

111



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How is it done?

S/H

Comparator

D/A

Control Logic

000

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

4.375V3.8V

0

111



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How is it done?

S/H

Comparator

D/A

Control Logic

000

Vi

Dt

Clock

Reset

Init


Weights Array

Shift Register

4.375V3.8V

0

110



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On-Chip A/D Subsystem

The MC9S12XDP512 contains two (S12ATD10B8CV3) 8 channel 10 bit

successive approximation A/D subsystems.

The external reference voltages VRH and VRL are set to 5V and GND

respectively on the Adapt9S12X board.

It also has external trigger pins, that can be used to initiate a sampling of theanalog inputs. A bit like the IRQ interrupt pin, but specifically for the A/D

subsystem.


ATD10B8CClockBus Clock ATD clock


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On-Chip A/D

Subsystems

VSSA

Analog

MUX

Mode and

Successive

Approximation

Register (SAR)

Results

ATD 0ATD 1ATD 2ATD 3ATD 4ATD 5ATD 6ATD 7

and DAC

Sample & Hold

11

VDDA

VRL

VRH

Sequence Complete

Interrupt

+

Comparator

Prescaler

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

ETRIG0

(See Device Overview

chapter for availability

ETRIG1

ETRIG2

ETRIG3

and connectivity)

Timing Control

ATDDIENATDCTL1

PORTAD

Trigger

Mux



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The physical interface Analog input pins of the A/D subsystem are labelled AN0-AN15.

The pins AN0-AN15 can be used as general purpose digital input when the A/D subsystemis not in use.

ATD0 ATD1



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The Programmers Model

All interaction with the AD subsystems is done via thereI/O register sets.

ATDxCTL2

ATDxCTL3

ATDxCTL4

ATDxCTL5

ATDxCTL1

ATDxCTL0



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Controlling the A/D

The 6 control registers of the A/D allow you toconfigure the A/D in the way that is suitable foryour application.

Following is an in-depth look at these registers.

ATDxCTL2

ATDxCTL3

ATDxCTL4

ATDxCTL5

ATDxCTL1

ATDxCTL0


C ll h A/D


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Controlling the A/D

ATDxCTL0

WRAP2-WRAP0 Channel number to wrap from. When doing multiple

conversions this register defines when the analog multiplexershould switch back to AN0 (or AN8). It will switch back toAN0 (or AN8) after sampling the channel defined in this

register.

WRAP0WRAP1WRAP200000


C lli h A/D


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Controlling the A/D

ATDxCTL1

ETRIGSEL 0 - Selects a analog input channel as the triggering source.

1 - Selects one of the triggering channels as the triggeringsource.

ETRIGCH2-ETRIGCH0 This number represents the triggering source.

ETRIGCH0ETRIGCH1ETRIGCH2000ETRIGSEL 0


C lli h A/D


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Controlling the A/D

ATDxCTL2

ADPU (ATD Power Up)

0 disable subsystem

1 enable subsystem

It takes approximately100useconds for the analog circuits stabilize.Once the subsystem is powered all registers are reset to theredefault state.

AFFC (ATD Fast Flag Clear All) 0 means ATD flag clearing operates normally (A read to ATDSTAT0

and the appropriate result register is required to clear thecorresponding CCF flag).

1 means only a read to the result register is required to resetthe CCF flag.

ACIFASCIEETRIGEETRIGPETRIGLEAWAIAFFCADPU


C lli h A/D


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Controlling the A/D

ATDxCTL2

AWAI (ATD Wait Mode)

0 continues to run when in wait mode

1 doesnt run when in wait mode

ETRIGLE

0 means edge triggered

1 means level triggered ETRIGP (work in combination with ETRIGLE)

0 means falling edge or low level

1 means rising edge or high level



C lli h A/D


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Controlling the A/D

ATDxCTL2

ETRIGE

0 means disable external trigger

1 means enable external trigger

ASCIE (ATD Sequence Complete Interrupt Enable)

0 disable ATD interrupt (default)

1 enable ATD interrupt

ASCIF (ATD Sequence Complete Interrupt Flag

0 = No ATD interrupt occurred

1 = An ATD interrupt occurred.



C t lli th A/D


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Controlling the A/D

ATDxCTL3

S8C-S1C

Sets the number of conversions that should take place.

FRZ0FRZ1FIFOS1CS2CS4CS8C0

S8C S4C S2C S1CNumber of Conversions

per Sequence

0 0 0 0 80 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 X X X 8


C t lli th A/D


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Controlling the A/D

ATDxCTL3

FIFO

Defines the behavior of the results registers.

0 means the results are stored in the corresponding registers.

1 means the results are stored in consecutive registers (wraparound at ATDDR15).

FRZ1-FRZ0

Sets the behavior in freeze mode (halted during debugging).

FRZ0FRZ1FIFOS1CS2CS4CS8C0



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PRS0PRS1PRS2PRS3PRS4SMP0SMP1SRES8

Controlling the A/D

A/D Clock selection and Sampling Time The time it takes for a sample to be performed can be programmed from

18 to 32 ATD clock cycles.

Further more, the ATD clock frequency can be programmed using the

prescaler bits (PRS4-PRS0) to produce an ATD clock in the range of 500kHz to 2 MHz.

ATDxCTL4

SRES8

Sets the word size of the A/D.

0 means a 10 bit word size for the result.

1 means an 8 bit word size for the result.



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Controlling the A/D

ATDxCTL4

SMP1-SMP0 (Sample time select)

Set the length of time for sampling the analog input. Usingthese two bit you set how long the sample and hold circuitcan charge.



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Controlling the A/D

ATDxCTL4

PRS4-PRS0 (ATD Clock Prescaler)

Set the frequency of the ATD clock. The relationshipbetween the ATD clock and the Bus Clock (8MHz) isshown below


C ll h A/D


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Controlling the A/DATDxCTL5

DJM (Result Register Data Justification)

0 means left justified. 1 means right justified.

DSGN (Result Data Register Signed or Unsigned)

0 means unsigned data representation in Result Register.

1 enable signed data representation in Result Register.

CACBCC0MULTSCANDSGNDJM


C ll h A/D


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DJM+DSGN



C lli h A/D


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Controlling the A/D

ATDxCTL5

SCAN (Continuous Conversion Sequence Mode) 0 means single conversion sequence.

1 means continuos operation.

MULT (Multi-channel sample mode)

0 means sample only one channel.

1 means sample across several channels.



C lli h A/D


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CD-CA (Analog Input Channel Select Code)

Select the analog Input.

A write to this register will start the conversion process.


CC CB CAAnalog Input

Channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7


Result Registers


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Result RegistersATDxDRXH & ATDxDRXL

The result of the A/D conversion are stored in the appropriate resultregister.

Since the A/D has a 10 bit word size the result is stored a 16 bit result

register made up of ATDxDRxH:ATDxDRxL in which the result is eitherright or left justified.

The results be read when the conversion is completed, this is signalled beither an A/D interrupt being triggered or the SCF bit in ATDxSTAT0 isset.


S f h A/D


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Status of the A/D

Finding out what the AD is doing is as simple as looking at the values inthe two status registers.


St t f th A/D


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Status of the A/D

ATDxSTAT0

SCF

0 means a conversion in progress

1 means all conversions are complete

ETORF

0 means no external trigger overrun has occurred.

1 means an external trigger overrun has occurred. FIFOR

0 means no FIFO overrun has occurred.

1 means a FIFO overrun occurred.

CC2 CC0 Channel number that just completed a conversion.

CC0CC1CC20FIFORETORF0SCF


St t f th A/D


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Status of the A/D

ATDxSTAT1

CCF7-CCF0 0 means conversion number X is yet to completed.

1 means conversion number X has completed.

CCF0CCF1CCF2CCF3CCF4CCF5CCF6CCF7


U i AN0 AN15 f Di i l I


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Using AN0-AN15 for Digital Input...

Each analog input pin can be individually switch from analog inputto digital input using the ATDxDIEN register.

ATDxDIEN

IENX 0 means the corresponding pin is used for analog input.

1 means the corresponding pin is used for digital input.

IEN0IEN1IEN6IEN7 IEN5 IEN4 IEN3 IEN2


U i AN0 AN15 f Di it l I t


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Using AN0-AN15 for Digital Input...

The digital byte can be read from the ATDxPTAD register.

ATDxPTAD (ATD1PTAD or ATD0PTAD0)

PTAD0PTAD1PTAD2PTAD3PTAD5PTAD6PTAD7 PTAD4


Using the A/D


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Using the A/D

There are two modes of operating the A/Dsystem

Polled Mode, or

Interrupt Mode


Polled Mode


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Polled Mode

Using polled mode requires the use of a spin lock.

Firstly the A/D system is configured as required:

It is enabled, the type and number of conversion configured, the triggering type

setup and the interrupts are disabled.

The conversion process is started by writing the desired value to ATD0CTL5.

The program then needs to wait until the conversion is complete before readingthe result.

The SCF flag in the ATD0STAT0 register is set once the conversion is complete.

So it will require a spin lock like

SPIN: BRCLR ATD0STAT0,$80, SPIN


Polled Mode


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Polled ModeExample

mainloop: JSR InitAD

MOVB #$00, ATD0CTL5

SpinLock: BRCLR ATD0STAT0,$80,SpinLock

LDD ATD0DR0H

....Spin BRA Spin

InitAD: MOVB #$80,ATD0CTL2 ; Turn on A/D Subsystem

LDX #820

DBNE X,* ; Delay a minimum of 100usMOVB #$E0,ATD0CTL2 ; Turn on A/D Subsystem,External Trigger and Interrupts

OFF

MOVB #$08,ATD0CTL3 ; One conversion, FIFO off

MOVB #$60,ATD0CTL4 ; Set Max sample time, 10 bit and Fast ATD Clock

RTS


Interrupt Mode


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Interrupt Mode

As with polled mode, the A/D system is configured as required:

It is enabled, the type and number of conversion configured, thetriggering type setup and the interrupts are enabled.

The conversion process is started by writing the desired valueto ATD0CTL5.

The program then needs to wait until the conversion is complete beforereading the result.

However it can continue on to another task and doesnt need to wait forthe result. The ISR will take care of processing the result for it once i isready.


Interrupt ModeE l


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Example

MOVB #$F7,IVBRmainloop: JSR InitAD

MOVB #$00, ATD0CTL5

Spin BRA Spin

InitAD: MOVB #$80,ATD0CTL2 ; Turn on A/D Subsystem

LDX #820

DBNE X,* ; Delay a minimum of 100us

MOVB #$E2,ATD0CTL2 ; Turn on A/D,External Trigger OFF and Interrupts ON

MOVB #$08,ATD0CTL3 ; One conversion, FIFO off

MOVB #$60,ATD0CTL4 ; Set Max sample time, 10 bit and Fast ATD Clock

RTS

ATDISR: LDD ATD0DR0H

....

RTI

ORG $FFD2 ; Set up Interrupt Vector Table

DC.W ATDISR ; ATD Vector


Need Further


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Assistance?

Ask your Demonstrator,

Post a question on the Forum, Email the Convener, or

Make an appointment.


topic10 introduction to the analog to digital subsystem on the freescale mc9s12x

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