topic08 introduction to the serial interfaces on the freescale mc9s12x

Serial Subsystems: Clocked or Unclocked...

Topic Video 088

1Thursday, 22 October 2009

Cereal Communications

How’s it going?

OK, Can’t Complain…


Serial Communication

• Even though the use of parallel communication seems more logical it does require the use of more external pins on the device.

• More pins means bigger IC packaging is required.• One of the advantages of serial communication is

the fact that it uses only a small number of pins.



• Serial I/O is the transmission of of data over a single communication line.

• The data is transmitted sequentially, one bit at a time.• This process requires a conversion of the data from a parallel

format to serial one.• The conversion process is achieved using a shift register on both

the transmitter when it is sent and on the receiver when it is received.

• Both shift registers are driven by a clock that can be either encoded into the signal or transmitted in parallel on a separate channel.


Serial CommunicationHow it Works...

Double Buffered, LSB first example.

Transmitter



$82


Transmitter



1 0 0 0 0 0 1 0


$64

Transmitter



1 0 0 0 0 0 1 0


$64Transmitter



1 0 0 0 0 0 1 0


0 1 1 0 0 1 0 0Transmitter



1 0 0 0 0 0 1 0


0 1 1 0 0 1 0 0

Transmitter




0 1 1 0 0 1 0 0

Receiver



1 0 0 0 0 0 1 0


0 1 1 0 0 1 0 0

Receiver



$82


0 1 1 0 0 1 0 0

Receiver



$82


0 1 1 0 0 1 0 0Receiver



$82


$64Receiver




$64

Receiver




Receiver



Double Buffered, MSB first example.

Transmitter



$82


Transmitter



1 0 0 0 0 0 1 0


$64

Transmitter



1 0 0 0 0 0 1 0


$64Transmitter



1 0 0 0 0 0 1 0


0 1 1 0 0 1 0 0Transmitter




0 1 1 0 0 1 0 0

Transmitter




Transmitter



1 0 0 0 0 0 1 0


Receiver



1 0 0 0 0 0 1 0


0 1 1 0 0 1 0 0

Receiver



1 0 0 0 0 0 1 0Double Buffered,

MSB first example.

0 1 1 0 0 1 0 0

Receiver



$82


0 1 1 0 0 1 0 0

Receiver



$82


0 1 1 0 0 1 0 0Receiver



$82


$64Receiver




$64

Receiver




Receiver



• There are two methods of serial communication:• Synchronous Serial Communication• Asynchronous Serial Communication


On-Chip Serial Devices

• The MC9S12XDP512 contains a large range of possible serial solutions, including:

• Six Asynchronous Serial Communications Interfaces (RS232), • Three Synchronous Serial Peripheral Interface (SPI), and• A single Synchronous Inter-Intergrated Chip (I2C) Interface.


Asynchronous Serial Communication

• A common form of Asynchronous Serial is RS232.• The receiver and transmitter have separate

independent local clocks.• The receiver phase locks its local clock to the

transmitter’s clock by detecting the start and end of a transmission.

TXRX

GND



• In asynchronous serial communication, the start of transmission is signified by a start bit. The start bit is a logical ‘1’.

• The end of transmission is represented by one or two stop bits. The stop bits are logical ‘0’.

DataStart bit Stop bits12Thursday, 22 October 2009


• Therefore at the start of a transmission there is a transition from ‘0’ to ‘1’. The receivers clock is phase aligned to the positive edge of this transition.

• The stop bit also acts as an error checking mechanism.

DataStart bit Stop bits



• An asynchronous serial transmission consists of one more additional element; the parity bit.

• Using this single parity bit it is possible to detect single bit errors.

P


Parity bit



• Via programmable registers it is possible to enable or disable the parity bit.

• Is also possible to set the parity bit to be even or odd parity.

P


Parity bit



Data



P

Data

Even Parity bit



P


Even Parity bit



Data



P

Data

Odd Parity bit



P


Odd Parity bit



• The communication rates for serial transmission are denoted by two terms:

• Characters per second (CPS): The rate at which 8 bit data is transmitted.• Baud rate (Baud): Frequency of the carrier used to transmit the data.

The relationship between CPS and Baud is

CPS = Baud ( Numberbits in Character + NumberStop bits + NumberStart bits + NumberParity bits)



• Full duplex or Half duplex?

• Full-duplex:

TX

RX

Two Channels



• Full duplex or Half duplex?

• Half-duplex:

One Channel


On-Chip RS232 Serial Devices

The six on Chip RS232 devices (SCI0 - SCI5) are provided through a number of different ports on the MC9S12XDP512.

SCI0 SCI1 PortS

SCI2 PortJ

SCI3 PortM

SCI4 SCI5 PortH


On-Chip RS232 Serial Devices

• The SCIs are full duplex asynchronous serial interfaces.

• Each with an independent on-chip baud rate generator .

• The receiver and transmitted are both double buffered, they use the same baud rate and frame format even though they operate independently.

• The SCI interface can send either 8 bit or 9 bit data.

• Each device is fully programmable and provides a variety of interrupt sources.


The Programmers ModelAll interaction with the SCIs is done via there I/O register set. (Note that the x in the register name should be replaced with device number [0-5])

SCIxACR1

SCIxACR2

SCIxBDH

SCIxBDL

SCIxSR1

SCIxSR2

SCIxASR1

SCIxCR2

SCIxCR1

SCIxDRH

SCIxDRL


The Programmers ModelThe I/O register for each device is located in a different area of the memory.

When referring to each register, the address of the register is shown relative to an offset.

Device OffsetSCI0 $00C8SCI1 $00D0SCI2 $00B8SCI3 $00C0SCI4 $0130SCI5 $0138


Controlling the SCI

SCIxCR1 (Offset + $02)

– LOOPS (Loop Select bit) • 0 means the SCI reciever is disconnected from the RX pin and

connect to the TX pin (useful for half-duplex).• 1 means TX and RX pins are used (Normal Operation).

– SCISWAI (SCI Stop in Wait Mode bit)• 0 means SCI operates normally in WAIT mode.• 1 means SCI is disabled in WAIT mode.

PTPEILTWAKEMRSRCLOOPS SCISWAI


Controlling the SCI


– RSRC (Receiver Source bit) • 0 means the receiver is connected to the transmitter internally.• 1 means Reciever is connected to TX pin, if LOOPS =1.

– M (Data Format Mode bit)• 0 means one start bit, eight data bits and one stop bit.• 1 means one start bit, nine data bits and one stop bit.

– WAKE (Wake up Condition bit)• 0 means idle line wake up (wake up once the line goes active).• 1 means address mark wake up (a ‘1’ in the MSB of a received

character is required to wake it up).



Controlling the SCI


– ILT (Idle Line Type bit) – Good for discovering it the line is idle for half duplex modes.

• 0 means Short Idle detect.• 1 means Long idle detect.

– PE (Parity Enable bit)• 0 means parity is disabled.• 1 means parity is enabled.

– PT (Parity Type bit)• 0 means even parity.• 1 means odd parity.



Controlling the SCI


– TIE (Transmitter Interrupt Enable bit) • 0 means interrupt source is disabled.• 1 means interrupt source is enabled.

– TCIE (Transmitter Complete Interrupt Enable bit) • 0 means interrupt source is disabled.• 1 means interrupt source is enabled.

– RIE (Receiver Interrupt Enable bit) • 0 means interrupt source is disabled.• 1 means interrupt source is enabled.

SBKRWURETEILIERIETCIETIE


Controlling the SCI


– ILIE (Idle Line Interrupt Enable bit) • 0 means interrupt source is disabled.• 1 means interrupt source is enabled.

– TE (Transmitter Enable bit) • 0 means Transmitter is disabled.• 1 means Transmitter is enabled.

– RE (Receiver Enable bit) • 0 means Receiver is disabled.• 1 means Receiver is enabled.



Controlling the SCI


– RWU (Receiver Wake Up Bit) • 0 means Receiver works normally.• 1 means the wake up function is enabled and prevents any further

receiver interrupt requests. Hardware can wake the receiver by clearing the RWU bit.

– SBK (Send Break bit) • 0 means no break character.• 1 means send break character ( a break character is 10 or 11 logical

‘0’s.



Controlling the SCI

SCIxACR1 (Offset + $01) (Requires AMAP bit in SCIxSR2 to be set)

– RXEDGIE (Receiver Active Edge Interrupt Enable bit) • 0 means RXEDGIF interrupt disabled.• 1 means RXEDGIF interrupt enabled.

– BERRIE (Bit Error Interrupt Enable bit)• 0 means BERRIF interrupt disabled.• 1 means BERRIF interrupt enabled.

– BKDIE (Break Detect Interrupt Enable bit)• 0 means BKDIF interrupt disabled.• 1 means BKDIF interrupt enabled.

BKDIEBERRIE00000RXEDGIE


Controlling the SCISCIxACR2 (Offset + $02) (Requires AMAP bit in SCIxSR2 to be set)

– BERRM[1:0] (Bit Error Mode) • These bit determine the functionality of the Bit Error Detect

feature.

– BKDFE (Break Detect Feature Enable)• 0 means Break Detect Circuit is disabled.• 1 means Break Detect Circuit is enabled.

BKDFE00000 BERRM1 BERRM0


Controlling the SCISCIxBDH (Offset + $00)

SCIxBDL (Offset + $01)

– IREN (Infrared Enable bit) • 0 means IR is disabled.• 1 means IR is enabled.

– TNP[1:0] (Transmitter Narrow Pulse)• Set the Narrow Pulse width for IR.

– SBR[12:0] (SCI Baudrate bits)• when IREN = 0, SCI Baudrate = SCI bus clock / (16 * SBR[12:0])• when IREN = 1, SCI Baudrate = SCI bus clock / (32 * SBR[12:1])

SBR8SBR9SBR10SBR11TNP0TNP1IREN SBR12

SBR0SBR1SBR2SBR3SBR4SBR5SBR6SBR7


Status of the SCI

SCIxSR1 (Offset + $04)

– TDRE (Transmit Data Register Empty flag) • 0 means no data was moved from the data register to the shift

register.• 1 means data has moved to shift register, leaving the data register

empty.– TC (Transmit Complete flag)

• 0 means the transmitter is active.• 1 means all data has been transmitted, both the data and shift

registers are empty.

PEFENFORIDLERDRFTCTDRE


Status of the SCI


– RDRF (Receive Data Register Full flag) • 0 means the receive data register is empty.• 1 means the receive data register has received new data.

– IDLE (IDLE line flag)• 0 means the receiver input is active or hasn’t been active since the

IDLE flag was cleared .• 1 means the receiver input is idle.



Status of the SCI


– OR (Overrun flag) • 0 means no overrun error has occurred.• 1 means an overrun error has occurred, due to data no being read

for the receive register before it was overwritten.– NF (Noise flag)

• 0 means no noise.• 1 means there is noise on the receiver input.



Status of the SCI


– FE (Framing Error flag) • 0 means no framing error occurred.• 1 means a framing error occurred (the stop bit wasn’t detected

properly).– PE (Parity Error flag)

• 0 means no parity error occurred.• 1 means there was a parity error.



Status of the SCISCIxSR2 (Offset + $05)

– AMAP (Alternative Map) • 0 means the registers SCIxBDL, SCIxBDH and SCIxCR1 are

available.• 1 means the registers SCIxASR1, SCIxACR1 and SCIxACR2 are

available.– TXPOL (Transmitter Polarity)

• 0 means normal polarity.• 1 means inverted polarity.

RAFTXDIRBRK13RXPOL00AMAP TXPOL


Status of the SCI


– RXPOL (Receiver Polarity) • 0 means normal polarity.• 1 means inverted polarity.

– BRK13 (Break Transmit Length)• 0 means 10 to 11 logical ‘0’s are sent.• 1 means 13 to 14 logical ‘0’s are sent.



Status of the SCI


– TXDIR (Transmitter Pin Data Direction in Single Wire Mode) • 0 means input.• 1 means output.

– RAF (Receiver Active Flag)• 0 means no reception in progress.• 1 means reception in progress.



Status of the SCISCIxASR1 (Offset + $00)

– RXEDGIF (Receiver Edge Active Input Flag) • 0 means no active edge has been detected on the receiver.• 1 means an active edge has been detected on the receiver.

– BERRV (Bit Error Value)• 0 means a low input was sampled when a high input was expected.• 1 means a high input was sampled when a low input was expected.

– BERRIF (Bit Error Interrupt Flag)• 0 means no mismatch occurred.• 1 means a mismatch occurred.

BKDIFBERRIFBERRV0000RXEDGIF


Controlling the SCI

SCIxDRH (Offset + $06)

– R8 (Receiver Bit 8) • When the SCI is used in 9bit mode this is the location for the 9 bit

from the receiver.– T8 (Transmitter Bit 8)

• When the SCI is used in 9bit mode this is the location for the 9 bit to be transmitted (this bit must be set prior to setting the lower eight bits).

000000T8R8


Controlling the SCI

SCIxDRL (Offset + $07)

– R[7:0] (Receiver Data Register) • Data that has been recieved by the SCI device is stored in this

register.– T[7:0] (Transmitter Data Register)

• Data written to this register is transmitted out of the SCI device.

This memory address is a window to two register when reading from this address it refers to the receiver’s data register. When writing to this address the memory location refers to the transmitter’s data register.

R0/T0R1/T1R2/T2R3/T3R4/T4R5/T5R6/T6R7/T7


On-Chip RS232 Serial Device


Using the SCI Device

• Before the SCI can be used it must first be initialized, so we firstly need to ask some questions.• What are the communication characteristics?• Baudrate, bit format, parity• Single wire (half-duplex) or Two wire (full-

duplex)• Will my use of the SCI be interrupt driven or

will I use polled mode?• The control registers need to be set to reflect

these decisions.


Using the SCI Device

• Once the SCI has been initialized, you then want to use it to send or receive data.

• Since the SCI device is slower than the uP we need to ensure the data register of the SCI is empty before writing a new value to it.

• This will require us to check the TDRE flag in SCIxSR1, and ensure it is set before writing a second value to register.

• Also before reading a value from the register we need to ensure that new data has arrived.

• This means we will have to check that the RDRF flag is set in SCIxSR1 before reading the data register.


SCI Example

Entry: LDS #RAMEnd+1 ; initialize the stack pointer CLI ; enable interruptsmainLoop: JSR InitSCI ; Initialize the SCI LDAB #’A’ ; print a ‘A’ JSR PutChar LDAB #$0D ; print a newline ('\n') JSR PutCharSpin: BRA Spin ; while(1);

Serial_Base EQU $00d0 ; Use the auxiliary serial port INCLUDE 'Serial.inc' ; similar to #include<stdio.h> in C

main.asm


SCI Example

;Requires that Serial_base be set in main assembly file;Register definesSCISR1 EQU Serial_Base + $04SCISR2 EQU Serial_Base + $05SCICR1 EQU Serial_Base + $02SCICR2 EQU Serial_Base + $03SCIBDH EQU Serial_Base + $00SCIACR1 EQU Serial_Base + $01SCIACR2 EQU Serial_Base + $02SCIDRL EQU Serial_Base + $07;Bit definesAMAP EQU $80TDRE EQU $80RDFR EQU $20;Register SettingsSCIControl1 EQU $00 ;8 bit, no paritySCIControl2 EQU $0CBaudrate EQU 52 ;Set Baudrate to 9600

Serial.inc


SCI Example

InitSCI: BSET SCISR2,AMAP MOVB #0,SCIACR1 MOVB #0,SCIACR2 BCLR SCISR2,AMAP MOVB #SCIControl1,SCICR1 MOVB #SCIControl2,SCICR2 MOVW #Baudrate,SCIBDH RTS

PutChar: BRCLR SCISR1,TDRE,* STAB SCIDRL RTS

Serial.inc


Interrupt Driven Serial Communication

– In situations were you need fast response to serial events, it is best to use the interrupt mechanism.–Each serial device has a single interrupt line associated

with it.–This interrupt can be triggered under four possible

conditions:–The transmit buffer is empty (TIE)–The serial transmission is complete (TCIE),–The receive buffer is full (RIE), or–The line is idle (ILIE)



– In situations were you need fast response to serial events, it is best to use the interrupt mechanism.–Each serial device has a single interrupt line associated

with it.–This interrupt can be triggered under four possible

conditions:–The transmit buffer is empty (TIE)–The serial transmission is complete (TCIE),–The receive buffer is full (RIE), or–The line is idle (ILIE)

Used during half duplex operation



–Depending on when you want the interrupt to be triggered you should set the appropriate interrupt enable bit in the SCIxCR2 register. –You should also enable the global maskable interrupt

subsystem by clearing the I bit in the CCR.–Create an ISR and insert the appropriate vector into

the vector table location for the serial subsystem you are using.


Synchronous Serial Communication

–Uses a common clock to synchronize the receiver with the transmitter.–Requires a separate line to carry the clock signal.– SPI and I2C are two common forms of Synchronous

Serial.

TX

RX

GNDClock

Master Slave


• The Serial Peripheral Interface is a form of synchronous serial communication.

• SPI is a high speed interface capable of transmitting and receiving data up to a rate of 12.5 Mbits/second.

• SPI is an interface that is available on many devices including:• MCUs• I/O devices• Memories devices



Synchronous Serial Communication - SPI

• SPI is synchronous therefore both the receiver ad transmitter are driven by the same clock source.

• SPI has a physical interface that consists of four pins:• MOSI• MISO• SCLK• SS

MOSIMISO

GND

SCLKMaster Slave

SS


Synchronous Serial Communication - SPI• When two SPI capable devices are connected together, they

need to synchronize their shift registers, This is done by using the same clock to drive both shift registers.

• But they both can’t generate the clock.• One of the SPI devices becomes the master and the other

device becomes the slave.• The master generates the clock signal and therefore controls

the transfer of information on this interface.

MOSIMISO

GND

SCLKMaster Slave

SS



• The Role of the Master

• The master generates the clock for both itself and the slave devices.

• The master controls when the slave can send and receive information.

• The Role of the Slave

• Just does what the master tells it to do...



• Single Buffered

• The data register is the actual shift register responsible for serial conversion.

• Has a single status flag to show when a transmission is complete.


Synchronous Serial Communication - SPISingle Buffered Example

The connection between the master and slave SPI devices

Data Register

ClockSource

Master Slave

MOSI

MISO

SCLK

Shift RegisterShift Register

SS

Data Register




ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register Shift RegisterData Register

SS

SingleBuffered

Data Register



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift RegisterData Register

Shift Register

10110010

00010011Data Register

SS




ClockSource

Master Slave

MOSI

MISO

SCLK


Shift Register

1011001000010011

Data Register

Transmission Complete

Flag

SS

10110010


00010011



ClockSource

Master Slave

MOSI

MISO

SCLK


Shift Register

10110010

00010011Data Register

SS


(a second time)



ClockSource

Master Slave

MOSI

MISO

SCLK


Shift Register

1011001000010011

Data Register


Flag

SS

10110010


(a second time)

00010011



• Double Buffered

• There are two data registers, one writing and one for reading. When a transmission is complete the data in the shift register is moved in the receive data register and the data from the transmit data register is copied into the shift register.

• Has two flags; one to show when a transmission is complete, a second flag to show if the transmit data register can be written to.



Data Register Data Register

ClockSource

Master Slave

MOSI

MISO

SCLK


Shift Register

Data Register

SS

Synchronous Serial Communication - SPIDouble Buffered Example




ClockSource

Master Slave

MOSI

MISO

SCLK


Shift Register

Data Register

SS

DoubleBuffered





ClockSource

Master Slave

MOSI

MISO

SCLK


Shift Register

Data Register

SS




ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


00010011



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


Data Register Empty

Flag

00010011



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


1011001000010011


Flag



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


00010011



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


(a second time)

00010011



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


(a second time)

Data Register Empty

Flag

00010011



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


(a second time)

1011001000010011


Flag



ClockSource

Master Slave

MOSI

MISO

SCLK

Shift Register

Data Register

Shift Register

Data Register

SS


(a second time)

00010011


• The three SPI subsystems provided on the MC9S12XDP512 have the following features:

• Double buffered,

• Capable of a maximum SPI clock speed of 4MHz at the default system clock of 8MHz,

• Master or Slave modes,

• Slave Select Output

• Serial clock, with programmable speed, phase and polarity

• Bidirectional mode

Synchronous Serial Communication - SPIThe MC9S12XDP512’s SPI Subsystem


The Programmers ModelAll interaction with the SPIs is done via there I/O register set. (Note that the x in the register name should be replaced with device number [0-2])

SPIxBR

SPIxSRSPIxCR2

SPIxCR1

SPIxDR


Controlling the SPI

• SPIE (SPI Interrupt Enable) :• 0 means SPI Interrupts are inhibited.• 1 means hardware interrupt is requested each time the SPIF or MODF

status flag is set.• SPE (SPI System Enable):

• 0 means SPI internal hardware is initialized and SPI system is in a low power disabled state.

• 1 means SPI is enabled and IO pins are dedicated to the SPI function.

LSBFESSOECPHACPOLMSTRSPTIESPESPIESPIxCR1


Controlling the SPI

• SPTIE (SPI Transmit Interrupt Enable bit):0 means SPTEF interrupts are disabled.1 means SPTEF interrupts are enabled.

• MSTR (SPI Master/Slave Mode Select) :0 means Slave Mode1 means Master Mode



Controlling the SPI


• CPOL, CPHA (SPI Clock Polarity, Clock Phase):These two bits are used to specify the clock format to be used in SPI

operations. When the clock polarity bit (CPOL) is cleared and data is not being transmitted the SCLK line idles low. When CPOL is set the SCLK line idles high.

• SSOE (Slave Select Output Enable):

The SS output feature is enabled only in master mode by asserting the SSOE and DDS7.


• LSBFE (SPI LSB First Enable bit):0 = Data is transferred most-significant bit (MSB) first.

1 = Data is transferred least-significant bit (LSB) first.

The setting of this bit does not alter the location of the MSB in the data register.

Controlling the SPI



SPI Clock Format

SPI Clock Format 0 CPHA=0 SPI Clock Format 1 CPHA=1

Controlling the SPI



Controlling the SPI

SPC00000SPIxCR2

• MODFEN (Mode Fault Enable bit):

• This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN.

• 0 means SS port pin is not used by the SPI device.

• 1 means SS port pin with MODF feature.

MODFEN BIDIROE SPISWAI


Controlling the SPI

SPC00000SPIxCR2

• BIDIROE (Output Enable in Bidirectional Mode of Operation):

• This bit controls the operation of the output buffer when bidirectional mode is set (SPC0=1).

• 0 means output buffer is disabled.

• 1 means output buffer enabled.



Controlling the SPI

SPC00000SPIxCR2

• SPISWAI (SPI Stop in Wait mode):

• This bit controls the behaviour of the SPI device when in WAIT mode.

• 0 means SPI clock operates normally.

• 1 means SPI clock is disabled.



Controlling the SPI

SPC00000SPIxCR2

• SPC0 (Serial Pin Control bit 0):

• This bit enables bidirectional pin configuration.



Controlling the SPI

SPR0SPR1SPR20SPPR1SPPR20SPIxBR

• SPPR[2:0] (SPI Baud Rate Preselection bits):These bits specify the baud rate.

• SPR[2:0] (SPI Baud Rate Selection bits):These bits also specify the baud rate.

Baud rate divisor = (SPPR + 1) 2 (SPR+1)

Baudrate = Bus Clock / Baud rate divisor

SPPR0


• SPIF (SPI Interrupt Request Flag):SPIF is set after the eighth SCK clock cycle in a data transfer, and it is

cleared by reading the SPIxSR register (with SPIF set) followed by an access (read or write) to the SPIxDR data register.

• SPTEF (SPI Transmit Empty Interrupt Flag):This bit indicates if the transmit data register is empty.0 means register is not empty.1 means it is empty.

0000MODF0SPIFSPIxSR

Controlling the SPI

SPTEF


• MODF – SPI Mode Error Interrupt Status Flag:This bit is set automatically by SPI hardware, if the MSTR control bit is set

and the slave select input pin becomes ‘0’. This condition is not permitted in normal operation. In the case of SPI0 where DDRS bit 7 is set, the PS7 pin is a general-purpose output pin or SS output pin rather than being dedicated as the SS input input for the SPI system. In this special case, the mode fault function is inhibited and MODF remains cleared. This flag is cleared automatically by a read of the SPIxSR (with MODF set) followed by a write to the SPIxCR1 register.

0000MODF0 SPTEFSPIFSPIxSR

Controlling the SPI


• SPD7-0 SPI Data:Data written to this register is serially transmitted via the SPI port, data

received by the SPI port is made available through this register also. Data written to this register will not overwrite data received by the SPI port.

SPD0SPD1SPD2SPD3SPD4SPD5SPD6SPD7SPIxDR

Controlling the SPI



Block Diagram of the Serial Peripheral Interface


Using the SPI device

• When using the SPI subsystem, you need to ask yourself some questions:

• Who is the Master, who is the slave?

• What is the speed of communication?

• What is the clock format?

• What size is the slaves buffer?


Example

• Application example were two MC9S12XDP512s are connected together.

MOSIMISOSCLK

SS


ExampleMaster Code

SPIF: EQU %10000000SPTEF EQU %00100000SPE: EQU %01000000MSTR: EQU %00010000SS: EQU %10000000SMASK EQU %11100000SPISETUP EQU MSTR|SPE ...MainLoop: JSR INITSPI

BSET PORTS,SSBRCLR SPI0SR,SPTEF,* ; Wait until Data register is empty

MOVB #43,SPI0DR ; Write $43 to SPI Data Register BRCLR SPI0SR,SPIF,* ; Wait until Data is shifted

LDAB SPI0DR ; Reset SPIF BCLR PORTS,SS ;Select Slave HC912

Spin: BRA Spin

INITSPI: MOVB #SMASK,DDRS ;Set Port S bits 7-5 for output. MOVB #SPISETUP,SPI0CR1 ;Enable SPI in master mode MOVB #0,SPI0CR2 ;Normal SPI mode MOVB #$00,SPI0BR ;Set up the clock rate to be max.

RTS


ExampleSlave Code

SPIF: EQU %10000000SPE: EQU %01000000SS: EQU %10000000SMASK EQU %000100000SPISETUP EQU SPE ...MainLoop: JSR INITSPI BRCLR SPI0SR,SPIF,* BRSET PORTS,SS,* ;Select Slave HC912 LDAA SPI0DR

Spin: BRA Spin

INITSPI: MOVB #SMASK,DDRS ;Set Port S bits 7-5 for input. MOVB #SPISETUP,SPI0CR1 ;Enable SPI in slave mode MOVB #0,SPI0CR2 ;Normal SPI mode MOVB #$00,SPI0BR ;No effect, since it is a slave.

RTS



• The popularity of SPI is increasing, and it becoming a standard feature on all MCUs.

• Many peripherals are also SPI enabled, including: • Digital-to-Analog Converters• Analog-to-Digital Converters• LCD Displays• RAM / ROM chips• Protocol Conversion Devices (SPI to RS232)‏• And many more…


Need Further Assistance?

• Ask your Demonstrator,

• Post a question on the Forum,

• Email the Convener, or

• Make an appointment.


topic08 introduction to the serial interfaces on the freescale mc9s12x

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