Tools for synthesis and implementationusing Xilinx FPGAs

Synthesis ToolflowHDL DesignerSynplify ProLeonardo SpectrumDesignSynthesisImplementationISE Project NavigatorVHDL codeNetlistBitstreamXST

Synthesis stagesHigh level synthesis TechnologyindependentTechnologydependentLow level synthesis CompileMapPlace & RouteImplement Code analysis- Derivation of main logic constructions Technology independent optimization Creation of RTL View Mapping of extracted logic structures to device primitives Technology dependent optimization Application of synthesis constraintsNetlist generation Creation of Technology View Placement of generated netlist onto the deviceChoosing best interconnect structure for the placed designApplication of physical constraints Bitstream generation Burning device

Synthesis stagesHigh level synthesis TechnologyindependentTechnologydependentLow level synthesis CompileMapPlace & RouteImplement

Why we need third-side synthesis tool?Support of larger VHDL subsetMore and better optimizationsMore stable synthesisControl and management of synthesis process more user-friendly and simplerCan be used for different technologiesPossibility of working with number of revisions in parallelAdvanced synthesis techniquesAnd more

Main TopicsLecture schedule:Introduction to synthesis tools (Synplify and Leonardo) Environments, constraints, timing analysis, optimizationsIntroduction to Place & Route tools Environments, pin assignment, timing information extraction (Advanced analysis tools for FPGAs)Using IMPACT burning toolTiming simulation

Introduction to synthesisSynplify Pro synthesis tool

Tool invocationInvocation of Synplify Pro performed by double click on Synplify PRO flow in Team tasks or by pressing button in toolbarSynplify Pro invocation linkSynplify Pro invocation button

Tool tuningWorking directory for Synplify is one defined in Downstream in HDL DesignerFor each revision new directory is created and all Synplify-generated files are placed thereIn case of using CoreGen, netlist generated by Coregen placed in Synplify working directory and not in appropriate revision directory. Copy it to revision directoryTo avoid errors caused by embedded configurations, make them standalone by:

Synplify Pro main windowWindow with source filesWindow with result filesMessages, warnings and errorsWatch windowMain optimization modesStatus lineWorking with filesStart synthesisWorking with revisions

Understanding list of source filesIf you have also Verilog files, separate directory will be createdIn such case, main block of the design must be defined in another placeNumber of revision (version)The main entity should be last in the list of filesIf you use package(s), put it first in the list of files

Compilation processCompilation is the first stage of synthesis processThere is a possibility to invoke compilation only (without mapping) by choosing Run->Compile only or pressing F7After compilation Synplify main window looks like this:Show RTL viewSome files were generated

Understanding report fileAll errors, warnings and notes reported during compilation, are written to .srr file This file can be viewed by double click on its name in right window or pressing View Log button on the left side of the main windowEach error message started from @E and colored to redEach warning message started from @W and colored to violetEach note message sarted from @N and colored to blueCrossprobing makes possible viewing problematic code by simple double click on errror/warning/note message

Understanding RTL viewRTL view can be opened by pressing or double click on .srs fileMUX incrementercomparatorThe group of buttons is useful in RTL view windowGeneral logic structures can be recognized on RTL view

Crossporbing between RTL view and codeEach port, net or block can be chosen by mouse click from the browser or directly from the RTL ViewBy double-clicking on the element its source code can be seen:Reverse crossprobing is also possible: if section of code is marked, appropriate element of RTL View is marked too:

Understanding FSM ViewerCrossprobing is possible between graphical representation of FSM and its states / transactions listSynplify Pro has feature to show state machines in graphic form (like HDL Designer). The feature is invocated by indicating V for FSM Compiler optionInitial statesCoding of states after compilationCoding of states after mapping

Mapping process Compilation of design is not enough to complete high level synthesis we need to perform also mappingMapping is technology dependent stage of synthesisDuring mapping, excluding mapping itself, are performed the next processes:Application of synthesis constraintsGeneration of netlistInitial timing analysisGeneration of Technology ViewHDL source filesCompiled (RTL) netlist Mapped netlist (edif)CompilationMappingRTL viewSynthesis constraintsTo place & routeTechnology viewPost map timing analysis

Defining device parametersAll mapping parameters defined via implementation options windowThe window is opened by pressing button or by double-click on current revisionThe first step is choosing device for implementationDevice-specific mapping options can apply different optimizationsStand on specific option and press F1 to learn more about it

Defining compilation optimizationsCompilation optimizations can be defined in Options tabThe same optimizations can be invoked from the main Synplify window

Defining constraint files to be appliedGlobal frequency and constraint files can be defined in the next tab Constraints (we will see constraint files later)

Defining result filesLocation of result files created after mapping process can be defined in the tab Implementation resultsAdditional files can be created:Post-map netlist in HDL format for post-map timing simulationPhysical constraints file for P&R tools Important note: to prevent problems with low-level sythesis tools, the name of result netlist (edif file) should be similar to the name of the top design entityPost map netlist in HDL formatP&R constraint file

Timing report definitionsTiming report form can be configured by specifying number of reported critical paths or/and start/end points

Synthesis constraints specification - SCOPESCOPE (Synthesis Constraint Optimization Environment) is graphical tool for defining different (mainly timing) constraintsThe output of SCOPE is the synthesis constraint file (.sdc) which is attached to RTL netlist and applied during mapping stageSCOPE is invoked by pressing button or by specifying File->New->Constaint FileMain window of SCOPE divided to tabs by constraint types

Types of synthesis constraintsThe groups of constraints are:Clocks defining design clocks form and frequency, groups of clocks, there is possibility to define part of period intended to routing delayClock to clock defining relations between clocksInput / output delays defining propagation delays of input (Input port -> FF) or output (FF -> Output port) pathsRegisters defining setup times and propagation delays of FFsPaths constraintsMulti-cycle paths between FFs in which signal is allowed to be propagated in more than one clockFalse paths which is not required to be analyzed Max-delay paths constrained to certain delay valueAttributes additional (non-timing) constraintsBlack box definitionsObject pruning preventionExcluding code for synthesisAnd more

Mapping invocationMapping (including compilation) is invocated by pressing F8 , choosing Run->Synthesize or by pressing Showing Technology ViewNumber of files were createdErrors and warnings can appear

Understanding of Technology ViewTechnology view is mapped RTL view. It can be seen by pressing button or by double-click on .srm fileAs in case of RTL View, buttons can be used here

Two additional buttons are enabled: - show critical path - open timing analystTechnology view is presented using device primitivesPorts, nets and blocks browserPay attention: technology view is usually large and presented on number of sheets

Viewing critical path Critical path can be viewed by pressing on

Slack and delay values are written near each component of the path

Timing AnalystTiming analyst opened by pressing on Timing analyst gives a possibility to analyze different paths in the designTiming analyst can be opened only from Technology View

Timing reportTiming report is part of general report file .srrDo search of START OF TIMING REPORT in .srr file to get itNext things can be found in this report:General design information name, included constraint files, required frequency, required number of critical paths to be reported Performance summary achieved frequency, worst slackClock relationship table with rise to rise, rise to fall, fall to rise and fall to fall delays for each pair of clock groupsInterface information standing in requirements for input / output delays Detailed report for each clock group of the design, including:Table with all most critical path for this clock groupTable with all start / end points for critical paths for this clock groupSeparate table of signal propagation for each critical path

Working with number of revisionsSynplify gives a possibility to create number of revisions of the design, to synthesize them and compare. The most used options are:Creation of new revision of the same design with the same constraints but for another technologyCreation of new revision of the same design with different constraints for another technologyNew revision can be created by pressing on or by choosing Project -> New Implementation New revision automatically accepts new revision numberCurrent revision is marked by green arrowAll revisions can be synthesized by choosing Run->Run All Implementations

Introduction to synthesisLeonardo Spectrum synthesis toolbriefly

Tool invocationInvocation of Leonardo Spectrum performed by double click on Leonardo Spectrum flow in Team tasks or by pressing button in toolbarLeonardo Spectrum invocation linkLeonardo Spectrum invocation button

Tool invocationThe window for fast start is opened after invocation:

Leonardo definitionsThere are two types of menus:Quick setup perform synthesis defining minimal set of optionsAdvanced flow tab this tab includes options to define constraints, form of reports and invocation of P&R toolsSwitching between two menus perfomed by:

Quick setup windowThere is quick setup window:

Advanced flow tabAdvanced flow tab facilitates synthesis in steps:In addition there is also Synthesis Wizard, which passes via all above tabs one-by-one

Analysis of synthesis results

Adding constraints

High-level synthesis conclusionsTo obtain good synthesis results, always follow the next rules:Write understandable HDL code. Think hardware, not software!Analyze report file after compilation and after mapping: - did you mean to make RAM here? - does this register really redundant? - why black box is created?Especially pay attention to recognized clocks and generated latchesUse FSM Compiler to analyze derived FSM and compare them to ones drawn in HDL designerAnalyze inserted buffers in Technology ViewApply optimizations carefullyUse synthesis constraints to tune the design and estimate timingFollow file naming conventions to avoid problems in low-level synthesis tools

Introduction to place and route toolsXilinx Project Navigator P&R tool

Reminder - synthesis stagesHigh level synthesis TechnologyindependentTechnologydependentLow level synthesis CompileMapPlace & RouteImplement Code analysis- Derivation of main logic constructions Technology independent optimization Creation of RTL View Mapping of extracted logic structures to device primitives Technology dependent optimization Application of synthesis constraintsNetlist generation Creation of Technology View Placement of generated netlist onto the deviceChoosing best interconnect structure for the placed designApplication of physical constraints Bitstream generation Burning deviceWE ARE HERE

Tool invocationFrom Synplify:From Leonardo:

But, there is a problemWhen running from Synplify:ISE project is created, but Project Navigator is not openedWhen running from Leonardo:Project Navigator is opened, but project is not createdSo, if you use Synplify:Try to run Project Navigator (it will create the project), and after that invoke tool from WindowsIf you use Leonardo:Open Directly Project Navigator from the Windows

Project Navigator main windowSource filesSynthesis processesLog window errors, warnings and notesResults window

Creation of new projectIf you work with Leonardo, you have to create new project firstlyNew Project is created by File->New ProjectProject directory not necessary have to be output directory of high-level synthesis toolEDIF must be chosen as top-level module typeAfter choosing press next

Creation of new projectEDIF file created after high-level synthesis should be entered as input designAll netlists created by external tools (such as CoreGen) should be placed in the project directory together with main netlistIf you want your netlist will not be affected by high-level resynthesis, specify copy input design to the project directory (relevant if your project directory differs from output directory of high-level synthesis tool) We will discuss further the constraint filePress next

Creation of new projectVerify that you use right device and Modelsim simulatorPress Next and then Finish

Opening existing projectOpen existing project (when working with Synplify) by:File -> Open Project and further choosing .npl file

Understanding project viewAfter creation or opening, design file(s) (netlist) displayed in the left top windowPossible processes displayed in the left bottom windowProcess can be invoked by double-clicking on its nameWhen you invoke the process, the tool performs check and invokes previous processes if needed

But:Before place & route starts, we have to define physical constraints file

Physical constraints fileReminder toolflow: Compiled (RTL) netlist Mapped netlist (edif)MappingSynthesis constraintsPlace & routeTechnology viewPost map timing analysisPlaced and routed netlist (ncd)Physical constraintsBitstream (bit)Routed design viewPost P&R timing analysisPhysical constraints file (.ucf) must me provided to perform Place & Route in the right wayThis file is necessary for pin assignment, because it attaches physical device pins to design external ports (in contrast with synthesis constraints file that is not necessary to produce right implementation)

Physical constraints fileCreation of new constraints file:Choose nameChoose design file constraints file attached toNew constraints file is added under defined design file

Physical constraints fileConstraint file can be edit by several ways:Using special programs for constraints

Or by editing constraints file directlyThe latter way is preferred (more simple)You can use reference constraints file and just to change pin assignments relevant for your design (can be found at Q:\Virtex II PRO\constraints file)Constraint file has very simple structure and looks like this:NET + name of the port in the designLOC + name of the FPGA pinNames of pins can be found at:Q:\Virtex II Pro\development board\user_guide

Extraction of timing informationReminder toolflow:Mapped netlist (edif)Place & routePlaced and routed netlist (ncd)Physical constraintsBitstream (bit)Post P&R timing analysisHDL source filesPost P&R timing simulation modelTiming simulationTiming simulation is required to check if the design works right with real delay values (post Place & Route timing simulation model)Non standing of design in real timing can cause changing of HDL source filesInformation for timing simulation is extracted from Project Navigator

Extraction of timing informationTo accept files for timing simulation:Choose Modelsim VHDL for Simulation Mode targetChoose right device speedPress OK and double click on Generate post Place & Route Simulation Model to invokeTwo files are created : design name_timesim.vhd VHDL description of netlist design name_timesim.sdf file with timing informationWe will see later how to use these files

Burning device - IMPACTDouble-click on Generate programming file to generate bitstream for downloading (.bit file)The tool will invoke all required previous processes Burning of FPGA is executed by IMPACT tool

Burning device - IMPACTWhen starting, IMPACT will display wizard which will guide you through the programming processAttention: download cable should be connected and board power on before running IMPACT !If there are no problems with JTAG, 3 devices are recognized on the board:First two devices are on-board PROMS, we are not interested in them (press Cancel twice)Virtex II PRO is the third in the JTAG chain of the board

Burning device - IMPACTRight click on Virtex II PRO and select Assign new configuration fileSelect required .bit file and press OpenRight click on Virtex II PRO and select ProgramPress OK device will start programming:

Timing Simulation

Placing timing simulation files into HDL designerDuring P&R we have accepted two files:.vhd containts HDL description of netlist.sdf containts timing information These files will be used in HDL Designer for timing simulation

Firstly, add HDL netlist, as External IP:This block will replace the old one in test bench architecture

Placing timing simulation files into HDL designerNow, start Modelsim by When start window opens, add command for loading .sdf file -sdftyp / = is hierarchical path to instance of HDL netlist, where hierarchical levels separeted by / file is Windows path to .sdf file, where / is used (instead of conventional \)

Advanced analysis tools - FloorplanerThere are several tools giving a possibility to analyze design deeperFloorplaner displays placed designYou can check where each block of the design was placedPlacing can be changed by specifying appropriate physical constraints

Advanced analysis tools FPGA EditorFPGA Editor displays placed and routed designImplementation of each cell can be viewed

Advanced analysis tools Power EstimatorPower estimator calculates power consumed by the design, activity factors and average current values