tomasulo algorithmlecture 11: case study—ricardo/courses/advtopcompsys/material/tomasulo... ·...

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Lecture 11: Case Study—Tomasulo Algorithm

Professor Randy H. KatzComputer Science 252

Fall 1995

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Review: Scoreboard Summary

• Speedup 1.7 from compiler; 2.5 by hand BUT slow memory (no cache)

• Limitations of 6600 scoreboard– No forwarding– Limited to instructions in basic block (small window)– Number of functional units(structural hazards)– Wait for WAR hazards– Prevent WAW hazards

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Another Dynamic Algorithm: Tomasulo Algorithm

• For IBM 360/91 about 3 years after CDC 6600• Goal: High Performance without special compilers• Differences between IBM 360 & CDC 6600 ISA

– IBM has only 2 register specifiers/instr vs. 3 in CDC 6600– IBM has 4 FP registers vs. 8 in CDC 6600

• Differences between Tomasulo Algorithm & Scoreboard– Control & buffers distributed with Function Units vs. centralized in

scoreboard; called “reservation stations”– Registers in instructions replaced by pointers to reservation station

buffer– HW renaming of registers to avoid WAR, WAW hazards– Common Data Bus broadcasts results to all FUs– Load and Stores treated as FUs as well

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From instruction unit

Floating-pointoperations

Frommemory

Load buffersFP registers

Store buffers

To memory

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2

1

Reservationstations

FP adders FP multipliers

321

21

Common data bus (CDB)

Operation bus

Operandbuses

LoadBuffer

FPRegisters

FP Op Queue

StoreBuffer

FP AddRes.Station

FP MulRes.Station

CommonDataBus

Tomasulo Organization

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Reservation Station Components

Op—Operation to perform in the unit (e.g., + or –)Qj, Qk—Reservation stations producing source registers Vj, Vk—Value of Source operandsRj, Rk—Flags indicating when Vj, Vk are ready

Busy—Indicates reservation station and FU is busy

Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register.

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Three Stages of Tomasulo Algorithm

1.Issue—get instruction from FP Op Queue If reservation station free, the scoreboard issues instr &

sends operands (renames registers).

2.Execution—operate on operands (EX) When both operands ready then execute;

if not ready, watch CDB for result

3.Write result—finish execution (WB) Write on Common Data Bus to all awaiting units;

mark reservation station available.

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Tomasulo Example Cycle 0

Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 Load1 NoLD F2 45+ R3 Load2 NoMULTDF0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Time Name Busy Op V j Vk Qj Qk0 Add1 No0 Add2 No

Add3 No0 Mult1 No0 Mult2 No

Register result status

Clock F0 F2 F4 F6 F8 F10 F12 ... F300 FU

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 Load1 No 34+R2LD F2 45+ R3 Load2 NoMULTDF0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k




Clock F0 F2 F4 F6 F8 F10 F12 ... F301 FU Load1

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 Load1 Yes 34+R2LD F2 45+ R3 2 Load2 Yes 45+R3MULTDF0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k




Clock F0 F2 F4 F6 F8 F10 F12 ... F302 FU Load2 Load1

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 Load1 Yes 34+R2LD F2 45+ R3 2 Load2 Yes 45+R3MULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k


Add3 No0 Mult1 Yes MULTD R(F4) Load20 Mult2 No


Clock F0 F2 F4 F6 F8 F10 F12 ... F303 FU Mult1 Load2 Load1

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 Load2 Yes 45+R3MULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Time Name Busy Op V j Vk Qj Qk0 Add1 Yes SUBD M(34+R2) Load20 Add2 No

Add3 No0 Mult1 Yes MULTD R(F4) Load20 Mult2 No


Clock F0 F2 F4 F6 F8 F10 F12 ... F304 FU Mult1 Load2 M(34+R2) Add1

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 Load2 Yes 45+R3MULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2Reservation Stations S1 S2 RS for j RS for k

Time Name Busy Op V j Vk Qj Qk0 Add1 Yes SUBD M(34+R2) Load20 Add2 No

Add3 No0 Mult1 Yes MULTD R(F4) Load20 Mult2 Yes DIVD M(34+R2) Mult1


Clock F0 F2 F4 F6 F8 F10 F12 ... F305 FU Mult1 Load2 M(34+R2) Add1 Mult2

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2 6Reservation Stations S1 S2 RS for j RS for k

Time Name Busy Op V j Vk Qj Qk2 Add1 Yes SUBD M(34+R2) M(45+R3)0 Add2 Yes ADDD M(45+R3) Add1

Add3 No1 0 Mult1 Yes MULTD M(45+R3) R(F4)

0 Mult2 Yes DIVD M(34+R2) Mult1Register result status

Clock F0 F2 F4 F6 F8 F10 F12 ... F306 FU Mult1 M(45+R3) Add2 Add1 Mult2

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2 6Reservation Stations S1 S2 RS for j RS for k


Add3 No9 Mult1 Yes MULTD M(45+R3) R(F4)0 Mult2 Yes DIVD M(34+R2) Mult1



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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6Reservation Stations S1 S2 RS for j RS for k





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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5ADDD F6 F8 F2 6Reservation Stations S1 S2 RS for j RS for k

Time Name Busy Op V j Vk Qj Qk0 Add1 No0 Add2 Yes ADDD M()–M() M(45+R3)



Clock F0 F2 F4 F6 F8 F10 F12 ... F309 FU Mult1 M(45+R3) Add2 M()–M() Mult2

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Clock F0 F2 F4 F6 F8 F10 F12 ... F301 0 FU Mult1 M(45+R3) Add2 M()–M() Mult2

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5ADDD F6 F8 F2 6 1 2Reservation Stations S1 S2 RS for j RS for k





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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5ADDD F6 F8 F2 6 1 2 1 3Reservation Stations S1 S2 RS for j RS for k




Clock F0 F2 F4 F6 F8 F10 F12 ... F301 3 FU Mult1 M(45+R3) (M–M)+M() M()–M() Mult2

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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 1 6 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5ADDD F6 F8 F2 6 1 2 1 3Reservation Stations S1 S2 RS for j RS for k





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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 1 6 1 7 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5ADDD F6 F8 F2 6 1 2 1 3Reservation Stations S1 S2 RS for j RS for k


Add3 No0 Mult1 No0 Mult2 Yes DIVD M*F4 M(34+R2)


Clock F0 F2 F4 F6 F8 F10 F12 ... F301 7 FU M*F4 M(45+R3) (M–M)+M() M()–M() Mult2

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Add3 No0 Mult1 No

4 0 Mult2 Yes DIVD M*F4 M(34+R2)Register result status


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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 1 6 1 7 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5 5 8ADDD F6 F8 F2 6 1 2 1 3Reservation Stations S1 S2 RS for j RS for k





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Instruction status Execution WriteInstruction j k Issue complete Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 5 6 Load2 NoMULTDF0 F2 F4 3 1 6 1 7 Load3 NoSUBD F8 F6 F2 4 8 9DIVD F10 F0 F6 5 5 8 5 9ADDD F6 F8 F2 6 1 2 1 3Reservation Stations S1 S2 RS for j RS for k




Clock F0 F2 F4 F6 F8 F10 F12 ... F305 9 FU M*F4 M(45+R3) (M–M)+M() M()–M() M*F4/M

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Tomasulo Loop Example

Loop: LD F0 0 R1 MULTD F4 F0 F2 SD F4 0 R1 SUBI R1 R1 #8 BNEZ R1 Loop

• Multiply takes 4 clocks• Load have cache misses

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Loop Example Cycle 0Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 Load1 NoMULTDF4 F0 F2 1 Load2 NoSD F4 0 R1 1 Load3 No QiLD F0 0 R1 2 Store1 NoMULTDF4 F0 F2 2 Store2 NoSD F4 0 R1 2 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R10 Mult1 No SUBI R1 R1 # 80 Mult2 No BNEZ R1 Loop

Register result statusClock R1 F0 F2 F4 F6 F8 F10 F12... F30

0 8 0 Qi

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Loop Example Cycle 1Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 Load1 Yes 8 0MULTDF4 F0 F2 1 Load2 NoSD F4 0 R1 1 Load3 No QiLD F0 0 R1 2 Store1 NoMULTDF4 F0 F2 2 Store2 NoSD F4 0 R1 2 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R10 Mult1 No SUBI R1 R1 # 80 Mult2 No BNEZ R1 Loop


1 8 0 Qi Load1

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Loop Example Cycle 2Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 Load1 Yes 8 0MULTDF4 F0 F2 1 2 Load2 NoSD F4 0 R1 1 Load3 No QiLD F0 0 R1 2 Store1 NoMULTDF4 F0 F2 2 Store2 NoSD F4 0 R1 2 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R10 Mult1 Yes MULTD R(F2) Load1 SUBI R1 R1 # 80 Mult2 No BNEZ R1 Loop


2 8 0 Qi Load1 Mult1

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Loop Example Cycle 3Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 Load1 Yes 8 0MULTDF4 F0 F2 1 2 Load2 NoSD F4 0 R1 1 3 Load3 No QiLD F0 0 R1 2 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 Store2 NoSD F4 0 R1 2 Store3 NoReservation Stations S1 S2 RS for jRS for k




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Loop Example Cycle 6Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 Load1 Yes 8 0MULTDF4 F0 F2 1 2 Load2 Yes 7 2SD F4 0 R1 1 3 Load3 No QiLD F0 0 R1 2 6 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 Store2 NoSD F4 0 R1 2 Store3 NoReservation Stations S1 S2 RS for jRS for k




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Loop Example Cycle 7Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 Load1 Yes 8 0MULTDF4 F0 F2 1 2 Load2 Yes 7 2SD F4 0 R1 1 3 Load3 No QiLD F0 0 R1 2 6 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 7 Store2 NoSD F4 0 R1 2 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R10 Mult1 Yes MULTD R(F2) Load1 SUBI R1 R1 # 80 Mult2 Yes MULTD R(F2) Load2 BNEZ R1 Loop



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Loop Example Cycle 8Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 Load1 Yes 8 0MULTDF4 F0 F2 1 2 Load2 Yes 7 2SD F4 0 R1 1 3 Load3 No QiLD F0 0 R1 2 6 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 7 Store2 Yes 7 2 Mult2SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k




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Loop Example Cycle 9Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 Load1 Yes 8 0MULTDF4 F0 F2 1 2 Load2 Yes 7 2SD F4 0 R1 1 3 Load3 No QiLD F0 0 R1 2 6 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 7 Store2 Yes 7 2 Mult2SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k




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Loop Example Cycle 10Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 Load2 Yes 7 2SD F4 0 R1 1 3 Load3 No QiLD F0 0 R1 2 6 1 0 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 7 Store2 Yes 7 2 Mult2SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R14 Mult1 Yes MULTD M(80) R(F2) SUBI R1 R1 # 80 Mult2 Yes MULTD R(F2) Load2 BNEZ R1 Loop


1 0 6 4 Qi Load2 Mult2

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Loop Example Cycle 11Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 Load2 NoSD F4 0 R1 1 3 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 7 Store2 Yes 7 2 Mult2SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R13 Mult1 Yes MULTD M(80) R(F2) SUBI R1 R1 # 84 Mult2 Yes MULTD M(72) R(F2) BNEZ R1 Loop


1 1 6 4 Qi Mult2

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1 2 6 4 Qi Mult2

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1 3 6 4 Qi Mult2

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Loop Example Cycle 14Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 Load2 NoSD F4 0 R1 1 3 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 Yes 8 0 Mult1MULTDF4 F0 F2 2 7 Store2 Yes 7 2 Mult2SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k



1 4 6 4 Qi Mult2

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Loop Example Cycle 15Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 Yes 8 0 M(80)*R(F2)MULTDF4 F0 F2 2 7 1 5 Store2 Yes 7 2 Mult2SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k

Time Name Busy Op V j Vk Qj Qk Code:0 Add1 No LD F0 0 R10 Add2 No MULTDF4 F0 F20 Add3 No SD F4 0 R10 Mult1 No SUBI R1 R1 # 80 Mult2 Yes MULTD M(72) R(F2) BNEZ R1 Loop


1 5 6 4 Qi Mult2

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Loop Example Cycle 16Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 Yes 8 0 M(80)*R(F2)MULTDF4 F0 F2 2 7 1 5 1 6 Store2 Yes 7 2 M(72)*R(72)SD F4 0 R1 2 8 Store3 NoReservation Stations S1 S2 RS for jRS for k



1 6 6 4 Qi Mult1

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Loop Example Cycle 17Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 Yes 8 0 M(80)*R(F2)MULTDF4 F0 F2 2 7 1 5 1 6 Store2 Yes 7 2 M(72)*R(72)SD F4 0 R1 2 8 Store3 Yes 6 4 Mult1Reservation Stations S1 S2 RS for jRS for k



1 7 6 4 Qi Mult1

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Loop Example Cycle 18Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 1 8 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 Yes 8 0 M(80)*R(F2)MULTDF4 F0 F2 2 7 1 5 1 6 Store2 Yes 7 2 M(72)*R(72)SD F4 0 R1 2 8 Store3 Yes 6 4 Mult1Reservation Stations S1 S2 RS for jRS for k



1 8 5 6 Qi Mult1

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Loop Example Cycle 19Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 1 8 1 9 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 NoMULTDF4 F0 F2 2 7 1 5 1 6 Store2 Yes 7 2 M(72)*R(72)SD F4 0 R1 2 8 Store3 Yes 6 4 Mult1Reservation Stations S1 S2 RS for jRS for k



1 9 5 6 Qi Mult1

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Loop Example Cycle 20Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 1 8 1 9 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 NoMULTDF4 F0 F2 2 7 1 5 1 6 Store2 Yes 7 2 M(72)*R(72)SD F4 0 R1 2 8 2 0 Store3 Yes 6 4 Mult1Reservation Stations S1 S2 RS for jRS for k



2 0 5 6 Qi Mult1

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Loop Example Cycle 21Instruction status ExecutionWriteInstruction j k iteration Issue completeResult Busy AddressLD F0 0 R1 1 1 9 1 0 Load1 NoMULTDF4 F0 F2 1 2 1 4 1 5 Load2 NoSD F4 0 R1 1 3 1 8 1 9 Load3 Yes 6 4 QiLD F0 0 R1 2 6 1 0 1 1 Store1 NoMULTDF4 F0 F2 2 7 1 5 1 6 Store2 NoSD F4 0 R1 2 8 2 0 2 1 Store3 Yes 6 4 Mult1Reservation Stations S1 S2 RS for jRS for k



2 1 5 6 Qi Mult1

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Tomasulo Summary

• Prevents Register as bottleneck• Avoids WAR, WAW hazards of Scoreboard• Allows loop unrolling in HW• Not limited to basic blocks (provided branch

prediction)• Lasting Contributions

– Dynamic scheduling– Register renaming– Load/store disambiguation

• Next: More branch prediction

tomasulo algorithmlecture 11: case study—ricardo/courses/advtopcompsys/material/tomasulo... ·...

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